© Independent Read/Write Addressing Permits ‘Simultaneous Reading and Writing ‘© Organized as Eight Words of Two Bits Each ‘© Fast Access Times: From Read Enable ... 15 ns Typical From Read Select .. . 33 ns Typical © 3State Outputs Simplify Use in Bus-Organized Systems © Applications: ‘Stacked Data Registers ‘Scratch-Pad Memory Buffer Storage Between Processors, Fast Multiplication Schemes description ‘The SN74172, containing the equivalent of 201 gates ‘on & monolithic chip, i a high-performance 16-bit register file organized as eight words of two bits each Multiple address decoding circuitry is used so thatthe read and write operation can be performed indepen: ently on two word locations. This provides 2 true Smmultaneous read/write capability. Basically, the file consists of two distenct sections (see Figure 1) Section 1 permits the writing of data into any two-bit word location while reading two bits of data from another location simultaneously. To provide this flexibility, independent decoding is incorporated. Section 2 of the register file is similar to section 1 with the exception that common read/write address circuitry is employed. This means that section 2 can be utilized in one of three modes: 1) Writing new data into two bits 2} Reading trom two bits 3) Writing into and simultaneously reading from the same two bits. Regardless of the mode, the operation of section 2 entirely independent of section 1 SN74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS ‘SN74172 ...N PACKAGE (ror view i 3 schematics of inputs and outputs a 107 wo TTL Devices a [SW 26M w Suc: Rag = 4 oH ‘nur ope Rigs ont logic symbolt Is Raa 2a.520, ‘This symbol iin accordance with ANSUIEEE St 91-1986 end EC Pusienton 617-12. Teas Y INSTRUMENTS, 2-569seoined TLL ‘SN74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS eee description (continued) “The three-state outputs of this register file permit connection of up to 129 compatible outputs and one Series 54/74 Hgtvogc level load to a common system bus. The outputs are controlled by the read-enable circuitry so that they Operate as standard TTL totem pole outputs when the appropriate read-enable input is low or they are placed in a Fgh impedance state when the associated reaenable input iat a high logic level. To minimize the posblity that two ditputs from separate register files will atemot to take @ common bus to opposite logic levels, the read-enable circuitry {a designed such that disable times are shorter then enable times, ‘At inputs are buffered to lower the drive requirements of the clock, read/write address, and write-enable inputs to one pormalized Series 54/74 load, and of al other inputs to onetalf of one normlized Series 64/74 toed. Functions of the inputs and outputs of the SN74172 are as shown in the following table. FUNCTION SECTION 1 SECTION 2 DESCRIPTION Binary wite address selects one of eight two-bit Write Address two, twa, 1W2 | 2W/RO, 2W/RT, 2WIR2 | OO Nocations _ When low. permits the writing of new dat Wieite Enable 16H 268 the selected word location on a positive transition of the clock input. Data at these inputs is entered on a postive transition of the clock input into the location telected by the write address inputs if the write tenable input is 1ow, Since the two sections ax independent, i is possible for both write functions Data Inputs 1DA, 108 20A, 208 to be activated with both write addresses selecting the same word location. If this occurs and the information at the data inputs is not the same for both sections {ie,, 10A#2DA and/or 0B #208) the low-level data will predominate in each bit and be stored. ‘common with | Binary write address selects one of eight worit ae ee ‘write address | word locations. _ ‘When read enable is low, the outputs assume the Read Enable 16h 26 levels of the data stored in the location selected by ead address inputs. When read enable is high, the ‘sociated outputs remain in the high impedance fate and neither significantly load por drive the Data Outputs 1A, 108 eee ines to which they are connected, The positive going transition of the clock input will enter new data into the addressed location if the write enable input is tow. The clock is ‘common to both sections Clock cK —— SSeS 2-570 » TEXAS. INSTRUMENTS$N74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS ovat or LINE FOSLINE euive vo TUNE on 22!_} vemurrtexen ‘MuLTipcexen to | o ‘ ! 8 root $ i 8 3 een eee eee 4 a 7 SECTION? 1 a g ! REGISTER, | e EF 2 | i 2 7 z \ I g é ! | . ! ovat mee | | sume rosie eunero rune | | 208 DEMULTIPLEXER ‘mucrevexen 20g 200 208 "aponess warremeao wm Fiaune 1 2571 TEXAS. INSTRUMENTSPC Board Considerations Power Planes‘SN74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS ‘switching characteristics, Voc = 5 V, TA = 28°C, RL = 4002 TTL Devices a Ta PARAMETER const tos [MM T¥P max]uner] Tiacinon dock Reena Ey ma Propoaton delay tne, ow ih lee ouip fram rad ic Bs Propoostion deby tine, Rah -owtee output from Fed et cu =s00r. | Propagation delay time, low to-hightevel output from clock ar 3 50 Propegation delay time, high-to-lowlevel output from clock as s0|™ ‘Bator enable re 1 Fight 1490 1PZL__ Output enable time to low level 7% 30] ™ iid Outpt bl i rr igh na = 8oF 6% TeLZ vipat dase ie from low Teve ‘Sen Figuee 2 720] ™ PARAMETER MEASUREMENT INFORMATION neu steer ‘eure para ineur twugncever DATA) swowuevee DATA chaste inurs 1 ome i —— von ours 1 Tea i You fein} von ourrur 7sv ‘SMITCHING TIMES FROM CLOCK INPUT VOLTAGE WAVEFORMS Flaune 2 TEXAS. % 2-673 INSTRUMENTSSN74172 16-BIT MULTIPLE-PORT REGISTER FILE WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION ean av ENABLE 1sv Sev iweur joa —- ov TT got stan waveronm1 — | 81 closed, isv | Saco 1sv pu act rest bon} wate OY eRe waveronn? stom, Way a ely Seen er Seeoaa ZE'SY Stone [ENABLE AND DISABLE TIMES FROM READ ENABLE VOLTAGE WAVEFORMS FIGURE 2 (continued) seoineg of TEXAS. » 2874 INSTRUMENTS