An Analog Leaf Cell for Analog Circuit Design
D. W. Parent, E. J. Basham, S. Ng, and P. Weil
Department of Electrical Engineering
San Jose State University
San Jose CA 95192-0084
dparent@email.sjsu.edu
ABSTRACT
In this paper, we describe an Analog Leaf Cell (ALC) that was
created to facilitate teaching analog circuit design to
senior/graduate EE. It is intended as a teaching tool to
introduce the student to the design, fabrication and test
cycle in a simple yet complete manner.
1. Introduction
The Analog Leaf Cell (ALC ) is a sea-of-gates semi-custom
IC design approach that reduces design and fabrication time.
The design time is reduced because the transistors are pre-
placed and the novice designer only has to route one metal
layer, and fabrication time is reduced because the transistors
are pre-fabricated and only one metal layer has to be
processed to complete the manufacture of an IC design.
Since analog designs such as current mirrors and mixed
signal designs such as current steered DACs are easy to test,
the test/verification time is reduced as well. Reducing the
design, fabrication and test time of an IC design reduces the
cost of offering this kind of experience to students, and allow
a design (Cadence Design Systems CAD tools)/fabricate/test
experience to be completed in one semester.
The main reason for offering this kind of design, fabrication
and test experience to all EE students is to make sure that our
students can compete for jobs in a global economy. Since
engineers based in the US are expensive, we have to make
sure that they have skills that are in demand and cannot be
supplied at a lower cost. A graduating engineer that has seen
a product go through a complete cycle of design, fabrication,
test will be better prepared for careers as design, verification,
applications, product or process engineers. If our students
are better prepared they will need less on the job training
before they become profitable for their company. This kind
of real world experience will require the students to
demonstrate good teamwork skills to finish a real world IC
design project, as well as good written skills to properly
document their project results (i.e. application note for their
IC design).
We envision the ALC environment being used by our
required senior level course in analog electronics, our CMOS
analog VSLI senior/graduate course, and our graduate analog
design course.
Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05)
0-7695-2374-9/05 $20.00 © 2005 IEEE
2. Analog Leaf Cell Design Flow
The designer first uses hand calculations to roughly size the
transistors to meet specification. Each transistor is 14
x14µm wide and can be wired in parallel or series to meet
the W/L ratio or transistor sizing determined by the hand
calculations. Of course not all ratios or sizes are possible,
and so once a ratio or transistor width is calculated, the
closest possible match is selected and then the new W/L ratio
or transistor size is checked to make sure it is still possible to
meet specification. The design is entered into schematic
capture and simulated using a Bsim4 model.
Once the design’s schematic view has been verified to meet
specification, the designer uses a bubble schematic (Figure
1) to make a layout plan. Each empty bubble represents a
connection that can be made between the wires that run
vertically and the wires that run horizontally. Each solid
bubble is a hard-wired connection. Transistor gates are
connected to an individual wire running horizontally by a
short wire running vertically. Since there are two sets of
transistors with gates connected to the same horizontal bus,
there are 5 horizontal bus lines for P transistors (0-4) and 5
horizontal bus lines for N transistors (5-9). Once the layout
plan is completed, the design is ready to be input into a
layout view.
The layout view of the ALC can be seen in Figure 2. There
are 8 banks of 10 N transistors (bottom) and 8 banks of 10 P
transistors (top). They are laid out in a predetermined, but
not connected manner in order to guide the student and
reduce the level of required layout for a functional design.
The horizontal lines are the METAL1 the vertical lines are
POLY.
Two banks of PMOS transistors and two banks of NMOS
transistors have their gates tied together with poly-silicon to
facilitate current mirror design. Connections are made by
simply adding METAL1 between two METAL1 layers.
Design rule checking and layout vs. schematic checks are
then done. Once the layout view passes these checks the
extracted view is simulated to verify that the circuit still
meets specification. The layout view is then added to a pre-
laid out pad-frame and re-verified. The circuit can be
fabricated through MOSIS using the AMI16 NWELL
technology, or by our in house PWELL technology[1]. If
our process is used, then it is possible to design fabricate and
 test the circuit in one semester because the CMOS layers
PWELL to CONT have been prefabricated during a previous
semester[2]. The circuits are tested with a probe card
consisting of 40 pins.
Figure 1: Bubble Schematic of ALC.
3. Analog Leaf Cell Design Environment
The ALC design environment consists of a well-crafted
tutorial[3], the NCSU CDK (with modifications), and 40 sun
UNIX stations and a sunfire 280 server running
IC446. The NCSU CDK can be run in IC50 as well, but
global pins will only simulate properly in the
analog_extracted (not extracted) view.
The tutorial introduces the student to the ALC design
environment and also shows the student step by step how to
use the Cadence Design Systems Virtuoso CAD tool. The
tutorial consists of a current mirror design and Operational
Transconductance Amplifier (OTA) design examples.
The NCSU kit was modified to allow the prune command to
work. The prune command deletes unconnected transistors
so LVS can pass.
5. Results/Discussion
We have used the ALC design environment in our
senior/graduate level CMOS design/processing course.
Current mirrors, class AB amplifiers and OPAMPS were
designed very quickly by students. Even students without a
circuits background (MatE) were able to design simple
current mirrors using this environment.
Proceedings of the 2005 IEEE International Conference on Microelectronic Systems Education (MSE’05)
0-7695-2374-9/05 $20.00 © 2005 IEEE
Figure 2: Layout view of the ALC.
5. Summary
We have developed an analog design environment consisting
of a semi-custom design flow where students hand stitch
basic analog circuits together to learn analog design. We
will introduce this environment to a required electronics
design class at SJSU in the future and make it available to
other universities as well.
ACKNOWLEDGMENT
We gratefully acknowledge Cadence Design Systems for the
extensive resources we used to develop our program. We
also thank Linda Schnell of Cadence Design Systems for her
valuable input to this work.
REFERENCES
[1] D. Parent, Y. Dessouky, S. Gleixner, G. Young and E.
Allen, “The Microelectronics Process Engineering
Program at SJSU,” Proceedings of the 14th Biennial
IEEE UGIM Symposium,” Richmond, VA, pp. 128-134,
(June 2001).
[2] D. Parent, E. Basham, Y. Dessouky, S. Gleixner, G.
Young, E. Allen, “Improvements to a Microelectronic
Design and Fabrication Course”, IEEE Transactions on
Education, accepted for publication September 2004.
[3] www.engr.sjsu.edu/dparent/ICGROUP/analogleafcell.pdf