740 IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO.

5, MAY 1996

Multiplexer/Demultiplexer IC Technology for 100 Gb/s Fiber-Optic

Transmission
R. Pullela, U. Bhattacharya, S. T. Allen, and M. J. W. Rodwell

Abstract—We report a new integrated circuit for multiplexing II. SYSTEM CONFIGURATION
and demultiplexing at rates of 100 Gb/s. In transistor multi-
plexer/demultiplexer circuits, the operating data rate is limited by The present paper concerns design and initial evaluation of
transistor bandwidth. The demonstrated circuit, which uses tera- 100 Gb/s mux/demux circuits. While a full 100 Gb/s fiber
hertz Schottky diodes, readily attains the necessary bandwidths. transmission system remains to be demonstrated, the receiver
The IC, based in the diode nonlinear-transmission line (NLTL) configuration (Fig. 1) must be considered to understand the
technology, consists of an array of four sample-hold gates driven mux/demux design. The photodetector output is amplified
by NLTL strobe generators. To permit use in multiplexing, the
sample-hold gates use a six-diode configuration with 150 GHz by HEMT traveling wave amplifiers. The signal is passed
output bandwidth. Initial measurements with simple data patterns through a 100 Gb/s Nyquist filter GHz low-pass filter)
at 104 Gb/s are demonstrated. to bandlimit noise. The signal is passed through a linear de-
multiplexer IC consisting of four synchronized sampling gates
clocked by a 25 GHz, four-phase clock – regenerated
I. INTRODUCTION from the 100 Gb/s data. The diode bridges generate four
parallel analog sampled data streams [3]. Each data stream
F IBER-OPTIC data transmission has evolved rapidly to 10
Gb/s and 40 Gb/s time-division-multiplexed (TDM) sys-
tems. Because of the perceived limits on electronic switching
is passed through a 25 Gb/s Nyquist filter and amplifier to a
25 Gb/s transistor decision circuit, where the analog samples
component bandwidths, present research at higher data rates are restored to binary levels. A similar system is used for
has focused on wavelength-division-multiplexing or TDM multiplexing.
using optical switching.
As it leads to lower cost and a more compact system, 100 III. CIRCUIT DESIGN
Gb/s TDM with electronic components (integrated circuits) is
The mux/demux requires an array of diode “sample-
desirable. Although a substantial challenge, 100 Gb/s TDM
hold” (sample-and-Nyquist-filter) gates. The sample-hold
fiber-optic transmission is feasible using electronic amplifica-
mux/demux configuration was first demonstrated at 480
tion and multiplexing. Optical fiber dispersion can be counter-
Mb/s in CMOS by Hu et al. [4]. A nonzero sampling
acted by dispersion compensation while Erbium-doped-fiber
aperture time is equivalent to a filter with transfer function
(EDFA) optical preamplifiers will provide adequate receiver
this response is incorporated into
sensitivity. For components operating at the data rate (100
the design of the 100 Gb/s Nyquist filter; 100 Gb/s data has
Gb/s), bandwidths greater than –70 GHz are required.
a bit period of 10 ps. A 5 ps aperture time is thus readily
Most required components have been demonstrated, including
tolerated. Diode sampling bridges gated by (diode) NLTL
110 GHz bandwidth, photodetectors [1], and 70
pulse generators attain subpicosecond aperture times [5], [6]
GHz electro-optic modulators. We have reported elsewhere
and have bandwidths far in excess of that required here, but
[2] HEMT traveling-wave amplifiers with 98 GHz bandwidth.
such circuits must be modified before use in multiplexers.
Critical missing elements are 100 Gb/s multiplexers and
Conventional sampling bridges used in microwave instru-
demultiplexers, and 27 Gb/s transistor multiplexers [3] should
ments have high input and low output (sampled or downcon-
soon evolve to 40 Gb/s rates. Large improvements in device
verted signal) bandwidth as needed for repetitive sampling in
bandwidths are necessary for multiplexing at rates of 100
oscilloscopes. The switch used in the mux/demux must have
Gb/s and beyond, if present transistor circuits are to be
input and output bandwidths –70 GHz. Further, the off-
used. We demonstrate here a new multiplexer/demultiplexer
state transmission of the switch should be small to minimize
(mux/demux) circuit using Schottky diodes, with cutoff fre-
crosstalk between the multiplexed channels. Wide diode bridge
quencies of few terahertz, as the major components. With
output bandwidths are obtained through use of transistor or
present diode nonlinear-transmission-line (NLTL) technology,
transformer strobe coupling networks, but such techniques are
it is possible to build mux/demux circuits for data rates higher
not scalable to 100 Gb/s. Two-diode (and four-diode) sampling
than 100 Gb/s.
bridges [Fig. 2(a)] contain a capacitor which both couples
the strobe pulse to the bridge and serves as the hold capacitor.
Manuscript received May 16, 1995; revised September 15, 1995. This work
was supported by the ARPA Thunder and Lightning program. The output circuit is loaded by a high resistance. While
R. Pullela, U. Bhattacharya, and M. J. W. Rodwell are with the Department a large is necessary to minimize off-state transmission,
of Electrical and Computer Engineering, University of California, Santa the capacitor’s discharge time limits the sampled output
Barbara, CA 93106 USA.
S. T. Allen is with Cree Research Inc., Durham, NC USA. bandwidth to at most a few MHz. In a six-diode NLTL-
Publisher Item Identifier S 0018-9200(96)03398-7. gated bridge [Fig. 2(b), (c)], both requirements are realized
0018–9200/96$05.00  1996 IEEE
IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 5, MAY 1996
(a)
(b)
Fig. 1. Block diagram of a 100 GB/s fiber-optic receiver (a) and of the
diode demultiplexer (b).
by switching out of the signal path during the sampling
event. A large minimizes the off-state transmission without
degrading the output bandwidth. Input and output bandwidth
can be several hundred GHz.
The strobe pulse for the diode bridge is generated by an
NLTL pulse generator, which is a transmission line period-
ically loaded by reverse biased diodes. The reverse biased
diodes have a voltage dependent capacitance. The variable
diode capacitance introduces a desired reduction in propa-
gation delay with increasing reverse bias, resulting in the
reduction in fall time of the waves propagating on the NLTL
[5]. In the present design, the 1.3 ps wavefront at the NLTL
output is differentiated into a 4 ps FWHM strobe impulse.
Circuit simulations predict a 3–4 ps aperture time and a
110–150 GHz output bandwidth, well in excess of that required
for 100 Gb/s operation.
To fabricate the diodes, an buried contact layer and
an diode active layer are grown on semi-insulating GaAs
substrate. Ohmic contacts are formed to the layer, and
device areas are defined by a proton isolation implant. Schottky
contacts are formed where the deposited Ti/Pt/Au metal layer
overlays the unimplanted layer [6].
The on–off impedance ratio of the bridge is the signal
frequency divided by the diode cutoff frequency. The diodes
must therefore have high cutoff frequencies, small junctions
areas, and small pad parasitics. The bridge uses air-bridge-
contacted Schottky diodes of area and 2.5 THz
cutoff frequency [6].
IV. LAYOUT
Fig. 3 shows the layout of the four-channel demultiplexer
IC. The four-channel demultiplexer IC consists of four single
channel units with the length of transmission lines on the clock
and data adjusted, so that the desired timing difference between
741
(a)
(b)
(c)
Fig. 2. (a) Two-diode sampling bridge and simplified model showing the
output RC charging network. (b) Six-diode switch and its simplified model.
(c) One channel of four of the diode mux/demux IC.
the different channels is achieved. Because of the short
ps aperture time of the bridge output, any parasitic layout
capacitance or inductance effects performance. The circuit
layout must be compact and must maintain the integrity of
on-chip ground plane.
The single channel unit measures and
has a dc power consumption of 0.2 W. The strobe input to the
NLTL is a 5 V p-p sinusoidal signal at 25 GHz into a 50
termination. The input to the bridge is 1 V p-p signal while the
output is 250 mV p-p. The four-channel demultiplexer requires
a 4 V p-p signal at the 100 Gb/s input as this is attenuated
by the resistive matching circuit (Fig. 3) and then input to the
four bridges.
On-wafer interference between the four 5 V NLTL strobe
(clock) signals and the mV data is a major difficulty.
For the demultiplexer, the clock harmonics at 25, 50, and 75
GHz are beyond the bandwidth of the output Nyquist filters
and will be eliminated. Clock interference is relevant in the
multiplexer and should be minimized. In addition to fabrication
742
Fig. 3. Layout of four-channel demultiplexer IC.
Fig. 4. Photomicrograph of a section of four-channel demultiplexer IC.
of the four-channel demux IC’s, single-channel mux/demux
IC’s were fabricated. With each single channel IC having only
one NLTL clock line, and a much more compact layout than
the four-channel IC interference is reduced. A four-channel
mux/demux can be constructed from a hybrid assembly of
four single channel units.
V. TESTING
Testing the mux/demux circuits is difficult because of the
wideband switch outputs and the absence of a bit-error-rate-
test set (BERT) at 100 Gb/s. Full testing of the demultiplexer
requires generation of 100 Gb/s pseudorandom bit streams
(PRBS) by the 100 Gb/s diode multiplexer. This has not
yet been performed. For initial switch and demultiplexer
evaluation, sinusoidal input test signals are used. A 50 GHz
sinusoid corresponds to a pattern at a 100 Gb/s data
rate, while and streams are emulated by
positive and negative dc inputs. Available signal generators
forced testing at 104 Gb/s. The wideband signal generated
at the output of the mux/demux cannot be observed on
commercially available (sampling) oscilloscopes due to their
limited bandwidth (50 GHz). Two tools were used to mea-
sure the output waveforms. Some single channel IC’s were
fabricated with integrated on-wafer sampling circuits. While
these provide wideband measurements [5], the close proximity
IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 5, MAY 1996
Fig. 5. (a) 26 GB/s 1111 . . . output of a single channel IC for a 104
GB/s 1010 . . . input, measured by an on-wafer sampling circuit, with clock
interference nulled. (b) 26 GB/s 1111 . . . output of a single channel IC for a
104 GB/s 1111 . . . input, measured by an active probe.
Fig. 6. 1010 . . . output pattern of the single channel IC for a 39 GHz input.
of the sampling circuit to the mux/demux circuit results in
spurious coupling between the sampling circuit and the strobe
NLTL. To obtain measurement uncorrupted by clock coupling
in the instrumentation, the mux/demux circuits were also
tested by NLTL-based active probes [5]. The active probes
limit waveform measurements to ps resolution due their
smaller bandwidth.
Fig. 5 shows demultiplexed 26 Gb/s output patterns
of a single channel IC for 104 Gb/s and input
patterns. The latter measurement, taken by an active probe,
indicated dB clock interference. The aperture time is
3 ps (Fig. 5a), and the output bandwidth is 150 GHz. Fig.
6 shows the demux output at 39 GHz input, generating an
alternating output. The single channel IC was tested
with such sinusoidal data inputs up to 60 GHz (120 Gb/s).
While testing at higher data rates is limited by the lack of
test equipment, the measured switch aperture time indicates
sufficient bandwidth for at least 150 Gb/s operation.
Fig. 7 shows the four-channel demux output on one of the
channels for a 39 GHz sinusoidal input. In addition to the
expected output pattern, clock interference at 26 GHz
is observed. This clock coupling does not impair demultiplexer
operation as the clock interference is eliminated by the 26
Gb/s (13 GHz) Nyquist filter. Such clock interference cannot
be tolerated in the multiplexer.
The interchannel timing of the demultiplexer was evaluated
by a sampling experiment. In this measurement a sinusoidal
IEEE JOURNAL ON SOLID-STATE CIRCUITS, VOL. 31, NO. 5, MAY 1996
Fig. 7. 1010. . . output pattern on one of the channels of the four-channel
demultiplexer.
Fig. 8. Output on channels 1 and 4 of the demux for a sinusoidal RF input
at 52 GHz + 1 MHz; clock frequency is 26 GHz.
data input signal was offset from 52 GHz (a 104 Gb/s
pattern) by 1 MHz. The resulting output patterns of the four
channels, after the 26 Gb/s Nyquist filter, correspond to sam-
pled versions of the input 104 Gb/s signal, with each channel
functioning as an individual sampling circuit. The input RF
signal is downconverted in frequency to 1 MHz, with phase
differences between the sampled signals on the four channels
corresponding to the interchannel timing differences. The
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measured timing difference between the signals on channel one
and four is ps (Fig. 8), which is very close
to the desired 10 ps timing differnce between the channels.
Similar interchannel timing is observed for the other channels.
We have demonstrated first results with diode IC’s for 100
Gb/s transmission; required bandwidths are readily attained.
The single channel mux/demux IC and the four-channel de-
multiplexer IC have been built and tested with simple data
patterns at 104 Gb/s. To permit full system-level 100 Gb/s
experiments with pseudorandom data streams, four-channel
multiplexer, and clock recovery circuit have been designed
and are currently in fabrication. The six-diode gates can
also have impact on high-speed instrumentation applications
requiring high output bandwidths, including harmonic mixers
for spectrum analysis, bit-error-rate test sets, and multiplexed
A-D converters.
REFERENCES
[1] Y. G. Wey, K. S. Giboney, J. E. Bowers, M. J. W. Rodwell, P.
Silvestre, P. Thiagarajan, and G. Y. Robinson, “108-GHZ GaInAs/InP
p-i-n photodiodes with integrated bias tees and matched resistors,” IEEE
Photonics Tech. Lett., vol. 5, no. 11, Nov. 1993.
[2] J. Pusl, B. Agarwal, R. Pullela, L. D. Nguyen, M. V. Le, M. J.
W. Rodwell, L. Larson, J. F. Jensen, R. Y. Yu, and M. G. Case,
“Capacitive-division travelling-wave amplifier with 340 GHz gain-
bandwidth product,” in Proc. 1995 IEEE Microwave and Millimeter-
Wave Monolithic Circuits Symp., Orlando, FL, May 15–16, 1995.
[3] K. Runge, D. Daniel, J. L. Gimlett, R. B. Nubling, R. L. Pierson, M.
F. Chang, K. C. Wang, and D. M. Chen, “A 27 Gb/s AlGaAs/GaAs
HBT 4:1 multiplexer IC,” 1991 IEEE GaAs IC Symp., Monterey, CA,
Oct. 20–23, 1991.
[4] T. H. Hu and P. R. Gray, “A monolithic 480 Mb/s parallel
AGC/decision/clock-recovery circuit in : 12 m
 CMOS,” IEEE
Solid-State Circuits, vol. 28, no. 12, Dec. 1993.
[5] M. J. W. Rodwell, S. T. Allen, R. Y. Yu, M. G. Case, M. Reddy, E.
Carman, J. Pusl, M. Kamegawa, Y. Konishi, and R. Pullela, “Active
and nonlinear wave propagation devices in ultrafast electronics and
optoelectronics,” Proc. IEEE, vol. 82, no. 7, pp. 1037–1058, July 1994.
[6] U. Bhattacharya, S. T. Allen, and M. J. W. Rodwell, “DC-725 GHz
sampling circuits and subpicosecond nonlinear transmission lines using
elevated coplanar waveguide,” IEEE Microwave Guided Wave Lett., vol.
5, no. 2, pp. 50–52, Feb. 1995.