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Analog Communication
Laboratory
Phase Locked Loop (PLL)
Basics
1
PLL Block Diagram
Basic parts
2
Basic Components
Phase detector
Transfer function: KΦ [V/radians].
Implemented as: four quad multiplier, XOR
gate, state machine.
Basic Components
Voltage controlled oscillator (VCO).
Frequency is the first derivative of phase.
Transfer function: KVCO/s [radians/(V•s)]
3
Basic Components
Low pass filter
Removes high frequency components
coming from the phase detector.
Determines loop order and loop dynamics.
θo K Φ KVCO F ( s )
Transfer function : =
θ i s + K Φ KVCO F ( s )
θe s
Error function : =
θ i s + K Φ KVCO F ( s )
Loop gain : K Φ KVCO F ( s )
s 2θ i
Steady state error : lim sθ e =
s →0 s + K Φ KVCO F ( s )
4
Selecting your filter
No filter.
First order system.
Simplicity and stability.
Steady state error and bandwidth are
tightly linked.
Useful if you have a huge bandwidth
available and no other constraints.
Example: harmonic locked oscillators
5
Selecting your filter
One pole one zero RC filter
Small gain→
gain→ small damping
As gain increases damping first decreases but
then increases again.
Good transient response, good bandwidth easy
to design.
1
p1 =
2π ( R1 + R2 )C
1
z1 =
2πR2C
( sτ 2 + 1)
KVCO K Φ
H ( s) =
(τ 1 + τ 2 )
(1 + KVCO K Φτ 2 ) KVCO K Φ
s +s
2
+
(τ 1 + τ 2 ) (τ 1 + τ 2 )
KVCO K Φ
ωn =
τ1 + τ 2
1 ⎛ 1 ⎞
ξ = ωn ⎜⎜τ 2 + ⎟⎟
2 ⎝ K VCO K Φ ⎠
τ 1 = R1C1
τ 2 = R2C1
s 2 + 2ξω n +ωn2
6
Second order system
Parameters:
Natural frequency: ωn
Damping coefficient: ξ
Related to:
How fast your system should settle.
How much overshoot you are willing to
tolerate.
Root Locus
Single pole low pass filter
7
Root Locus
One pole one zero LP filter
Acquiring Lock
Some important parameters:
Capture/lock-
Capture/lock-in range: range of frequencies over
which the PLL is able to acquire lock given that it
was initially unlocked.
Tracking/Hold-
Tracking/Hold-in range: range of frequencies over
which the PLL can track and follow the input
signal once it has acquired locked.
8
Acquiring Lock
Pull-in range: frequency range over which
the PLL will always lock.
Pull-out range: maximum frequency step
that can be applied without losing lock.
Tracking Range
Basically given by the loop gain and phase
detector range.
Δω LOCK = K Φ KVCO (Phase detector range in rad)
9
Capture Range
Involves a non-linear process where
the linear model breaks down.
Transient from Transient from
fi=1.0MHz fi=1.0MHz
Capture Range
Non-linear response
10
Capture Range
What is going on?
PLL Simulation
The F(s) is
SPICE model simply an RC;
A=1 (no gain)
Again, as in O/A
“summing node” in model, this block is
the O/A-like model indeed a multiplier
of PLL (see SPICE deck)
11
PLL simulation
Time domain simulation (SPICE): very
small time step required (long
simulation time).
Frequency domain simulators: initial
conditions may be difficult to set, but it
is very efficient (short simulation time).
PLL Applications
FM demodulator.
FM Modulator
12
PLL Applications
Frequency Synthesis
13
Simple Design Example
VCO range of 450KHz ± 10KHz ensure
the incoming signal is within the
capture and tracking range of a
MC14046.
Assume a 6KHz square wave audio
signal that shifts the VCO to 457.5KHz
and 442.5KHz during the positive and
negative cycle.
14
Final Comments
PLL model usually assumes linearity.
VCO tuning range is usually non linear.
Phase detector can also be non linear.
Bandwidth is usually limited to about
one tenth of your reference frequency.
Leave enough margin for part to part
variations.
15