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The project presents the detailed information about

interfacing motherboard with the peripherals such as keyboard,
LCD and LED display via ATMEL 89C51.

It is practically inefficient to connect the PIU’s of

peripherals to the MPEG - 2 DECODER IC which is present in
motherboard. Hence a user interface board is used which
provides the connection between the motherboard and the
peripherals using only two signal lines Rx and Tx.

The motherboard will access one of the various RF signals

from the satellite to which the dish is oriented which is installed
in the receiver station. The selection of the specific signal is done
by diseq2.0 switch which is a mux that receives control signal
from motherboard through keyboard. Details of the signal
received is displayed on LCD and the status of the motherboard
is indicated by LED. Due to complexities involved in designing
motherboard, the motherboard is replaced by PC with VB


Audio Audio
Video Right left L band signal

Audio Video

Tuner and

PEG 2 decoder

Power Supply Digital data

Gnd Rx Tx
User Interface Board

yboard LCD Status Indicator

Front Panel Board


“Integrator Receiver Decoder” A satellite receiver used to

pick-up a radio-frequency signal and convert digital information
transmitted in it. When the information is beamed from the
satellite, it is collected by the satellite dish and sent to the
receiver. The information is then decoded and decompressed,
allowing a subscriber to view programming.

IRD is commonly found in radio, television, cable and

satellite broadcasting facilities, the integrator receiver decoder is
generally used for the reception of contribution feeds that are
intended for re-broadcasting. The IRD is the interface between a
receiving satellite dish or Telco networks and a broadcasting
facility video or audio infrastructure.

An integrated receiver/ decoder {IRD} is an electronic

device used to pick up a radio frequency signal and convert
digital information transmitted in it. Commonly found in radio,
television , cabel and satellite broadcasting facilities, IRD is
generally used for the reception of contribution feeds that are
intended for re- broadcasting. The IRD is the interface between a
receiving sattelite dish or telco networks and a broadcasting
facility video/audio infrastructure. IRD is an enhanced version of
set-top box {STB}.

STB functions were limited to only two types of decoding,

i.e audio and video decoding facilitated with only one audio and
video connection. For research purpose IRD was introduced with

some additional features such as data decoding which is
accomplished using asynchronous serial interface {ASI}. It has
two audio/video connections and has better performance in
terma of Eb/No and can receiv more than one RF inputs.

Our project aims at developing user interface board for

commercial IRD. It involves communication between various
peripherals and mother board through micro controller chip . It
includes receiving one signal among the several and displaying
details regarding the received signal on the corresponding
peripheral device. Due to the complexities involved in designing
mother board, the mother board is replaced by a PC with VB

IRD takes L band signal as input. L band frequency range is

950MHz to 2150MHz. The received L band signal is down
converted and demodulated. The output of demodulator is
MPEG2 digital data. This MPEG2 digital data is given to MPEG2
decoder. MPEG2 decoder decodes compressed digital data into
uncompressed digital data. MPEG2 decoder internally contains
digital to analog converter which converts uncompressed digital
data into analog composite video and stereo audio signals. IRD
contains power supply unit which provides supply to all other
units present in system. It takes AC as well as DC as power unit.
IRD has user interface board which acts as interface between
MPEG2 decoder (CPU) and front panel board. Front panel board
has keys, LCD and status indicator.

3.1 MPEG :

MPEG which stands for Moving Picture Experts Group, is

the name of a family of standards used for coding audio-visual
information (e.g., movies, video, music) in a digital compressed
format. The major advantage of MPEG compared to other video
and audio coding formats is that MPEG files are much smaller for
the same quality. This is because MPEG uses very sophisticated
compression techniques.


The terms tuner and receiver are used loosely, and it is

perhaps more appropriately called an ATSC receiver, with the
tuner being part of the receiver. The receiver generates the
audio and video (AV) signals needed for television, and performs
the following tasks: demodulation, error correction, transport
stream demultiplexing, decompression, analog to digital
conversion, AV synchronization, and media reformatting to
match what is optimal input for one’s TV.
Demodulation means that the signal that is pulled off the
airways is transformed into a usable signal that your TV set can
use to display quality images and quality sound.



User Interface Board

Keyboard LCD Status Indicator

Front Panel Board

To design user interface board for IRD :

This user interface board reduces complexity involved in

interfacing front panel with motherboard. User interface board is
required because decoder (CPU) IC does not have free PIO’s for
interfacing into front panel. The communication between front
panel and user interface board is parallel in nature and for user
interface board to decoder is serial. This user interface board is
based on 8051 microcontroller. User interface board recognizes
key being pressed at front panel and it will pass that information
to motherboard. Motherboard sends information (status) to front
panel through this user interface board.

Instead of motherboard we are interfacing it to PC with the

help of Visual Basic application.


1. Used in organization for reception of satellite signal

2. Used in relay transmitters

3. Used for decoding data content received from satellite

4. Direct broadcasting satellite (DBS) television applications like

Direct TV or ASTRA.

5. Fixed service satellite (FSS) applications like VideoCipher,

Digicipher or PowerVu

6. Digital audio radio satellite (DARS) applications like XM


Radio and Sirius Satellite Radio

7. Digital audio broadcasting (DAB) applications like Eureka 147

and IBOC

8. Digital video broadcasting (DVB) application like DVB-T and



The AT89C51RB2/RC2 is a high-performance Flash version

of the 80C51 8-bit microcontrollers. It contains a 16K or 32K
Bytes Flash memory block for program and data. The Flash
memory can be programmed either in parallel mode or in serial
mode with the ISP capability or with software. The programming
voltage is internally generated from the standard VCC pin.

The AT89C51RB2/RC2 retains all features of the 80C52

with 256 Bytes of internal RAM, a 9-source 4-level interrupt
controller and three timer/counters. In addition, the
AT89C51RB2/RC2 has a Programmable Counter Array, an XRAM
of 1024 Bytes, a Hardware Watchdog Timer, a Keyboard
Interface, an SPI Interface, a more versatile serial channel that
facilitates multiprocessor communication (EUART) and a speed
improvement mechanism (X2 mode). The Pinout is the standard
40/44 pins of the C52. The fully static design reduces system
power consumption of the AT89C51RB2/RC2 by allowing it to
bring the clock frequency down to any value, even DC, without
loss of data.

The AT89C51RB2/RC2 has 2 software-selectable modes of

reduced activity and 8-bit clock prescaler for further reduction in
power consumption. In Idle mode, the CPU is frozen While the

peripherals and the interrupt system is still operating. In power-
down mode, the RAM is saved and all other functions are
inoperative.The added features of the AT89C51RB2/RC2 make it
more powerful for applications that need pulse width modulation,
high speed I/O and counting capabilities such as alarms, motor
control, corded phones, and smart card readers.


Table 4.1: Memory size of different ATMEL memory



Fig 4.1: Block diagram of AT89C51

Fig 4.2: Pin configuration OF 89C51

Symbo PDIP I/O Name and Function
ALE 30 I/O Address Latch Enable: Output pulse for
latching the low byte of the address during an
address to the external memory. In normal
operation, ALE is emitted at a constant rate of
1/6 the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE
pulse is skipped during each access to external
data memory.

I External Access enable: must be

31 externally held low to enable the device to fetch
code from external program memory locations
0000H to FFFFH. If is held high, the device
executes from internal program memory unless
the program counter contains an address
greater than 0FFFH

P0.0 I/O Port 0: Port 0 is an 8-bit open-drain,

- 39-32 bidirectional I/O port. Port 0 pins that have 1s
P0.7 written to them float and can be used as high
impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses
to external program and data memory. In this
application, it uses strong internal pull-ups when
emitting 1s.

P1.0 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port

- 1-8 with internal pull-ups. Port 1 pins that have 1s
P1.7 written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.
(See DC Characteristics: IIL). The Port 1 output
buffers can sink/source four TTL inputs. Port 1
also receives the low-order address byte during
ROM verification.

P2.0 21-28 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port

- with internal pull-ups. Port 2 pins that have 1s
P2.7 written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will
source current because of the internal pull-ups.
(See DC Characteristics: IIL). Port 2 emits the
high order address byte during fetches from
external program memory and during accesses
to external data memory that used 16-bit
addresses (MOVX @ DPTR). In this application,
Port 2 uses strong internal pull-ups when
emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ Ri [i
= 0, 1]), 12Port 2 emits the contents of the P2
Special Function Register.
Port 2 also receives the high-order bits and
P3.0 10-17 I/O Port 3: Port 3 is an 8-bit bidirectional
- I/O port with internal pull-ups. Port 3
P3.7 pins that have 1s written to them are
pulled high by the internal pull-ups
and can be used as inputs. As inputs,
10 Port 3 pins that are externally pulled
11 I low will source current because of the
13 O internal pull-ups. (See DC
14 I Characteristics: IIL). Port 3 also serves
15 I the special features of the
16 I IS80LV51/31, as listed below:
17 I RxD (P3.0): Serial input port.
O TxD (P3.1): Serial output port.
O (P3.2): External interrupt 0.
(P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
(P3.6): External data memory write
(P3.7): External data memory read

29 O Program Store Enable: The read strobe

to external program
memory. When the device is executing
code from the external
program memory, is activated twice
each machine cycle
except that two activations are
skipped during each
access to external data memory. is
not activated during
fetches from internal program memory.

RST 9 I Reset: A high on this pin for two machine

cycles while the
oscillator is running, resets the device. An
internal MOS resistor
to GND permits a power-on reset using
only an external
capacitor connected to Vcc.

XTAL 1 19 I Crystal 1: Input to the inverting oscillator

amplifier and input

to the internal clock generator circuits

XTAL 2 18 O Crystal 2: Output from the inverting

oscillator amplifier.

Vcc 40 I Power Supply: This is the power supply

voltage for operation.

GND 20 I Ground: 0V reference.

Table 4.2 : Pin description


The Atmel 80C51 Microcontrollers implement two general

purposes, 16-bit timers/counters. They are identified as Timer 0
and Timer 1, and can be independently configured to operate in
a variety of modes as a timer or as an event counter. When
operating as a timer, the timer/counter runs for a programmed
length of time, and then issues an interrupt request. When
operating as a counter, the timer/counter counts negative
transitions on an external pin. After a preset number of counts,
the counter issues an interrupt request.


A basic operation consists of timer registers THx and TLx

(x= 0, 1) connected in cascade to form a 16-bit timer. Setting the
run control bit (TRx) in TCON register (see Figure 2-3) turns the
timer on by allowing the selected input to increment TLx. When
TLx overflows it increments THx; when THx overflows it sets the
timer overflow flag (TFx) in TCON register. Setting the TRx does
not clear the THx and TLx timer registers.Timer registers can be

accessed to obtain the current count or to enter preset values.
They can be read at any time but TRx bit must be cleared to
preset their values, otherwise the behavior of the timer/counter
is unpredictable. The C/TX # control bit (in TCON register) selects
timer operation, or counter operation, by selecting the divided-
down peripheral clock or external pin Tx as the source for the
counted signal. TRx bit must be cleared when changing the
mode of operation, otherwise the behavior of the timer/counter is
unpredictable. For timer operation (C/Tx# = 0), the timer
register counts the divided-down peripheral clock. The timer
register is incremented once every peripheral cycle (6 peripheral
clock periods). The timer clock rate is FPER / 6, i.e. FOSC / 12 in
standard mode or FOSC / 6 in X2 mode. For counter operation
(C/Tx# = 1), the timer register counts the negative transitions on
the Tx external input pin. The external input is sampled every
peripheral cycle. When the sample is high in one cycle and low in
the next one, the counter is incremented. Since it takes 2 cycles
(12 peripheral clock periods) to recognize a negative transition,
the maximum count rate is FPER / 12, i.e. FOSC / 24 in standard
mode or FOSC / 12 in X2 mode. There are no restrictions on the
duty cycle of the external input signal, but to ensure that a given
level is sampled at least once before it changes, it should be held
for at least one full peripheral cycle. In addition to the “timer” or
“counter” selection, Timer 0 and Timer 1 have four operating
modes from which to select which are selected by bit-pairs (M1,
M0) in TMOD. Modes 0, 1,and 2 are the same for both
timer/counters. Mode 3 is different. The four operating modes
are described below.

Timer 2:
The timer 2 has three modes of operation: ‘capture’, ‘auto-
reload’ and ‘baud rate generator’.

Timer 0:
Timer 0 functions as either a timer or event counter in four
modes of operation. in figure show the logical configuration of
each mode. Timer 0 is controlled by the four lower bits of the
TMOD register (see Table 2-5) and bits 0, 1, 4 and 5 of the TCON
register (see Table 2-3). TMOD register selects the method of
timer gating (GATE0), timer or counter operation (T/C0#) and
mode of operation (M10 and M00). The TCON register provides
timer 0 control functions: overflow flag (TF0), run control bit
(TR0), interrupt flag (IE0) and interrupt type control bit (IT0) For
normal timer operation (GATE0= 0), setting TR0 allows TL0 to be
incremented by the selected input. Setting GATE0 and TR0
allows external pin INT0# to control timer operation Timer 0
overflow (count rolls over from all 1s to all 0s) sets TF0 flag,
generating an interrupt request. It is important to stop
timer/counter before changing mode.

Mode 0 (13-bitTimer) :

Mode 0 configures timer 0 as a 13-bit timer which is set up

as an 8-bit timer (TH0 register) with a modulo 32 presale
implemented with the lower five bits of the TL0 register (see
Figure). The upper three bits of TL0 register are indeterminate
and should be ignored. Percale overflow increments the TH0
register. As the count rolls over from all 1’s to all 0’s, it sets the
timer interrupt flag TF0. The counted input is enabled to the

Timer when TR0 = 1 and either GATE = 0 or INT0 = 1.(Setting
GATE = 1 allows the Timer to be controlled by external input
INT0, to facilitate pulse width measurements). TR0 is a control bit
in the Special Function register TCON (Table 2-3). GATE is in
TMOD. The 13-bit register consists of all 8 bits of TH0 and the
lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate
and should be ignored. Setting the run flag (TR0) does not clear
the registers. Mode 0 operation is the same for Timer 0 as for
Timer 1. Substitute TR0, TF0 and INT0 for the corresponding
Timer 1 signals in Table 2-10. There are two different GATE bits,
one for
Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).


Fig 4.3: In timer/counter x (x = 0 or 1) mode 0

Mode 1 (16-bit Timer) :

Mode 1 is the same as Mode 0, except that the Timer

register is being run with all 16 bits.Mode 1 configures timer 0 as
a 16-bit timer with the TH0 and TL0 registers connected in
cascade The selected input increments the TL0 register.


Fig 4.4: In timer/counter x (x = 0 or 1) in

mode 1

Mode 2 (8-bit Timer with Auto-Reload) :

Mode 2 configures timer 0 as an 8-bit timer (TL0 register)

that automatically reloads from the TH0 register (see Table 2-5
on page 87). TL0 overflow sets TF0 flag in the TCON register and
reloads TL0 with the contents of TH0, which is preset by
software. When the interrupt request is serviced, hardware
clears TF0. The reload leaves TH0 unchanged. The next reload
value may be changed at any time by writing it to the TH0
register.Mode 2 operation is the same for Timer/Counter 1.


Fig 4.5 : In timer/counter x (x = 0 or 1) in mode


Mode 3 (Two 8-bit Timers) :

Mode 3 configures timer 0 so that registers TL0 and TH0

operate as separate 8-bit timers This mode is provided for
applications requiring an additional 8-bit timer or counter. TL0
uses the timer 0 control bits C/T0# and GATE0 in the TMOD
register,and TR0 and TF0 in the TCON register in the normal
manner. TH0 is locked into a timer function (counting FPER /6)
and takes over use of the timer 1 interrupt (TF1) and run control
(TR1) bits. Thus, operation of timer 1 is restricted when timer 0 is
in mode 3.



Fig 4.6 : In timer/counter x (x = 0 or 1) in mode


Timer 1 :

Timer 1 is identical to timer 0, except for mode 3, which is

a hold-count mode. The following comments help to understand
the differences: Timer 1 functions as either a timer or event
counter in three modes of operation. Figure show the logical
configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a hold-

count mode.• Timer 1 is controlled by the four high-order bits of
the TMOD register and bits 2, 3, 6 and 7 of the TCON register
The TMOD register selects the method of timer gating (GATE1),
timer or counter operation (C/T1#) and mode of operation (M11
and M01). The TCON register provides timer 1 control functions:
overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and
interrupt type control bit (IT1).Timer 1 can serve as the baud rate
generator for the serial port.

Mode 2 is best suited for this purpose. For normal timer

operation (GATE1 = 0), setting TR1 allows TL1 to be
incremented by the selected input. Setting GATE1 and TR1
allows external pin INT1# to control timer operation. Timer 1
overflow (count rolls over from all 1s to all 0s) sets the TF1 flag
generating an interrupt request. When timer 0 is in mode 3, it
uses timer 1’s overflow flag (TF1) and run control bit (TR1). For
this situation, use timer 1 only for applications that do not
require an interrupt (such as a baud rate generator for the serial
port) and switch timer 1 in and out of mode 3 to turn it off and
on. It is important to stop timer/counter before changing modes.

Mode 0 (13-bit timer) :

Mode 0 configures Timer 1 as a 13-bit timer, which is set

up as an 8-bit timer (TH1 register) with a modulo-32 prescaler

implemented with the lower 5 bits of the TL1 register. The upper

3 bits of the TL1 register are ignored. Prescaler overflow

increments the TH1 register.



Fig 4.7 : In timer/counter1 in mode 0

Mode 1 (16-bit timer) :

Mode 1 configures Timer 1 as a 16-bit timer with the TH1

and TL1 registers connected in cascade). The selected input
increments the TL1 register.

Mode 2 (8-bit Timer with Auto Reload) :

Mode 2 configures Timer 1 as an 8-bit timer (TL1 register)
with automatic reload from the TH1 register on overflow (see
Figure 2-11). TL1 overflow sets the TF1 flag in the TCON register
and reloads TL1 with the contents of TH1, which is preset by
software. The reload leaves TH1 unchanged.


Fig 4.8 : Timer/counter 1 mode 2

Mode 3 (Halt) :

Placing Timer 1 in mode 3 causes it to halt and hold its

count. This can be used to halt Timer 1 when TR1 run control bit
is not available i.e., when Timer 0 is in mode 3.


The IS80C51/31 provides 6 interrupt sources: two external

interrupts, three timer interrupts, and a serial port interrupt.The
External Interrupts INT0 and INT1 can each be either level-

activated or transition-activated, depending on bits IT0 and IT1 in
Register TCON. The flags that actually generate these interrupts
are the IE0 and IE1 bits in TCON. When the service routine is
vectored to, hardware clears the flag that generated an external
interrupt only if the interrupt was transition-activated. If the
interrupt was level-activated, then the external requesting
source (rather than the on-chip hardware) controls the request
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except for Timer 0 in Mode 3).When a
timer interrupt is generated, the on-chip hardware clears the flag
that generated it when the service routine is vectored to. Each
timer handles one interrupt source; that is the timer overflow
flag TF0 or TF1. This flag is set every time an overflow occurs.
Flags are cleared when vectoring to the timer interrupt routine.
Interrupts are enabled by setting ETx bit in IE0 register. This
assumes interrupts are globally enabled by setting EA bit in the
IE0 register Timer Interrupt System

Fig 4.9: Timer interrupts


The serial I/O port in the AT89C51RB2/RC2 is compatible
with the serial I/O port in the 80C52. It provides both
synchronous and asynchronous communication modes. It
operates as a Universal Asynchronous Receiver and Transmitter
(UART) in three full-duplex modes (Modes 1, 2 and 3).
Asynchronous transmission and reception can occur
simultaneously and at different baud rates It is also receive-
buffered, meaning it can commence reception of a second byte
before a previously received byte has been read from the receive
register. (However, if the first byte still hasn’t been read by the
time reception of the second byte is complete, one of the bytes
will be lost). The serial port receive and transmit registers are
both accessed at Special Function Register SBUF. Writing to
SBUF loads the transmit register, and reading SBUF accesses a
physically second receive register.

The serial port can operate in 4 modes:

Mode 0:

Serial data enters and exits through RXD. TXD outputs the
shift clock. 8 bits are transmitted/received: 8 data bits (LSB first).
The baud rate is fixed at 1/12 the oscillator frequency.

Mode 1:

10 bits are transmitted (through TXD) or received (through

RXD): a start bit (0),8 data bits (LSB first), and a stop bit (1). On
receive, the stop bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.

Mode 2:

11 bits are transmitted (through TXD) or received (through

RXD): a start bit (0),8 data bits (LSB first), a programmable 9th
data bit, and a stop bit (1). On transmit, the 9th data bit (TB8 in
SCON) can be assigned the value of 0 or 1. Or, for example, the
parity bit (P, in the PSW) could be moved into TB8. On receive,
the 9th data bit goes into RB8 in Special Function register SCON,
while the stop bit is ignored. The baud rate is programmable to
either 1/32 or 1/64 the oscillator frequency.

Mode 3:

11 bits are transmitted (through TXD) or received (through

RXD): a start bit (0),8 data bits (LSB first), a programmable 9th
data bit and a stop bit (1). In fact, Mode 3 is the same as Mode 2
in all respects except the baud rate. The baud rate in Mode 3 is
variable.In all four modes, transmission is initiated in Mode 0 by
the condition RI = 0 and REN =1. Reception is initiated in Mode 0
by the condition RI = 0 and REN = 1. Reception is initiated in the
other modes by the incoming start bit if REN = 1 Serial I/O port
includes the following enhancements:

• Framing error detection

• Automatic address recognition

The serial port control and status register is the Special

Function Register SCON,shown below. This register contains not

only the mode selection bits, but also the 9th data bit for
and receive (TB8 and RB8), and the serial port interrupts bits (TI
and RI).

Baud Rates :

The baud rate in Mode 0 is fixed as shown in the following

equation.Mode 0 Baud Rate = Oscillator Frequency 12 The baud
rate in Mode 2 depends on the value of the SMOD bit in Special
Function Register PCON. If SMOD =0 (the value on reset), the
baud rate is 1/64 of the oscillator frequency. If SMOD = 1, the
baud rate is 1/32 of the oscillator frequency, as shown in the
following equation.Mode 2 Baud Rate = 2SMOD x (Oscillator
Frequency)64 In the IS80C51/31, the Timer 1 overflow rate
the baud rates in Modes 1 and 3.

Using the Timer 1 to Generate Baud Rates :

When Timer 1 is the baud rate generator, the baud rates in

Modes 1 and 3 are determined by the Timer 1 overflow rate and
the value of SMOD according to the following equation.

The Timer 1 interrupt should be disabled in this
application.The Timer itself can be configured for either timer or
counter operation in any of its 3 running modes. In the most
typical applications, it is configured for timer operation in auto-
reload mode (high nibble of TMOD = 0010B). In this case, the
baud rate is given by the following formula.

The Serial Port Interrupt is generated by the logical OR of

RI and TI. Neither of these flags is cleared by hardware when the
service routine is vectored to.

In fact, the service routine normally must determine

whether RI or TI generated the interrupt, and the bit must be
cleared in software.All of the bits that generate interrupts can be
set or cleared by software, with the same result as though they
had been set or cleared by hardware. That is, interrupts can be
generated and pending interrupts can be canceled in software.


Fig 4.10 : Interrupt System


Each interrupt source can also be individually programmed

to one of two priority levels by setting or clearing a bit in Special
Function Register IP (interrupt priority) at address 0B8H. IP is
cleared after a system reset to place all interrupts at the lower
priority level by default. A lowpriority interrupt can be
interrupted by a high-priority interrupt but not by another low-
priority interrupt. A highpriority interrupt can not be interrupted
by any other interrupt source. If two requests of different priority
levels are received simultaneously, the request of higher priority
level is serviced. If requests of the same priority level are
received simultaneously, an internal polling sequence

determines which request is serviced. Thus, within each priority
level there is a second priority structure determined by the
polling sequence, as follows:

Table 4.3: Priority level table

Note that the "priority within level" structure is only used to

resolve simultaneous requests of the same priority level.


The interrupt flags are sampled at S5P2 of every machine

cycle. The samples are polled during the following machine
cycle. If one of the flags was in a set condition at S5P2 of the
preceding cycle, the polling cycle will find it and the interrupt
system will generate an LCALL to the appropriate service routine,
provided this hardware generated LCALL is not blocked by any of
the following conditions:

1. An interrupt of equal or higher priority level is already in


2. The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
3. The instruction in progress is RETI or any write to the IE or IP
registers. Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Condition 2 ensures
that the instruction in progress will be completed before
vectoring to any service routine. Condition 3 ensures that if the
instruction in progress is RETI or any access to IE or IP, then at
least one more instruction will be executed before any interrupt
is vectored to.
The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2 of the
previous machine cycle. If an active interrupt flag is not being
serviced because of one of the above conditions and is not still
active when the blocking condition is removed, the denied
interrupt will not be serviced. In other words, the fact that the
interrupt flag was once active but not serviced is not

Every polling cycle is new. The polling cycle/LCALL

sequence is illustrated in figure. Note that if an interrupt of
higher priority level goes active prior to S5P2 of the machine
cycle labeled C3 in Figure. Thus, the processor acknowledges an
interrupt request by executing a hardware-generated LCALL to
the appropriate servicing routine. In some cases it also clears the
flag that generated the interrupt, and in other cases it does not.
It never clears the Serial Port flag. This must be done in the
user’s software. The processor clears an external interrupt flag
(IE0 or IE1) only if it was transition-activated. The hardware-
generated LCALL pushes the contents of the Program Counter
onto the stack (but it does not save the PSW) and reloads the PC

with an address that depends on the source of the interrupt
being serviced, as shown in the following table.

Table 4.4: Priority level table handled

Execution proceeds from that location until the RETI

instruction is encountered. The RETI instruction informs the
processor that this interrupt routine is no longer in progress, then
pops the top two bytes from the stack and reloads the Program
Counter. Execution of the interrupted program continues from
where it left off.Note that a simple RET instruction would also
have returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt was
still in progress.

Table 4.5: Priority level table handled
When an interrupt is accepted the following action occurs:

1. The current instruction completes operation.

2. The PC is saved on the stack.
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
5. The PC is loaded with the vector address of the ISR.
6. The ISR executes.

The ISR executes and takes action in response to the

interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the stack
and restores the old interrupt status. Execution of the main
program continues where it left off.


The external sources can be programmed to be level
activated or transition-activated by setting or clearing bit IT1 or
IT0 in Register TCON. If ITx= 0, external interrupt x is triggered
by a detected low at the INTx pin. If ITx = 1,external interrupt x
is edge-triggered. In this mode if successive samples of the INTx
pin show a high in one cycle and a low in the next cycle,
interrupt request flag IEx in TCON is set. Flag bit IEx then
requests the interrupt. Since the external interrupt pins are
sampled once each machine cycle, an input high or low should
hold for at least 12 oscillator periods to ensure sampling. If the
external interrupt is transition-activated, the external source has
to hold the request pin high for atleast one machine cycle, and
then hold it low for at least one machine cycle to ensure that the
transition is seen so that interrupt request flag IEx will be set. IEx
will be automatically cleared by the CPU when the service
routine is called. If the external interrupt is level-activated, the
external source has to hold the request active until the
requested interrupt is actually generated. Then the external
source must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be generated.


The INT0 and INT1 levels are inverted and latched into the
interrupt flags IE0 and IE1 at S5P2 of every machine cycle.
Similarly, the Serial Port flags RI and TI are set at S5P2. The
values are not actually polled by the circuitry until the next
machine cycle. The Timer 0 and Timer 1 flags, TF0 and TF1, are
set at S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. If a request is
active and conditions are right for it to be acknowledged, a

hardware subroutine call to the requested service routine will be
the next instruction executed. The call itself takes two cycles.
Thus, a minimum of three complete machine cycles elapsed
between activation of an external interrupt request and the
beginning of execution of the first instruction of the service
routine. Figure 17 shows response timings. A longer response
time results if the request is blocked by one of the three
previously listed conditions. If an interrupt of equal or higher
priority level is already in progress, the additional wait time
depends on the nature of the other interrupt's service routine. If
the instruction in progress is not in its final cycle, the additional
wait time cannot be more than three cycles, since the longest
instructions (MUL and DIV) are only four cycles long. If the
instruction in progress is RETI or an access to IE or IP, the
additional wait time cannot be more than five cycles (a
maximum of one more cycle to complete the instruction in
progress, plus four cycles to complete the next instruction if the
instruction is MUL or DIV).Thus, in a single-interrupt system, the
response time is always more than three cycles and less than
nine cycles.

1.Stress greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect

2.Minimum DC input voltage is –0.5V. During transitions, inputs
may undershoot to 2.0V for periods less than 20 ns. Maximum
DC voltage on output pins is Vcc + 0.5V which may overshoot to
Vcc +

3.0V for periods less than 20 ns.

4.Operating temperature is for commercial products only defined

by this specification.


Table 4.6: Operating range

Operating ranges define those limits between which the
functionality of the device is guaranteed.

Fig 4.11: Active mode

Fig 4.12: Power down mode


The Oriole's Display Module (ODM) is a dot matrix

liquid crystal display that displays alphanumeric,Kana(Japanese)

characters and symbols. The built-in controller & driver LSIs
provide convenient connectivity between a dot matrix LCD and
most 4 or 8 bit microprocessors or microcontrollers. All the
functions required for a dot matrix liquid crystal display drive are
internally provided. Internal refresh is provided by the ODM. The
CMOs technology makes the device ideal for Applications in hand
held, portable and the other battery powered instruments with
low power consumption.


 Easy interface with a 4-bit or 8-bit MPU.

 Built-in Dot Matrix LCD Controller with font 5×7 or 5×10
 Display Data RAM for 80 characters (80×8 bits).
 Character generator ROM, which provides 160 characters
font 5×7 dots and 32 characters with font 5×10 dots.
 Both display data and character generator RAMs can be
read from the MPU.
 Internal automatic reset circuit at power ON.
 Built-in Oscillator circuit. (No external clock required)
 Wide range of instruction functions : Clear Display, Cursor
home, Display ON/OFF, Cursor ON/OFF, Cursor Shift,
Display Shift.


Power supply for single supply voltage

Fig 5.1 : Power supply for single supply voltage

The data bus with MPU is available either for 8 bits 1-

operation or 4 bit 2-operation allowing the ODM to the interfaced
with either an 8 bit or 4 bit MPU. When the interface data is 8 bits
long, data bits DB to DB are all used and data input/output is
carried out simultaneously. W hen the interface data is 4 bit long,
data is transferred using only 4 bits (DB ) while DB are not used.
Data transfer between the ODM and the MPU is completed when
4-bit data is transferred twice. Data of the higher order 4 bits is
transferred first, then the lower order 4 bits is transferred. Check
the busy flag after4-bit data has been transferred twice (one
instruction). A 4 bit 2-operation read is used to transfer the busy
flag and address counter data. The latched data controls the
driver for generating drive waveform outputs. Transmission of
serial data always starts at the display data character pattern,
corresponding to the last address of the display data RAM (DD


Fig 5.2 : Interface with at89c51 through i/o ports

Ability of driving bus line :

DB to DB has the capacity of driving one TTL or

capacitance of 130pf. 0 7 The data bus terminals have three-
state construction. When the Enables signal is at low level, these
data bus terminals will remain in high Impedance state. The data
bus has pull-up MOS, so when the data bus is open, it produces
high output voltage.


The ODM is automatically initialized (Reset) when the

power is turned on using the internal reset circuit. The busy flag
(BF)holds “H”and does not accept instructions until initialization
ends. The busy state is 1 ms after V rises to 4.5 V. The following
instructions are executed in DD Initialization.
 Display clear
 Character font:5×7 dots (F=low)
 No. of lines: 1-line (N=low)
 Interface width: 8 bits (DL=high)
 Address Counter: Increment(I/D=high)

 Display: shift: Off (SH=low)
 Display: Off (D=low)
 Cursor: Off (c=low)
 Blink: Off (B=low)



Busy Flag (BF) :

When the busy flag is HIGH level, it indicates that the

controller is in the internal operation mode and the next
instruction will not be accepted. When R/W is '1' and RS is '0', the
busy flag is output from DB . The next 7 instruction must be
written after the busy flag goes low.

Address Counter (AC) :

The address counter (AC) generates the address for the DD

RAM, the CG RAM and for the cursor display. When an instruction
code for DD or CG RAM address is written to the controller, after
deciding whether it is DD RAM or CG RAM, the address
information is transferred to AC. After writing into (or reading
from ) DD or CG RAM display data, AC is automatically
incremented (or decremented). The data of the AC is output to
DB ~ DB When RS is ‘0’ and R/W is ‘1’. 0 6

Character General ROM (CG ROM) :

The character generator ROM generates 5×7 dot or 5×10

dot character patterns form 8-bit character codes. It can
generate 160 types of 5×7 dot character patterns and 32 types
of 5×10 dot character patterns. When the 8-bit character code of
a CG ROM is written to the DD RAM, the character pattern of the
CG ROM corresponding to the code is displayed on the LCD
display position corresponding to the DD RAM. Table 4 and 5
show the relation between character codes and character

Character Generator RAM (CG RAM) :

The character generator RAM (CG RAM) is the RAM with

which the user can generate character patterns by program. The
CG RAM has the capacity to store 8 kinds of 5×7 dots or 4 kinds

of 5×10 dots. Programming of these character patterns is
explained in CG RAM programming.

Display Data RAM (DD RAM) :

The display data ram(DD RAM) stores display data

represented in 8 Bit(hexadecimal) character codes. Its capacity
is 80 × 8 bits, or 80 characters. The display data RAM (DD RAM)
that is not used for display can be used as general data RAM.
Depending on the 8-bit character code that is written into the DD
RAM, LCD will select the character pattern either from Character
Generator RAM (CG RAM) or from Character Generator ROM (CG


If the power supply condition for correctly operating the

internal reset circuit are not met , or if the function set is
required to be modified , then initializing by instruction is
necessary. The following procedure should be adopted for
initialization .

1. Clear display

Fig 5.3 : Clear display

When this instruction is executed , the LCD display is
cleared and returned to its original status if it was shifted . the
cursor goes to left edge of display ( the left end of the first line if
2-line mode ) . Space code ‘20’(hexadecimal) (character pattern
for character code ‘20’ is blank pattern) is written into all DD
RAM addresses. Sets DD RAM address ‘0’ in AC. Sets I/D
=’1’(increment mode) of entry mode. S of the entry mode does
not change.

2. Return home

Fig 5.4 : Cursor returns to home position

The cursor or blink go to the left edge of the display (to the
left end of the first line in 2 line display mode ). The display
returns to its original status if it was shifted . DD RAM contents
do not change . Sets the DD RAM address 0 in AC.

3. Entry mode set

Fig 5.5 : Entry mode set

I/D : when the I/D set , the 8 bit character code is written or
read to and from the DD RAM , the cursor shifts to right by 1
character position ( I/D = ‘1’ ; increment ) Or to the left by 1
character position ( I/D = ‘0’ ; decrement ). The address
counter Is incremented ( I/D = ‘1’) or decremented ( I/D =’0’ )
by 1 at this time. Even after character pattern code is written
or read to and from CG RAM , the address counter is
incremented ( I/D =’1’ ) or decremented ( I/D = ‘0’ ) by 1.

S : shifts entire display either to right or to left when S is 1 ;

to the left when I/D=’1’ And to the right when I/D = ‘0’ .
thus it looks as if the cursor stands still and the Display
moves . the display does not shift when reading from the DD
RAM or When writing into or reading out from the CG RAM
when S = 0.

4. Display ON / OFF control

Fig 5.6 : Display ON/OFF control

D: the display is ON when D= ‘1’ and OFF when D=’0’. When

OFF due to D=’0’ Display data remains in DD RAM . it can
displayed immediately by setting D=’1’.

C: the cursor is displayed when C=’1’ and goes when C=’0’ .
even if cursor Disappears , the function if I/D , etc. does not
change during display data write . The cursor is displayed
using 5 dots in 8th line when 5x7 dot character font is

B: the character indicated by cursor blinks when B=’1’ , the

blink is displayed by Switching between all blank dots and
display characters at 409.6 ms interval when Fcp or fosc=250
khz . the cursor and blink can be set to display

Fig 5.7 : a)Cursor display b)Blink display

5. Cursor display shift

Fig 5.8 : Cursor display shift

Shifts cursor position or display to right or left without
writing or reading display Data . This function is used to correct
or search for the display . in a 2-line display the cursor moves to
2nd line when it passes the 40th digit of 1st line . Notice that 1st and
2nd line displays will shift at the same time . When the displayed
data is shifted repeatedly each line only moves horizontally . The
2nd line display does not shift into the 1st line position.

6. Function set

Fig 5.9 : Function set

DL : sets interface data length when DL= ‘1’ , the data input /
output and from the MPU is carried out by means of 8 bits DB7 to
DB0 . when DL = ‘0’ the data input /output to and from the MPU
is carried in 2 steps through the 4 bits DB7 to DB4.

N : sets number of display lines The 2-line display mode of the
LCD is selected when N=’1’ , while the 1-line display mode is
selected when N=’0’.

F : sets character font The 5x7 dots character font is selected

when F=’0’.

7. Set DD RAM address

Fig 5.10 : To set DD RAM address

Sets the DD RAM address into the address counter in binary B6

to B0.data then written or read from the ODM pertains to the DD
RAM . however , when N=’0’ (1-line display ) B6 to B0 is ‘00’ ~
‘4F’ ( hexa ) . when ‘00’ ~’27’ ( hexa ) for the first line , and
‘00’~67’ ( hexa ) for the second line.

8. Read busy flag and address

Fig 5.11 : Read busy flag and address

Reads the busy flag ( BF ) that indicates the system is now

internally executing a previously received instruction. BF=’1’
indicates that internal operation is in progress . the next
instruction will not be accepted until BF goes ‘0’. Check the BF
status before The next write operation . At the same time , the
value of address counter expressed in binary C6 to C0 is read .
CG and DD RAM address and its value is determined by previous

9. Write data to CG or DD RAM

Fig 5.12 : Write data to CG or DD RAM

Writes binary 8 data DDDDDDDD to the CG or the DD

RAM . whenever the CG or DD RAM is to be written into is
determined by the previous specifications of the CG RAM or DD
RAM address settings . after write , the address is automatically
incremented or decremented by 1 according to the entry mode .
the entry mode also determines display shift.

10. Read data from CG or DD RAM

Fig 5.13 : Write data to CG or DD RAM

Reads binary 8 bit data DDDDDDDD from CG or DD RAM . the

previous designation determines whether the CG or DD RAM is to
be read . before entering the read instruction , you must execute
either CG RAM or CG RAM address set instruction. If you don’t
the first read data will be invalid.

The ‘ address set ‘ instruction need not be executed just before

the ‘ read ‘ instruction when shifting the cursor between ‘ cursor
shift instruction ‘ . ( when reading out DD RAM ) . the cursor shift
instruction operation is the same as that of the DD RAM’s
address set instruction. After the read , the entry mode
automatically increases or decreases the address by 1 . however
display shift is not executed no matter what the entry mode is.


Function set can be performed only at power ON . initialize

the ODM by function set before executing any other instruction .
do not perform this operation subsequently . function set
includes setting of data length ( DL ) , number of display lines
( L ) and character font ( F ) .


The operating frequency of the controller is only 250 khz ,
therefore internal executing time is long . standard time is 40
micro sec ~ 1.6 ms . this varies for each instruction and is listed
in table. Table below shows the instruction set

Table 5.1 : Busy check

Since execution speed of ODM is much lower than its controlling
MPU . it is necessary to check the BF before performing any
operation with the ODM . while internal operation is active , the
BF is ‘1’ . at this time only operation that can be performed is
read busy operation .

Busy flag signal is output through DB7 , as shown in table 10.

when RS = 0 , R / W = ‘1’ and enable = ‘1’.

Figure 5.14 : Combinations of RS,RW


The only invalid instruction code to the ODM is as follows.

When the undefined instruction code is loaded to the ODM

it accepts the code but does not change the internal stages
( RAM and other status of flags ) . the ODM , however , goes into

the busy state for maximum 40 micro sec by the acceptance of
the code.

The AT89C51RB2/RC2 implements a keyboard

interface allowing the connection of a 8 x n matrix keyboard. It is
based on 8 inputs with programmable interrupt capability on
both high or low level. These inputs are available as alternate
function of P1 and allow to exit from idle and power-down
modes. At the lowest level, keyboards are organized in a matrix
of rows and columns . CPU accesses both rows and columns
through ports; therefore, with two 8 bit ports , an 8x8 matrix of
keys can be connected to a microprocessor . when a key is
pressed , a row and column make a contact ; otherwise , there is
no connection between rows and columns. In IBM PC keyboards ,
single microcontroller ( consisting of a microprocessor , RAM and
EPROM , and several ports all on a single chip ) takes care of
hardware and software interfacing of the keyboard. In such
systems , it is the function of programs stored in the EPROM of
the microcontroller to scan the keys continuously , identify the
one which has been activated, and present it to the mother
board. The keyboard inputs are considered as 8 independent
interrupt sources sharing the same interrupt vector. An interrupt
enable bit (KBD in IEN1) allows global enable or disable of the
keyboard interrupt (see Figure 23). As detailed in Figure 24 each
keyboard input has the capability to detect a programmable level
according to KBLS. x bit value. Level detection is then reported in
interrupt flags KBF. x that can be masked by software using KBE.
x bits. This structure allows keyboard arrangement from 1 by n
to 8 by n matrix and allow usage of P1 inputs for other purpose.

Keyboard Interface Block Diagram :

Fig 5.15 : Keyboard Interface Block Diagram


Fig 5.16 : Keyboard Input Circuitry


The Keil Software 8051 development tools are designed for

the professional software developer, but any level of

programmer can use them to get the most out of the 8051

microcontroller architecture. With the Keil tools, you can

generate embedded applications for virtually every 8051

derivative. The supported microcontrollers are listed in the

µVision Device Database

The Keil Software 8051 development tools listed below are

programs you use to compile your C code, assemble your

assembly source files, link and locate object modules and

libraries, create HEX files, and debug your target program.

• µVision is an Integrated Development Environment that

combines project management, source code editing, and

program debugging in one single, powerful environment.

• The Cx51 ANSI Optimizing C Cross Compiler creates

relocatable object modules from your C source code.

• The Ax51 Macro Assembler creates relocatable object

modules from your 8051 assembly source code.

• The BL51 Linker/Locator combines relocatable object

modules created by the C51 Compiler and the A51

Assembler into absolute object modules.

• The LX51 Extended Linker/Locator supports extended

device variants and provides additional features. LX51

supports all variants of the Cx51 Compiler and the Ax51


• The LIBx51 Library Manager combines object modules into

libraries that may be used by the linker.

• The OHx51 Object-HEX Converter creates Intel HEX files

from absolute object modules.

• The RTX51 Tiny Real-time Operating System that

simplifies the design of complex, time-critical software


This 8051 development tools are described in more details

in the section Development Tools. For software testing in target

hardware several µVision Debugger interfaces are available. The

Keil development tools for the 8051 offer numerous features and

advantages that help you quickly and successfully develop

embedded applications. They are easy to use and are

guaranteed to help you achieve your design goals. The µVision

IDE is a Windows-based software development platform that

combines Project Management, Source Code Editing, Program

Debugging, and Flash Programming in a single, powerful


For optimum support of the different 8051 variants, Keil provides

the following development tools:

Development Tools Description

C51 Compiler,
A51 Macro Assembler,
BL51 Linker/Locater, Supports standard
OC51 Banked Object File Classic 8051 8051 devices and
Converter, Devices. includes support for 32
LIB51 Library Manager, x 64K code banks.
OH51 Object/HEX File

C51 Compiler (with OMF2 Supports standard and

Classic 8051
Output), extended 8051
AX51 Macro Assembler, devices. Includes
Extended 8051
LX51 Linker/Locater, support for code
LIBX51 Library Manager banking and up to
OHX51 Object/HEX File 16MB code and xdata
Converter memory.

CX51 Compiler,
AX51 Macro Assembler, Supports Philips
LX51 Extended Linker/Locater Philips 80C51MX 80C51MX devices that
LIBX51 Library Manager Devices. provide a linear 16MB
OHX51 Object/HEX File address space.

Table 6.1 : Development Tools

µVision supports all tool variants and selects them on the

settings of selected device. The Keil user's guides uses generic

terms for the various tool variants:

• Cx51 refers to both the C51 Compiler and the CX51


• Ax51 refers to both the A51 Macro Assembler and the

extended AX51 Macro Assembler.

• Lx51 refers to both the BL51 Linker/Locater and the

extended LX51 Linker/Locater.

• LIBx51 refers to both the LIB51 and LIBX51 Library


Test Programs with the µVision Debugger

This chapter describes the Debug Mode of µVision and shows you

how to use the user interface to test a sample program. Also

discussed are simulation mode and the different options

available for program debugging.

You can use µVision Debugger to test the applications you

develop using the Cx51 Compiler and Ax51 Macro Assembler.

The µVision Debugger offers two operating modes that are

selected in the Options for Target – Debug dialog.

• Use Simulator allows to configure the µVision Debugger

as software-only product that simulates most features of

the 8051 microcontroller without actually having target

hardware. You can test and debug your embedded

application before the hardware is ready. µVision simulates

a wide variety of peripherals including the serial port,

external I/O, and timers. The peripheral set is selected

when you select a CPU from the device database for your


• Use Debugger Drivers that connect the µVision

Debugger directly to emulators, Embedded ICE (On-chip

Debug System) for example with the Keil ULINk USB-JTAG


There are a number of techniques you must know to create

programs that utilize the various on-chip peripherals and

features of the 8051 family. Many of these are described in this

chapter. You may use the code examples provided here to

quickly get started working with the 8051.There is no single

standard set of on-chip peripherals for the 8051 family. Instead,

8051 chip vendors use a wide variety of on-chip peripherals to

distinguish their parts from each other. The code examples

demonstrate how to use the peripherals of a particular chip or

family. Be aware that there are more configuration options than

are presented in this text.

• Startup Code

• Special Function Registers

• Register Banks

• Interrupt Service Routines

• Interrupt Enable Registers

• Parallel Port I/O

• Timers/Counters

• Serial Interface

• Watchdog Timer

• D/A Converter

• A/D Converter

• Power Reduction Modes

The startup code is executed immediately upon reset of the

target system and performs the following operations:

• Depending on the device variant, device specific features

are configured.

• Clears data memory (optionally)

• Initializes the reentrant stack and re-entrant stack pointer


• Initializes the 8051 hardware stack pointer

• Transfers control to the variable initialization code or to the

main C function.

The Keil C51 Compiler includes several device specific startup

code variants. A generic startup code is provided in the file



Visual basic 6 is Microsoft’s latest and greatest version of

the visual basic programming language. Visual basic reduces the
efforts required and makes many aspects of programming as
simple as dragging objects onto screen with your mouse.

Programming process :

1. Decide what our application is to do by creating an

overall design.
2. Create the visual portion of our application (the
screens and menus that our user will interact with).
3. Add visual basic programming language code to tie
the visual elements together and to automate the
4. Test our application to locate and remove any bugs if
5. Compile our tested application and distribute the
compiled application.


Fig 6.1 : Basic form window

The visual basic enables us to design and create

screens as we create our program. The Form window,

also called a Form, comprises the background of the

visual basic program’s screen and contains elements

such as command buttons and scrollbars. Programs may

require one or more form windows depending on the

nature and complexity of the program. In form window,

we design application forms which are background

windows that users can see, in the central editing area,

where the form window appears. We can also resize the

form window to make the windows which we create in

our application as large or as small as we need. This

application may also contain multiple forms. The form

files have an extension .FRM

The Toolbar :

The visual basic toolbar appears that you see

beneath the menu bar changes as you use visual basic:

• Debug: this toolbar appears when you use the

interactive debugging tools to trace and correct


• Edit: This toolbar aids your editing of visual basic


• Form Editor: This toolbar helps you adjust

objects on forms

• Standard: This toolbar is the default toolbar that

appears beneath the menu bar.

Toolbox :

The toolbox window differs from the toolbar. The
toolbox window typically called the toolbox, is a
collection of tools that act as a repository of controls
you can place on a form.

Fig 6.2 : Tool box


Fig 6.3 : Project form window

The above form window consists of two timers. Timer1 is

used to display the moving text “FIRST OPEN THE COMM PORT

TO SEND OR RECEIVE DATA”. This text will move when we run

the hex file. If text has reached extreme left end of screen move

it to right corner otherwise move it to left. Timer2 is used to

change the color of moving text. MSCOMM is used for serial

communication. This tool helps the hardware to communicate

with PC through comm port. It also has a text box which displays

the key pressed on keyboard. In another text box which is below

the first one we can type the data which should be displayed on

LCD. It has two command button CLEAR DATA and SEND

DATA. Clear data is used to send the data typed in textbox.

Send data is used to send the data typed in text box. It also has

CHECKBOX which controls on/off of LED. The LED can be made

on or off by checking or unchecking checkbox. If checkbox is

checked then it sends command to controller to make that

particular LED on.


Fig 6.4 : Comm port settings form

The figure above shows a communication port settings

form. Here ports, baud rates, data bits, parity, stop bits are all

set for communication through comm port. Every textbox has a

vertical scroll which shows a drop down menu and we can select

the appropriate port, baud rate etc. Here we will set commport1,

baud rate as 1200bps, which is the amount of data that can be

sent or received on comm port. We set data bits as 8, which

indicates that 8 bits are transmitted. We set parity bit as 1, which

determines whether the data transmitted is received correctly or

not. Stop bit is set to one which indicates the end of data byte.

There are two command windows OK and CANCEL, which is

used to confirm thesettings and cancel the settings respectively.


Figure shows the output form window where we set values for
the following

Fig 7.1: Output form for port settings



Fig 7.2 : IRD Simulator Showing Bit Error Rate

Fig 7.3 : IRD Simulator Showing Picture


With the available facilities and infrastructure provided, we
are successful in completing the project in the stipulated time
using keil and VB.

The basic model which we have designed, displays the

channel name and indicates the processor status. We can also
enhance this software so that a menu tree can be created.
Using this menu tree we can make provision for the user to
enter the polarization, frequency of the signal and its symbol
rate. This is accomplished by using the arrow keys present on
the keyboard.

As a final conclusion to the project, all major goals were

fulfilled. The user interface board is implemented in keil and
VB capable of performing two way communication between
the PC and hardware.

The commercial IRD is a patent product which is used only

by large institutes for research purpose. Because of its heavy
cost it is not used as a consumer component.


1. The 8051- Microcontroller and Embedded


3. Design With PIC Microcontrollers by PEATMAN

4. Hardcore Visual Basic by Mc KINNEY'S

5. Microprocessors and Interfacing by V. HALL

6. www.google.com

7. www.atmel.com

8. www.keil.com

9. www.MicroDigitalEd.com

10. www.8052.com/chips.phtml