Substrate Coupling in RF Analog/Mixed

Signal IC Design: A Review

Ashish C Vora, Graduate Student, Rochester Institute of Technology, Rochester, NY, USA.

Abstract : Digital switching noise coupled into the sensitive analog circuits is a critical
problem in the large scale integration of the mixed analog and digital circuits. Switching
transients in the digital MOS circuits can perturb the analog circuits integrated on the same
die by means of the coupling through the substrate. Parasitic substrate coupling can also
severely degrade the performance of high speed ICs. This paper describes the noise coupling of
this kind, especially through the substrate in the CMOS integrated circuits. Various models to
model mixed signal coupling have been reviewed. Also various techniques used to reduce this
coupling are suggested in the latter part of the paper. The paper also describes experimental
technique for observing the effect of substrate noise on RF analog circuit.

Index Terms : Vdd bounce, Gnd bounce, guard band, substrate noise, noise coupling

INTRODUCTION

Monolithic mixed signal and RF integrated circuits are becoming ubiquitous in the
semiconductor industry. Substrate coupling is the major problem in the field of mixed – signal
and RF circuit design due to the trend to integrate as many circuits as possible on the same die.
Substrate coupling is the phenomenon by which the transistors in the chip on the same substrate
interact with each other through the common substrate. In mixed signal systems the coupling of
noise between the on chip analog and digital can corrupt the low level analog circuit and impair
the performance of such mixed signal circuits. In the digital portion there are a large number of
gates undergoing transitions periodically at a high frequency. When such a transition occurs, a
spike of current is absorbed from the power bus. Usually a great portion of this current is passes
through the ground bus through direct feed through or it is injected into the substrate. The chip
complexity and the higher level of integration do not allow the analog and the digital grounds
tie together. The cumulative contribution of currents injected by switching gates in the substrate
is felt in the sensitive circuits in the form of spurious signal, which is known as substrate noise.
This high-speed substrate noise changes the desired analog output and degrades the overall IC
performance.

One of the most important issues in mixed signal design is to model the substrate and to predict
the signal coupling between the digital circuit and the analog circuit on the same substrate
correctly. The design methodology to reduce this substrate noise is also very important.

The author is a Graduate Student in Electrical Engineering at Rochester Institute of Technology. This paper is written as a part of the
Graduate Course Advanced Analog IC Design, Spring 2003.

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Various lumped elements have been proposed for heavily and lightly doped substrate.
Numerical techniques for efficient calculation of the substrate resistance have also been
investigated. In this paper is presented a review of the sources of substrate noise, its effect in
the mixed signal environment and various means to reduce these effects. Also simulation
results are demonstrated showing the effect of the substrate noise due to an inverter operating at
high frequencies on the performance of the Low Noise Amplifier at 2.4 GHz.

SOURCES OF SUBSTRATE NOISE

All the current that is injected into the substrate will cause fluctuations of the substrate voltage.
This is called substrate noise and is caused by the coupling of the switching or noisy signals to
the substrate. This noise can be caused due to different reasons: Coupling from the digital
power supply, coupling from the switching source-drain nodes and impact ionization in the
MOSFET channel.

Noise on the digital power supply is caused by the voltage drops due to the resistances and the
inductances of the power bus on the chip. This inductor and the on chip capacitor between the
power and ground cause a ringing in the power supply.

Fig. 1. Substrate as a parasitic return path

Normally the substrate is used as a digital ground in every CMOS gate and this results in a low
resistance path between the digital ground and substrate and hence all the digital noise and
ringing will be present in the substrate. Also the resistance and the capacitance of the substrate
causes the phenomenon of cross talk in the circuit as substrate acts as a parasitic return path for
the signals. The second source of substrate noise is the capacitive coupling from the switching
source and drain nodes of the transistors.

SUBSTRATE NOISE COUPLING EFFECTS IN MIXED-SIGNAL INTEGRATED

CIRCUITS

The lesser power consumption and lower cost of single chip solutions motivates technology
improvements in mixed signal (analog and digital) designs. But as there is a common substrate
for the digital and analog circuit, which causes coupling between the analog and the digital part
of the chip. Fig 2 shows that the digital switching node causes fluctuations in the underlying
voltage as it is capacitively coupled to the substrate through junction capacitances and

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interconnected bonding pad capacitances. Thus, a substrate current pulse flows between the
surrounding substrate contacts and the switching node. When the digital circuit is operating at
extremely high frequencies and many transistors are switching at a same time it causes a large
instantaneous current to flow through.

This current spike flows through the parasitic resistances and the inductances of the substrate
causing power supply noise voltage spikes known as “Vdd bounce” or “Gnd bounce”. A part of
this noise inevitably propagates to the sensitive analog circuitry through the substrate, power
supply lines, bonding wires, package pins etc., as shown in Fig. 3. This noise current ranges
from 0.1 mA to several mA depending on the circuit, number of transistors and their sizes.

The signal coupling through the substrate causes variations in the gain and the bandwidth of the
LNAs and other circuits at the front end of the receiver. Also the signal loss in the substrate is a
significant concern both in the design of receiver front end circuitry and in the realization of on
chip high Q inductors.

Fig. 2. Substrate noise coupling in mixed signal ICs

Fig. 3. The mixed signal problem of noise coupling from the switching portion of the IC to the
RF/analog portion via the substrate, package and supply lines.

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 MODELING MIXED SIGNAL COUPLING

Various Models have been described to explain the coupling through the substrate.

i. Impact Ionization Model

As the speeds of the operation of the circuits are increasing and the feature size is increasing,
impact ionization is becoming the main cause of substrate currents in the mixed signal
environment. When the electric field in the depleted drain end of the transistor increases
beyond a certain limit it causes impact ionization and as a result the electron hole pairs are
generated which causes the current to flow in the substrate.

ii. Device Interconnect Capacitance Model

Each and every transistor on the IC die is coupled capacitively to the substrate through its p-n
junction depletion region capacitances. Also every interconnect routed on the chip has some
capacitance to the substrate. This capacitive coupling to the substrate causes the coupling of the
signal to the substrate which becomes very important in the mixed signal IC because of the
large number of transistors which are switching and injecting current into the substrate at any
moment of time. This affects the high impedance analog circuits. Moreover with the decreasing
technology feature size this interconnects capacitances to the substrate are becoming very
important contributors of the injected current.

iii. Package Model

The effect of the non-ideal power supplies has a significant impact on the amount of substrate
coupled switching noise in any IC design. Since the bond wires and the package pins have a
significant amount of inductance and capacitance associated with them, any substrate current
picked up by them can cause glitches in the value of the substrate supply voltage.

iv. Substrate Model

The substrate can be modeled as layers of uniformly doped semiconductor material of varying
doping densities. Neglecting the effects of the magnetic fields on the chip, a simplified form of
the Maxwell’s equations can be applied to the substrate giving
1 2
[∂
]
.
∇ V (r , t ) + ε ∇ 2V (r , t ) = − q (r , t )
ρ ∂t
Solving this equation using the complex mathematics one can obtain the model for the
substrate. This thing has been done in many previous papers and is not described here.

SUBSTRATE NOISE COUPLING REDUCTION TECHNIQUES

Some bad side effects of substrate noise are mentioned in Section II, the following section
provides brief descriptions of some design techniques and guidelines for noise-aware physical
design, in order to reduce substrate noise coupling effects. In order to minimize the coupling of
substrate noise, three different aspects should be taken into account.

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 I) The amount of noise generated in the digital circuitry
II) The sensitivity of the analog circuitry to noise
III) The transfer of the noise from the digital portion of the chip into the analog section.

By minimizing these three areas, the substrate noise can be reduced.

The strategies for decoupling or reducing digital noise in the mixed signal integrated circuits
can be classified as follows:

I) Avoiding or suppressing noise generated by the digital circuit (the noise source)
II) Preventing or limiting noise transmission through the substrate.
III) Eliminating or compensating for the noise influence on the analog circuit.

These strategies can be applied through the device and process technologies, through the circuit
and layout techniques. Some of the methods to reduce the substrate coupling are shown here.

GUARD RINGS:
The guard ring is commonly utilized in the prevention of the substrate noise in the IC design.
The ring is a surface region heavily doped with the majority-carrier dopant and is intended to
form a Faraday shield around any sensitive devices, which need to be protected from the
substrate noise. A typical layout of guard bands is shown in Fig. The structures of the guard
ring are around the noisy and sensitive circuitry, and usually separate the digital circuits from
the analog circuits.

Bands
Digital
Noise Analog
Circuit

Guard Ring

Fig. 4. Guard Rings to reduce substrate coupling

NWELL Trench
NWELL trenches can be used in between the noisy and sensitive circuitry to block the substrate
current flowing near the surface of the substrate.

SUPPLY BOUNCE REDUCTION

A cross section of a package cavity with bond wires connecting the chip to package traces is
depicted in Fig. 5. This inductance of the package and bond wires can lead to supply bounce.
The supply bounce can cause the voltage drop between the board supply and the chip so that the
digital power and ground can be very noisy. There are two methods to minimize this bad effect:

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i) a separate power and ground are used in the analog portion of the chip to isolate the
more sensitive analog circuitry from the digital supply noise.
ii) lower package parasitic inductance can be accomplished through multiple or shorter
bond wire connections. This is a very effective solution, but it is expensive due to the
extra package costs.

Fig. 5. On-chip supply bounce due to the voltage drop across bond-wire package inductance

FLOORPLANNING

When the space in the circuit is available, careful floorplanning can be used to reduce the
effect of the substrate noise coupling. During floorplanning, specific well-isolated areas can
be allocated to noisy circuits as illustrated in Fig. 6. It means that the further the sensitive and
noisy circuits are apart, the less substrate noise coupling can affect the performance of the
circuit. Minimum distance requirements can be computed based on the overall noise spectral
energy produced by such circuits and the maximum levels of spurious energy tolerated by
sensitive circuits.
As with design trade-off, modifying a design to obtain better noise rejection may have an
associated cost due to extra die areas, more package pins, and more expensive packages.

Fig. 6. Good Floor planning to reduce the effect of the substrate noise coupling

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SIMULATION AND RESULTS

A sample Low Noise Amplifier operating at a frequency of 2.4GHz is simulated to study the
effect of the substrate noise on the performance of the analog circuits. An inverter operating at
a frequency of 500 MHz is considered to act as a digital circuit on the same substrate as the
inverter. The substrate is modeled as a resistor of a suitable value. Effects of change in the
resistance value due to the change in the resistivity of the substrate or the change in the spacing
between the digital and the analog circuit of the chip are studied. The substrate current is
modeled as a dc current of suitable low value. The different responses of the LNA like the S
parameters, the Gain, the Noise figure etc. are measured for both the case viz. without the
inverter connected i.e. isolated analog circuit and also with inverter connected and the substrate
current provided. Responses in both cases are compared and suitable conclusions are made.

Output Matching

Fig 7. Output Matching of a LNA without substrate noise and with substrate noise

The figure here shows us that how the output matching get affected due to substrate noise. Also
the peak frequency of resonance is reduced due to noise. This parameters affect the front end
performance of the receiver.

The Gain Plot

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 Fig 8. Gain of a LNA without substrate noise and with substrate noise

The gain value changes dramatically due to the substrate noise coupling effect. Also the
frequency at which the gain get maximum also changes.

Noise Figure

Fig 9. Noise Figure of a LNA without substrate noise and with substrate noise

The figure here shows how the Noise Figure of the LNA gets worse due to the substrate noise
of Inverter

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PowerGain

Fig 10. Power Gain of a LNA without substrate noise and with substrate noise

The figure here shows how the power gain is reduced due the substrate noise of inverter on
LNA.

CONCLUSION

Nowadays, the trend for IC design is high system complexities, short delay time and small die
areas. These systems may consist of analog, digital and even RF circuitry on the same
substrate, so modeling the substrate noise is very difficult because of the heterogeneity in
functionality and spurious signals in the mixed signal devices. However, substrate noise can
reduce the performance and impair the functionality of circuits, so substrate noise coupling
becomes a significant consideration in the high-speed design. Based on several techniques
introduced in this paper, there are three common trends for the development of substrate noise
coupling techniques: i) simple modeling, ii) modeling methods for high frequency and iii) pre-
layout. Simple substrate coupling techniques are good for IC designers due to extremely short
design cycle. Only a few experiments need to be done for the parameters of modeling
techniques. In addition, the demand for high frequency methods is increasing because the
operating frequency of IC communication system is increasing. Consequently, modeling
techniques as well as modeling equivalent circuits for high frequency should be explored and
developed. Finally, designers would prefer that substrate coupling analysis is performed
before circuit layout extraction in order to eliminate the time consumption for redesigning the
circuits if substrate noise problems appear in the layout extraction.

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