SemiconductorDevicePhysics - 4pt3 (Sze)

Introduction to
Semiconductor Device Physics
Tom Cunningham
Rev. 4.3, November 2001
Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3 Tom Cunningham 1-1
Introduction to
Semiconductor Device Physics
A user-friendly introduction
to semiconductor device physics
and digital CMOS circuits
Course Description:
This course provides a user-friendly introduction to semiconductor device physics, geared toward applications in digital microelectronics. It starts from basic principles of
chemistry and physics, and builds up in a stepwise fashion to an in-depth understanding of how transistors work and how they can be combined to make digital circuits – logic
as well as memory. The focus is MOSFET/CMOS technology, though the principles are applicable to other semiconductor devices and technologies as well. This course
consists of five modules:
1. Electronic Properties of Silicon
2. The PN Junction
3. The MOS Capacitor
4. The MOSFET
5. Small Circuits
In the first module, we study the electronic properties of silicon (and other semiconductors), including pure silicon and doped (N-type and P-type) silicon, to understand what
semiconductors are and how they behave. In the second module we study the junction formed by N-type and P-type silicon (called a PN Junction) because it is an important
step toward understanding the transistor (specifically, the source and drain regions of a MOSFET), and because it is an important semiconductor device in its own right – a
diode. In the third module, we study the MOS capacitor; this too is an important step toward understanding the transistor (specifically, the gate region of a MOSFET), and an
important device in its own right. In the fourth module, we combine the concepts of the previous modules to understand how transistors work (specifically, N-channel and P-
channel MOSFETs). In the fifth module, we learn about CMOS technology, and how transistors can be interconnected into small circuits, such as logic circuits (e.g. basic
logic gates) and memory circuits (specifically SRAM, DRAM, and Flash EEPROM cells). We will also have a high-level overview of how a complex chip, like a
microprocessor, is born – from design and layout to manufacture and test.
Course Goals:
• Understand what a semiconductor is and how transistors work, in detail. This is the primary goal of the course, to which the most time and detail are devoted.
• Illustrate how transistors can be used to build basic CMOS logic and memory circuits, and how complex integrated circuits like a microprocessor are born – from design and
layout to manufacture and test.
What This Course is NOT: In the context of understanding how transistors work, we will discuss some aspects of how integrated circuits are fabricated; however this course
is not about silicon processing per se. Similarly, we will discuss some aspects of device testing, but will not provide a comprehensive introduction to this subject. The material
on logic and memory circuits (module 5) is intended to illustrate the relevance of the first four modules and address some big-picture topics of interest; it is not intended to be a
complete introduction to circuit design. Other courses can be taken on these topics. This course provides the technical foundation for all of them.
Target Audience: This course is intended for scientists and engineers in various disciplines who would benefit from a good introduction to, or refresher course in,
semiconductor device physics. The typical audience consists of fab process and yield engineers, circuit designers (custom and ASIC), and validation and test engineers.
Prerequisites: A background in basic chemistry and physics is assumed, such as first-year college courses in these subjects. Knowledge of digital electronics, modern
physics, and/or calculus will be advantageous but is not required. Experience in IC design, fabrication, or testing is also an advantage. Mathematics is an integral (no pun
intended) part of this course, but is kept to a healthy minimum.
1
Electronic Properties of
Silicon
This is the first module in a five-module introduction to semiconductor device physics. The modules are:
2. The PN Junction
4. The MOSFET
5. Small Circuits
The purpose of this module is to study the electronic properties of silicon (and other semiconductors), to understand what a semiconductor is and how they
behave. We will begin by studying pure silicon, and then move on to study doped silicon – N-type and P-type.
The objectives of this module are:

• Understand the covalent bonding of silicon atoms
• Understand the energy band diagram – conduction band, valence band, and band gap
• Understand thermal generation and recombination
• Understand the charge carriers in a semiconductor – electrons and holes
• Understand the conduction properties of pure (intrinsic) silicon
• Understand the bonding diagram, band diagram, and conduction properties of N-type silicon
• Understand the bonding diagram, band diagram, and conduction properties of P-type silicon
• Understand the meaning and importance of the Fermi distribution and the Fermi energy level
Looking Ahead: After studying the electronic behavior of N-type and P-type silicon in this module, we will combine these concepts in the next module to
understand the physics of the PN Junction.
Silicon - Atomic Structure
I II III IV V VI VII VIII
1 2 2
H He He
Periodic Table of Elements
3 4 5 6 7 8 9 10
Li Be (abridged) B C N O F Ne
11 12 13 14 15 16 17 18
Na Mg Al Si P S Cl Ar
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
K Ca Sc Ti V Cr Mn Fe Co Ni Cu Zn Ga Ge As Se Br Kr
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
Rb Sr Y Zr Nb Mo Tc Ru Rh Pd Ag Cd In Sn Sb Te I Xe
nucleus
14
Si
Atomic Number 28.0855
(Z)
valence electrons (4) n=1 Atomic Mass [amu]

(outermost shell)
n=2
n=3
core electrons (10)
(inner shells)
1s22s22p63s23p2
Silicon is the semiconductor of choice for the modern digital microelectronics industry. (The reasons for this will be presented in
module 4, when we are in a better position to discuss them.) We will begin by studying the electronic properties of silicon to
understand what a semiconductor is.
Silicon has atomic number Z = 14 on the Periodic Table of Elements, indicating that the Si atom has 14 protons in its nucleus and
14 electrons surrounding the nucleus. Using Bohr’s “planetary” model of the atom, the four electrons in the outermost orbit or
“shell” are the valence electrons; the other ten are core electrons. Note that Si resides in column 4 of the Periodic Table, and
therefore has four valence electrons. The valence electrons participate in chemical bonding.
Pure Silicon - Bonding Diagram
Si Si Si
nucleus + core
electrons
Si valence electron Si Si Si
covalent
bond
Silicon Atom
Si Si Si
Schematic Diagram of Covalent Bonding in Silicon

(T = 0 K)
Those elements in column 8 of the Periodic Table are called the noble gasses; they have a full outer shell (8 valence electrons).
The noble gas structure is the lowest energy configuration, hence the noble gasses are chemically inert.
Other, “non-noble” atoms will form chemical bonds in order to approximate the noble gas structure. Silicon forms covalent bonds
as shown schematically; by sharing valence electrons with nearest neighbors, each Si atom is surrounded by eight valence
electrons, like a noble gas. These bonds hold the atoms together to form a solid, and play a key role in the electronic properties of
the material as well.
Pure Silicon - Energy Band Diagram
Conduction Band
Si Si
EC 1.1 eV
Electron Energy
Si Si Ei
EG = 1.1 eV
EV 0 eV
Si Si
Valence Band
Bonding Diagram Energy Band Diagram

(T = 0 K) (T = 0 K)
Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3 Tom Cunningham 1 - 10
Energy band diagrams are very useful for studying what the electrons inside a semiconductor material are doing. The vertical axis
represents electron energy. The horizontal axis represents distance or position (x) in the semiconductor sample. An electron in a
chemical bond resides in the valence band on this diagram (the top of the valence band EV is usually taken to be the zero of the
energy scale, which is a conventional but arbitrary choice).
At absolute zero* all of the electrons are in the valence band.
The Fermi energy level, EF, will be introduced later. Ei is the Fermi level in pure (aka. intrinsic) Si, and hence is called the
intrinsic Fermi level; it is near the middle of the band gap.
* Technical Aside: Absolute zero (0 Kelvin = -273 oC) is the theoretical minimum of temperature, i.e. as “cold” as an object or
material can possibly get. It is sometimes described as the temperature at which all molecular motion ceases, though perhaps a
more precise definition (from the standpoint of quantum physics) is that absolute zero is the temperature at which no thermal
energy whatsoever is available to, or extractable from, the system. Real objects/materials can approach absolute zero
asymptotically in a laboratory setting, but never reach it. It is, however, a very useful concept for discussing the behavior of a
material in the absence of thermal energy.
Pure Silicon - Thermal Generation (Low Temp)
n = p = ni
free
electron free
electron n = concentration of electrons
in conduction band (cm-3)
Si Si Si
EC
thermal
generation
Si Si Si E Ei EG = 1.1eV
(electron -
hole pair)
hole
EV
Si Si Si
hole p = concentration of holes
in valence band (cm-3)

(Low Temperature) (Low Temperature)
At temperatures above absolute zero, thermal generation takes place - i.e. an electron gains enough energy to break out of the
covalent bond and becomes free to roam about inside the solid. This leaves behind a hole (vacancy) in the bond. Thus, thermal
generation is said to create electron-hole pairs.
Thermal generation is also depicted in the band diagram. The electron traverses the band gap and resides in the conduction band.
A hole is left in the valence band. For silicon, the band gap is 1.1 eV, meaning that the electron must gain at least this much
energy to break free from the covalent bond. If it has less than this, it can not break free from the bond, and remains in the valence
band on the band diagram. Hence, electrons are not found inside the band gap; they reside in either the valence band or the
conduction band. The band gap can be thought of as forbidden energy states for the electrons.
Because free electrons and holes are created in pairs, the concentration of free electrons in the conduction band n (electrons / cm3)
is equal to the concentration of holes in the valence band p (holes / cm3). The intrinsic carrier concentration ni is equal to the
number of electron-hole pairs, i.e. n = p = ni for pure silicon.
Pure Silicon - Thermal Generation (Room Temp)
n = p = ni
n = concentration of electrons
Si Si Si
EC
Si Si Si E Ei
EG = 1.1eV
EV
Si Si Si
p = concentration of holes

(Room Temperature) (Room Temperature)
As the temperature increases, more thermal generation takes place, hence n and p increase.
Pure Silicon - Thermal Generation (High Temp)
n = p = ni
n = concentration of electrons
Si Si Si
EC
Si Si Si E Ei
EG = 1.1eV
EV
Si Si Si
p = concentration of holes

(High Temperature) (High Temperature)
At a high temperature, there is a lot of thermal generation.
(Note: When the temperature reaches the melting point, so many covalent bonds will be broken that the solid will not be able to
hold together, and the material will become liquid. Silicon has a melting point of about 1400 oC. In this course, we will concern
ourselves only with temperatures well below the melting point.)
Aside: A Closer Look at Covalent Bonds
r
U(r)
Si Si
coulombic
repulsion req isolated
of nuclei atoms
r
equilibrium req
bond length
Si Si
U(r)
r
electron in
n=3 electron in
coulombic
coulombic
potential well
n=2 barrier potential well of
of nucleus
lowering two nuclei
1 q1q 2 (covalent bond)
U (r ) =
n=1 4πεo r
Si Si Si
nucleus nucleus nucleus
r req
The top diagram shows two silicon atoms as they are brought closer to each other. Their separation distance (r) is plotted against
the potential energy of the system, U(r). When the atoms are far apart (isolated), they have no interaction and the net potential
energy is zero. As they are brought closer together, their valence electrons start to interact and form a covalent bond; this bond is
energetically favorable, and the total potential energy of the system is reduced. (Recall that, in general, nature favors lower
energy.) There is some equilibrium separation (the “valley” on the energy plot) that represents the equilibrium bond length (at a
given temperature). If the atoms are pushed closer together than this, a sharp rise in the potential energy of the system occurs due
to the coulombic repulsion of the (positively-charged) nuclei.
The bottom diagram shows the potential energy of an electron in an atom, due to the coulombic attraction between the positively-
charged nucleus (protons) and the negatively-charged electron. The potential energy goes as 1/r, where r is the separation between
the electron and the nucleus (determined by which shell the electron is in). Thus, we can say that the electron is in a coulombic
potential energy “well”, as shown on the diagram.
When two atoms are brought together to form a covalent bond, the electron in the bond now feels the attraction of both nuclei, and
thus it has a lower potential energy. The energy “barrier” is lowered in the region between the two nuclei, and the electron can be
shared between the two. Thus, the covalent bond is formed, and holds the two atoms together.
Aside: Where the Band Gap Comes From
Si Si Si Si
n =3
Levels split when
Electron energy
levels of isolated atoms form bond
n =2
atoms
n =1
Si electron configuration:
1s22s22p63s23p2
r
req
The electrons in an atom occupy different energy levels. When two atoms are brought together to form a covalent bond, these
levels split. (This is required by the Pauli Exclusion Principle, which says that no two electrons in an interacting system can have
the same quantum numbers.)
For an assemblage of N silicon atoms, N-way splitting will occur (in a real sample N is very large – e.g. there are 5x1022 Si
atoms/cm3). This is shown for the case of silicon in the diagram. At the far right of the graph, the silicon atoms are isolated (their
separation is large). As they are brought together to their equilibrium separation, band splitting occurs as shown, resulting in the
conduction band, valence band, and band gap. (Because there are so many energy levels and they are so closely spaced, each
band can be treated as a continuum of energies.)
Note from the electron configuration and the diagram that the valence band is full of electrons (contains all the valence electrons,
i.e. the 3s2sp2 electrons), and the conduction band is empty – this of course is at absolute zero, where there is no thermal
generation taking place.
Aside: Inside a Semiconductor
EC
EG
EV
Si Si Si Si
tunneling
Combining the concepts from the previous two slides.
Note that the movement of electrons in the valence band is carried out via tunneling*. A hole must exist on the other side of the
barrier for the electron to tunnel into (which is equivalent to the hole tunneling in the opposite direction). We will discuss carrier
motion later in more detail when we discuss conduction.
* Technical Aside: Tunneling is a central concept in modern physics (but having no analog in classical physics). Tunneling refers
to the transport of a particle (like an electron) across or through a potential energy barrier even though that particle does not have
sufficient energy to overcome that barrier according to classical physics. In the example presented here, the electron does not have
enough energy to travel over the potential energy “hill” shown in the diagram, and hence according to classical physics it can not
get to the other side of the barrier. But according to modern physics, under the right conditions the electron can tunnel through the
barrier to the other side. Despite its somewhat esoteric and counterintuitive nature, the phenomenon of tunneling has a sound
theoretical foundation, and has been experimentally observed in a wide variety of physical systems. We will encounter this
concept several times during this course.
Fermi Function & Fermi Level
Fermi Function
f(E) 0 < T1 < T2 T=0K
1
f ( E) = 1 T1
E − EF ·
1 + exp§¨ ¸ T2
© k BT ¹ 1/2
0 EF E
E = electron energy
EF = Fermi energy level
kB = Boltzmann constant = 8.617x10-5 eV/K = 1.381x10-23 J/K
T = Temperature (K)
kBT = thermal energy = 0.260 eV at 300 K
Thermal generation is a statistical process, i.e. it is not possible to predict whether a particular electron will be promoted to the
conduction band or not, but it is possible to predict statistically how many (or what percentage) of a large population will be
promoted. The Fermi function is used for this purpose. Derived based on Fermi-Dirac statistics, the Fermi function f(E) gives the
probability of finding an electron at energy E.* Hence, it takes on values in the range 0 to 1 (i.e. 0% to 100%).
EF is the Fermi energy or Fermi level. It is the “pivot-point” of the tail of the distribution, and the length of the tail is determined
by the temperature T. Note from the equation that the probability of finding an electron at the Fermi energy (E = EF) is always
50% (regardless of temperature). Think of the Fermi level as a “water mark” for the electron energies. It will prove to be a very
important quantity in the foregoing discussion.
* Technically, f(E) is the probability of finding the electron in some energy interval E to E + dE, where dE is an infinitesimal
increment in energy.
Density of States
conduction band:
g(E)
mn * 2mn * ( E − EC ) g (E) ~ E
gc ( E ) = E ≥ EC
π
2 3
valence band:
mp * 2mp * ( EV − E )
gv ( E ) = E ≤ EV 0 E
π
2 3
carrier concentrations:
≡ h/2π = 1.055x10-34 J•s
h = Planck’s constant = 4.136x10-15 eV.s = 6.626x10-34 J.s
∞
mn* = Electron effective mass
n= ³ f ( E ) g ( E )dE
EC
c mp* =Hole effective mass
EV
p= ³ [1 − f ( E )]g ( E )dE
−∞
V
The Fermi function gives the probability of finding an electron at energy E, but it doesn’t tell us whether (or how many) available energy states exist at that
energy. The density of states function, g(E), is derived from a quantum-mechanical treatment of the conduction/valence bands, and approximates the
number of energy states per unit volume at energy E. *
The probability of finding an electron at energy E is given by f(E)*g(E). Integrating f(E)*g(E) over the conduction band energy range gives n, the total
concentration of electrons in the conduction band. (Note that since the Fermi function goes to zero beyond the Fermi level, it is possible to make the
integral unbounded at the upper end, thus simplifying the integration.)
Since the probability of finding an electron at energy E is given by f(E), it follows that the probability of finding a hole (vacancy) at energy E is given by 1
– f(E). Integrating [1-f(E)]*g(E) over the valence band energy range gives p, the total concentration of holes in the valence band.
The quantities mn* and mp* are the electron and hole effective mass, respectively (numeric values are provided later in this module). Newton’s second law
of motion for an electron in free space is F = m0a (where F is the force acting on the electron, m0 is the mass of the electron in free space, and a is the
acceleration of the electron). For an electron inside a semiconductor, the analogous expression is F = mn*a, where mn* is the effective mass (particular to
the semiconductor material).
The mass of a hole may seem like a contradiction of terms at this point. We will clarify it shortly.
For our purposes, we are less interested in the mathematical details of the expression for g(E), and more interested in the general shape of the curve,
specifically the observation that that g(E) goes as the square root of energy E.
* Technically, g(E) is the density of available energy states in some energy interval E to E + dE, where dE is an infinitesimal increment in energy. Rarely
does one plug in numeric values to calculate f(E) and g(E) themselves; the expressions for f(E) and g(E) are used primarily in derivations of other quantities
(e.g. deriving expressions for the carrier concentrations by finding closed-form solutions for the integrals shown above).
Density of States - Analogy
SILICON STADIUM
visitors
g(E) = number of available g(E) = number of seats in

energy states at energy E row E
f(E) = probability of finding an EC f(E) = probability of

electron at energy E someone sitting in row E
f(E)*g(E) = number of electrons EG f(E)*g(E) = number of

at energy E (no seats) people in row E
³ f(E)*g(E) dE = total number

EV Σ f(E)*g(E) = total number
of electrons in conduction band of people in the visitors side
of the stadium
home
An analogy to help us understand the density of states, and how it is used.
The conduction and valence bands are like the home and visitor sections of a football stadium. Each row has a certain number of
seats (though all the rows do not necessarily have the same number of seats). There is some probability that a person will want to
sit in a given row; like electrons preferring lower energies, fans tend to prefer the front rows. By multiplying the number of seats
in a given row by the probability of someone wanting to sit in that row, the ticket agent can predict how many people total will be
sitting in that row (on average). (Whereas the ticket agent would have to come up with a probability function of his own, perhaps
based on historical data, we have the Fermi function.) By summing (integrating) this for all rows in the visitor section, the ticket
agent can predict how many people total will sit in the visitor section (on average).
And similarly for the home section.
The field is like the band gap – there are no seats there, so people are not found sitting there; they may cross the field to the other
side, but they do not sit on the field.
The Relationship Between the Fermi Function,
Density of States, and Carrier Concentrations
1 - f(E)
f(E)
source: Pierret & Neudeck (editors), Modular Series on Solid

State Devices, vol. 1, Addison-Wesley Publishing, 1988.
This slide shows graphically the relationship between the Fermi function, the density of states, and the electron and hole
concentrations for pure silicon. You can “visually” multiply the Fermi function and the density of states function together to
generate the electron concentration shown. Repeat using [1 – f(E)] to generate the hole concentration.
Aside -- A Closer Look at Energy: We are now in a position to understand the energy band diagram in greater detail. The
vertical axis E represents the total energy of the electron (potential energy + kinetic energy). EG = EC - EV represents the
potential energy of the electron (with EV ≡ 0 we can simply say that EC represents the potential energy of the electron). The
kinetic energy of the electron is then given by E – EC (the higher the electron is in the conduction band, the more kinetic energy it
has). In other words, EC is the minimum amount of thermal energy the electron must acquire to break free from the bond (enter
the conduction band), and any additional energy acquired by the electron becomes its kinetic energy. As for holes, the argument
is analogous. We will see shortly that hole energy increases in the downward direction on a band diagram, and it follows that the
hole kinetic energy is |EV – E| (the deeper the hole is in the valence band, the more kinetic energy it has). Treating the hole as an
independent positively-charged particle, it is easy to visualize what it means for a hole to have kinetic energy. Thinking of the
hole as a bond vacancy, it means that an electron occupying an energy level down in the valence band was promoted to the
conduction band. (Conservation of energy will require that the electron which fills this vacancy (during recombination) have
sufficient kinetic energy to “balance the books”.) Try to relate these concepts: the temperature of the sample increases, more
electrons are released from covalent bonds and with higher kinetic energy, the tail of the Fermi distribution pushes farther into the
conduction band and the higher energy states become populated by these higher-kinetic-energy electrons. Meanwhile the 1-f(E)
tail pushes farther into the valence band (by symmetry), releasing electrons from deeper energy levels, and thus the “books
balance” and the total energy of the system is conserved.
Pure (Intrinsic) Silicon - Useful Equations
n = p = ni
intrinsic carrier concentration:
3/ 2
ª 2π m *k T º
n B
NC = 2
« »
§ − EG · ¬ h2
¼
ni = NCNV exp¨ ¸ where
ª 2π m *k T º
3/ 2
© 2kBT ¹ NV =2
« h2
p
»
B
¬ ¼
intrinsic Fermi level:
EG = Energy band gap
kB = Boltzmann constant = 8.617x10-5 eV/K = 1.381x10-23 J/K
EG 3 § mp * · T = Temperature (K)
Ei = + kBT ln¨ ¸ kBT = thermal energy = 0.260 eV at 300 K

h = Planck’s constant = 4.136x10-15 eV.s = 6.626x10-34 J.s
2 4 © mn * ¹ mn* = Electron effective mass
mp* =Hole effective mass
m0 = Mass of the electron (free space) = 9.1095x10-31 kg
At 300 K:
-3
material mn*/mo mp*/mo ni (cm ) EG (eV) Ei (eV)
Si 1.18 0.81 1.18E10 1.12 0.5527
Ge 0.55 0.36 2.33E13 0.66 0.3218
GaAs 0.066 0.52 2.25E6 1.42 0.7501
Performing the integrations on the previous slide yields expressions for n and p (not shown).
Given that np = ni2, these expressions can be combined to yield the expression above for the intrinsic carrier concentration. Note
that ni increases with increasing temperature, as expected. Note also that ni is larger for a semiconductor material with a smaller
band gap, as expected.
These expressions for n and p can also be used to derive the above expression for the intrinsic Fermi energy, Ei.
Intrinsic Carrier Concentration vs. Temperature

Note the relationship between intrinsic carrier concentration, temperature, and band gap.
Pure Silicon - Conduction
I
+ Si -
electrons
holes
Si Si Si
+ -
V
+ -
Si Si Si
qV
EC
EG -
Si Si Si
+ Ei
EV
Conduction in Intrinsic Si Conduction in Intrinsic Si

Bonding Diagram (T ~ 300 K) Energy Band Diagram (T ~ 300 K)
Conduction is the movement of charge through a material under the influence of an applied voltage (bias). This charge transport results in an electric current through the
material.
At equilibrium* (i.e. when there is no voltage applied to the silicon sample), the electrons are in random thermal motion. There is no net transport of charge, and hence no
current in the sample.
These diagrams describe how conduction takes place inside a semiconductor when a voltage is applied. Looking at the bonding diagram, we see that the free electrons are
attracted to the positive terminal. The electrons in the covalent bonds are also attracted to the positive terminal, and use holes to facilitate their motion.
Conduction is also depicted in the energy band diagram. The bands are tilted by an amount qV (multiplying by q converts the voltage to energy), representing the voltage drop
across the material – the more voltage applied, the steeper the bands. Electrons follow the energy gradient and “roll downhill” from higher energy (negative terminal) to lower
energy (positive terminal). Notice again that, in the valence band, electrons “jump through holes” to facilitate their motion. Holes are required for conduction in the valence
band; if there are no holes, the electrons can not move. The situation is analogous to beings stuck in traffic – you can not move forward until there is some vacancy in front of
you to move into. If you are in a long line of traffic and there are no holes anywhere along the path, you have a traffic jam because nobody can move forward. The obvious
corollary is that the more holes there are, the more conductive the sample is.
Notice that, in the valence band, an electron moving toward the positive terminal means that a hole is moving toward the negative terminal. In this sense, a hole can be treated
as an independent, positively-charged particle. This mental construct is convenient, as it is easier to count the (relatively few) holes instead of the electrons when describing
the valence band. We will adopt this model moving forward. Holes will be treated like independent, positively-charged particles that move under the influence of an
applied voltage. We even assign an effective mass to the hole, as mentioned previously. Note that the electron and hole effective masses are not equal, and that the
transportation mechanisms are not the same (specifically, carrier movement in the valence band takes place via tunneling, as discussed previously).
Hence, conduction is carried out by electrons in the conduction band and holes in the valence band. Each contributes to the current through the sample. The larger n
and p are, the more conductive the sample is.
Current due to an applied electric field (voltage) is called drift current. The electric field vector is superimposed on the random thermal motion of the carriers (electrons and
holes). Although they maintain their disorderly thermal motion, they will tend to “drift” in the direction dictated by the electric field, resulting in a net migration of charge and
hence a current.
*Note: To be specific, equilibrium means: (1) no applied voltage; (2) no electric or magnetic fields present; (3) thermal equilibrium (no thermal gradients in the device); (4) no
mechanical stress; (5) no external sources of excitation (e.g. no light or radiation).
Pure Silicon - Conduction, A Closer Look . . .
I
electron conduction
(in conduction band) + Si -
electrons
holes
Si Si Si
+ -
hole conduction
(in valence band)
V
Si Si Si
EV
Si Si Si EV
EV
electrons time
holes EV
Introduction to Semiconductor Device Physics / Electronic Properties of Silicon / rev 4.3 Tom Cunningham hole 1 - 38
In the valence band, electrons moving toward the positive terminal means that holes are moving toward the negative terminal (the
direction a positive charge would move). Therefore, we can treat holes like independent, positively-charged particles inside the
semiconductor. This key concept is reiterated here because it will be used throughout the rest of the course.
Note that, because the electrons are “rolling downhill” in response to the band bending (energy gradient), holes are moving
“uphill”. Therefore, whereas electron energy increases going upward on a band diagram, it follows that hole energy increases in
the downward direction on the band diagram. An easy way to remember this is that electrons like to “sink” and holes like to
“float” on a band diagram. Given the opportunity, electrons will roll downhill, and holes will “roll uphill”.
Pure Silicon - Conduction (con’t)
σ)
conductivity (σ ρ)
resistivity (ρ
σ = qµ
µnn + qµ
µpp = qni(µ
µn+µ
µp) (Ω.cm)−1 1
ρ= (Ω.cm)
q = elementary charge = 1.602x10-19 coul.
σ
µn = electron mobility [= 1350 cm2/(V.s) for Si, room temp.]
µp = hole mobility [= 480 cm2/(V.s) for Si, room temp.]
resistance (R)
A L
ρL
R= (Ω)
ρ
A Si
L = length of sample(cm)
A = cross-sectional area of sample (cm2) I
Ohm’s Law R
Si
I (amps)
slope = 1/R
V=IR electrons
A holes
V = applied voltage (volts)
I = current (amps)
- +
V (volts)
V
The conductivity (σ) of a material is a measure of how readily it conducts current. Materials with a high conductivity (e.g. metals) are good conductors.
Resistivity (ρ) is the reciprocal of conductivity. Hence, a material with a high conductivity has a low resistivity.
Note that the conductivity and resistivity are inherent properties of the material itself; they do not take into account the size or shape of the sample.
The quantities µn and µp are the electron and hole mobility, respectively. The mobility is a measure of how easily the carrier can move through the material
in response to an applied electric field (voltage) - a high mobility is desirable for good conduction. Note that the electron mobility is higher than the hole
mobility in general. Mobility is discussed in more detail in the next slide.
The resistance (R) combines the inherent material properties (conductivity / resistivity) with the size and shape of the sample. Note that the resistance of the
sample is larger when the resistivity of the material is larger, as expected. Note also that the resistance increases as the length of the sample increases, and/or
as the cross-sectional area decreases. This is analogous to water flowing through a pipe: a shorter and/or wider pipe will have less resistance to water
flowing through it.
Ohm’s Law can be used to relate the resistance of the sample, the voltage applied across the sample, and the current flowing through the sample. Obviously,
a sample with a lower resistance will conduct more current for a given applied voltage. The total current through the sample is the sum of electron current
and hole current.
Note that semiconductor materials will typically deviate from ohmic (linear) behavior at higher voltage due to velocity saturation, discussed on the next slide.
This causes the I-V curve to “slope over” and become sub-linear at higher voltages (dashed line on graph).
* The current I in the diagram is in the direction of conventional current, i.e. the direction positive charge would flow (from + to -). Historically, this
convention was established before it was understood that current is carried by electrons, and electrons have a negative charge. Therefore, conventional
current always flows in the opposite direction of electron current, but the magnitude (amps) of the current is the same. Note that because holes have positive
charge, they flow in the direction of conventional current. In this course, diagrams will be labeled with the current I denoting the direction of conventional
current unless otherwise specified.
Mobility & Velocity Saturation
Si at 300 K
velocity saturation
slope = µ
vd = µε

As discussed previously, the carriers (electrons and holes) in the sample are in random thermal motion at equilibrium. When an
electric field (voltage) is applied, the influence of this field is superimposed on this random thermal motion, causing the carriers to
“drift” in the direction dictated by the field. Thus, there is a net movement of charge through the sample, i.e. a current referred to
as drift current.
This plot shows the speed or drift velocity, vd, at which an electron or hole moves through the Si sample as a function of the applied
electric field ε. Carrier velocity varies linearly with field strength for low and moderate applied fields, and the proportionality
constant (slope) is the mobility, µ (often referred to as the low-field mobility in this context). As previously noted, the electron
mobility is greater than the hole mobility, meaning that electrons move through the sample faster than holes in response to an
applied electric field.
As the carriers travel inside the solid in response to the electric field, their forward-progress is retarded by collisions (scattering
events) with vibrating Si atoms. At higher field strengths, these collisions become more frequent and more severe, thus reducing
the mobility. On the graph, this is the region where the curve slopes-over and eventually saturates (at vd ≈ 1.7x107 cm/s). This is
referred to as velocity saturation. In other words, increases in field strength contribute more to increased scattering than increased
carrier velocity.
(In fact, if the electric field accelerates carriers to sufficiently high speeds they can cause impact ionization when colliding with Si
atoms. These energetic carriers are called “hot” carriers. The impact ionization events give rise to an “avalanche” of hot carriers,
which results in a large current. We will discuss this in more detail in the next module.)
Other factors, such as temperature, also affect the mobility. These effects will be discussed in more detail later in this module.
Pure Silicon – Recombination & Generation (“R-G”)
n = p = ni
generation
dynamic equilibrium
Si Si Si
EC
generation
Si Si Si E Ei
EG
recombination
recombination EV
Si Si Si
Recombination is the reverse of thermal generation: an electron meets a hole and fills the vacancy. On the band diagram, an
electron in the conduction band returns to the valence band.
Recombination and generation both take place continuously inside a semiconductor material, and at any given temperature a
dynamic equilibrium is established between these two competing processes. Thus, n and p represent the carrier concentrations
inside the semiconductor at any given “snap shot” in time.
Recombination and generation are collectively referred to by the abbreviation “R-G” (e.g. one might refer to “minority carrier R-
G” in a silicon sample).
Properties of Common Semiconductors
Some useful semiconductor properties
Matl. Band Intrinsic Electron Hole Electron Hole Resis- Permit- Melting
gap carrier effective effective mobility mobility tivity tivity Point
conc. mass mass
EG ni mn*/m0 mp*/m0 µn µp ρ εr TM
-3
(eV) (cm ) cm /(V.s)
2
cm /(V.s)
2 .
(Ω cm) (=εs/ε0) (oC)
Si 1.12 1.18x1010 1.18 0.81 1350 480 2.5x105 11.8 1415
Ge 0.66 2.33x1013 0.55 0.36 3900 1900 43 16 936
GaAs 1.42 2.25x106 0.066 0.52 8500 400 4x108 13.2 1238
All values in table are for T = 300 K (room temperature).

m0 = 9.11x10-31 kg (mass of electron in free space)
ε0 = 8.85x10-14 F/cm (permittivity of free space)
εS = permittivity of the semiconductor
This table summarizes some physical properties of three important semiconductors: silicon (Si), germanium (Ge), and gallium-
arsenide (GaAs).
Although the foregoing discussion focuses on silicon, keep in mind that the concepts in this module are directly applicable to other
semiconductor materials as well.
Aside: Band Gap Variation with Temperature
source: S.M. Sze, Physics of Semiconductor

Devices, John Wiley & Sons, 1981.
The band gap decreases with increasing temperature, but the variation over the range of normal operating temperatures is very small
and can usually be neglected.
Metals, Insulators, & Semiconductors
Metal (e.g. Al) Semiconductor (e.g. Si) Insulator (e.g. SiO2)
Al nucleus & free (delocalized )
core electrons electrons
silicon
Si dioxide
(SiO2)
Si Si
O O
Aluminum (Al)
(room temperature)
Si Si
EC
(room temperature) Band Gap is too

conduction & valence large for thermal
bands overlap generation to occur
many electrons in
→ no carriers, not
conduction band,
EC conductive ( σ ∼ 0) EG = 9 eV
very conductive
- OR -
EG ~ 0.1 eV
Ei
EG = 1.1eV
EC
EV EV EV
Small or No Band Gap Moderate Band Gap Large Band Gap
In a metal, the band gap is very small (sometimes referred to as a “semi-metal”) or nonexistent (i.e. the conduction and valence
bands overlap). Hence, metals have a very high concentration of free (“delocalized”) electrons, and are very conductive. Metal
lines are used to carry electrical signals between transistors to form a circuit, as discussed later.
Insulators (dielectrics) have a very large band gap, and hence there is a negligible concentration of electrons in the conduction
band and the material is non-conductive. Such materials are useful for electrically isolating certain regions or features in a
semiconductor device or circuit, as discussed later.
Semiconductors have moderate band gaps, intermediate between conductors and insulators. Silicon can behave more like a
conductor or more like an insulator depending on the circumstances, hence the name semiconductor - e.g. the temperature or the
doping (discussed next) can vary the conductivity over orders of magnitude.
N-Type Silicon - Example: Phosphorous
1 2 2
H He He
3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
nucleus (15 protons

+ 15 neutrons)
15
P
30.97376
valence electrons (5) n=1

(outermost shell)
n=2
n=3
core electrons (10)
(inner shells)
1s22s22p63s23p3
Up to this point, we have been discussing the electronic properties of pure (intrinsic) silicon.
Silicon can be doped with other substances to make it either N-type or P-type. Note that doped silicon is also called extrinsic
silicon. We will discuss N-type silicon first.
N-type dopants reside in column 5 on the Periodic Table; common N-type dopants are phosphorous (P), arsenic (As), and antimony
(Sb). We will use phosphorous for example.
Column-5 elements like phosphorous have 5 valence electrons.
N-Type Silicon - Bonding Diagram (T = 0 K)
Si
Si Si Si Si
fifth
Silicon valence
(4 valence electrons) electron
Si P Si Si
P
Si Si Si P
Phosphorous
(5 valence electrons)
Bonding Diagram: Silicon Doped with Phosphorous (N-Type)

(Absolute Zero)
When the silicon is doped with phosphorous, the fifth valence electron of each phosphorous atom is not needed for covalent
bonding. At absolute zero, this fifth valence electron is weakly held by the phosphorous atom; i.e. very little thermal energy will
be required for this electron to break free and become a conduction electron.
For this reason, the phosphorous atoms are called donor atoms, because they will readily “donate” their fifth valence electrons to
the material as conduction electrons.
(Recall that at absolute zero there is absolutely no thermal energy available to the sample.)
N-Type Silicon - Energy Band Diagram (T = 0 K)
“Extra” (5th) valence

electrons of the phosphorous
dopant atoms n=p=0
~ 0.1 eV
EC
ED
EF
Ei
E
EG = 1.1 eV
EV
Energy Band Diagram: N-Type Si (Absolute Zero)
On the corresponding band diagram, these fifth valence electrons occupy a new energy level, called the donor level (ED), just below
the conduction band; i.e. very little energy will be required to promote these electrons to the conduction band.
The Fermi level (EF) has moved up toward the conduction band. The higher the concentration of phosphorous (ND), the more EF
moves up. Recall that the Fermi level is like a “water mark” for the electron energies in the sample.
(Aside: Previously, we discussed how energy bands and the band gap form via the splitting of energy levels when silicon atoms are
brought together into covalent bonds. When phosphorous atoms are introduced into this bonding scheme, the splitting of energy
levels is altered so as to form the donor level, and raise the Fermi level toward the conduction band.)
Fermi Level vs. Dopant Concentration
N-type
P-type

For N-Type silicon, the Fermi level moves toward the conduction band as the doping concentration ND is increased.
(The behavior of P-Type silicon, also shown on this diagram, will be discussed later.)
N-Type Silicon - Very Low Temperature
EC
ED
} 0.1 eV
Si Si P
EF
P Si Si Ei
EG = 1.1 eV
Si Si P
EV
Energy Band Diagram: N-Type Si Energy Band Diagram: N-Type Si

(Freeze Out, 0 < T < 77 K) (Freeze Out, 0 < T < 77 K)
At temperatures close to but above absolute zero, these fifth valence electrons begin to break free from their weak bonds to the
phosphorous atoms. On the band diagram, they move from the donor level to the conduction band. Again, this is a statistical
process; as the temperature increases, more of these electrons will be promoted to the conduction band.
This temperature range (0 to about 77 kelvin for this example) is called the Freeze Out range, because the temperature is so cold
as to prevent all of these electrons from reaching the conduction band.
N-Type Silicon - Low Temperature
n>p Extrinsic where ND is the concentration of
Temperature phosphorous atoms (atoms/cm3)
n ≈ ND Region
EC
ED
} 0.1 eV
Si Si P
EF
P Si Si Ei
EG = 1.1 eV
thermal
generation
thermal
generation
Si Si P
EV
Bonding Diagram: N-Type Si Energy Band Diagram: N-Type Si

Once the temperature rises out of the Freeze Out range, all of the fifth valence electrons have been released from their phosphorous
host atoms and have joined the conduction band.
Some small amount of thermal generation also takes place, as previously discussed. (Recombination also takes place, though it is
not explicitly shown on these diagrams. Recall that, at thermal equilibrium, the generation rate and the recombination rate are
equal, giving rise to a dynamic equilibrium. Thus, n and p denote the carrier concentrations at any “snap shot” in time.)
However, the concentration of electrons in the conduction band, n, is dominated by the population of “donated” electrons; the
contribution from thermal generation is negligible. Because each phosphorous atom donates one electron, we can write that n ≈ ND ,
where ND is the concentration of phosphorous atoms in the sample.
This is the onset of the extrinsic temperature range.
Note also that, for N-type silicon, the concentration of free electrons is greater than the concentration of holes, due to the presence
of the “donated” electrons. It is no longer the case that n = p as it was in pure silicon; for N-type silicon n > p, and hence electrons
are called the majority carriers, holes are the minority carriers.
This is where the name N-type comes from: the majority carriers are electrons, which have a Negative charge. (Note however that
the sample is macroscopically neutral; i.e. the “extra” electron donated by each phosphorous atom is balanced by a proton in its
nucleus. The sample as a whole has no net electrical charge under normal, equilibrium conditions.)
N-Type Silicon - Room Temperature
Extrinsic
n>p Temperature
n ≈ ND Region
EC
ED
} 0.1 eV
Si Si P
EF
P Si Si Ei
EG = 1.1 eV
thermal
generation
Si Si P
EV

(Room Temperature ≈ 300 K) (Room Temperature ≈ 300 K)
As the temperature rises, more thermal generation takes place, as expected. However, note that the approximation n ≈ ND is still
valid at room temperature, as the “donated” electrons in the conduction band far outnumber the thermally generated electrons.
This is a useful fact, since most semiconductor devices operate around room temperature, and the majority carrier concentration is
simply equal to the dopant concentration (which is generally known from the fabrication process, or can be measured).
N-Type Silicon - High Temperature
Intrinsic
n → ni Temperature
n = p = ni Region
many more electrons
created thermally
(n ≈ ni)
donated electrons
EC
} 0.1 eV
Si Si P ED
EF
P Si Si Ei
EG = 1.1 eV
thermal
generation
Si Si P
EV
holes approach their intrinsic
concentration (p ≈ ni)

(High Temperature, T > 450 K) (High Temperature, T > 450 K)
As the temperature increases, the concentration of thermally generated electrons becomes significant and eventually surpasses the
concentration of “donated” electrons (which is a fixed quantity, determined by the dopant concentration). In this case, n
approaches ni , the intrinsic carrier concentration. Hence, this is called the intrinsic temperature region. Also note that EF → Ei,
consistent with the intrinsic behavior of the material and the fact that n = p = ni.
Fermi Level vs. Temperature

This graph summarizes what we have already seen – EF → Ei as the temperature increases, consistent with the fact that n → ni
and p → ni (per np = ni2).
(This graph shows both N-type and P-type; P-type silicon will be discussed shortly.)
Summary: Carrier Concentration vs. Temperature

This graph summarizes the electron concentration as a function of temperature for N-type silicon.
Revisiting the Relationship Between f(E), g(E), n & p
N-Type
Intrinsic
(pure)
P-Type

This graph shows the relationship between the Fermi function, the density of states function, and the carrier concentrations for pure
and doped silicon. We have already seen this for pure silicon, and will discuss P-type silicon later. For now, we will compare and
contrast N-type silicon and pure silicon.
Looking at the graphs corresponding to N-type silicon, we see that the Fermi level is near the conduction band, as previously
discussed. This is consistent with the fact that there is a greater concentration of electrons in the conduction band for N-type
material. Recall that the Fermi level is like a “water mark” for the electron energies, and is the pivot point of the tail of the
distribution (the length of the tail being determined by the temperature).
Also recall that as the dopant concentration (ND) increases, the Fermi level moves up toward the conduction band. Visualize this in
the diagram above; this will increase the concentration of conduction electrons.
Other than the position of the Fermi energy level, the Fermi function itself does not change. Nor does the density of states
function, as it is not dependent on doping.
Note that the electron concentration is much greater than the hole concentration (n > p), as expected.
N-Type Silicon - Useful Equations
Freeze-Out Temperature Region
+ ND ND+ = conc. of ionized donor atoms (cm-3)

n = ND = gD = spin degeneracy of donor level [= 2 (standard value)]
§ EF − ED ·
1 + gD exp¨ ¸
© kBT ¹
Extrinsic & Intrinsic Temperature Regions

These equations hold for nondegenerately doped Si (EC - EF < 3kBT) in the extrinsic and intrinsic temperature regions
§ EF − EC ·
n = NC exp¨ ¸
© kBT ¹
§ EF − Ei · §n·
n = ni exp¨ ¸ EF = Ei + kBT ln¨ ¸
© kBT ¹ © ni ¹
n p = ni2
extrinsic temperature region: n ≈ ND
intrinsic temperature region: n = p = ni
These equations can be used to calculate the carrier concentrations in an N-type sample if the Fermi level is known, or, conversely,
to calculate the Fermi level if the carrier concentrations are known.
The equations for the extrinsic and intrinsic temperature regions are valid for non-degenerately doped semiconductor materials
only. For N-type material, this means that the Fermi level is below the conduction band edge (EC) and is not too close to it
(specifically, EF is at least 3kBT below EC). If the Fermi level is close to the conduction band, or inside the conduction band, the
sample is said to be degenerately doped, and these equations are not valid.*
Note that, if one carrier concentration (n or p) is known, the other can be calculated using np = ni2 . This relationship holds for pure
and doped semiconductor materials alike! For pure silicon (only!) it is the case that n = p = ni (hence np = ni2). This is obviously
not the case for N-type material; we know that n > p. However, the product np is still equal to ni2 . This fact represents a balance
between thermal generation and recombination inside the material; when the electron concentration n is raised, the likelihood of a
hole meeting an electron (recombination) increases, and hence the hole concentration p decreases proportionately. Since p is
reduced by the same factor that n is raised, the relationship np = ni2 is preserved. (This applies to any nondegenerately-doped
semiconductor sample at equilibrium - i.e. no optical generation, etc.)
* Note that heavily (degenerately) doped silicon is very conductive, similar to a metal. Also note that such high doping levels perturb the silicon crystal
structure (due the presence of so many dopant atoms), and alter the band gap (usually making it narrower) and the internal conduction properties (e.g. the
mobility, discussed later).
N-Type Silicon - Conduction
σ)
resistivity (ρ
σ = qµ
µnn + qµ
µpp ≈ qµ
µnND (Ω.cm)−1 1
ρ= (Ω.cm)
σ
resistance (R)
ρL I
R= (Ω)
A
R
L = length of sample (cm) Si
A = cross-sectional area of sample (cm2)
electrons
holes
Ohm’s Law A
V=IR - +
V = applied voltage (volts)

I = current (amps)
V
The conductivity and resistivity of an N-type sample can be calculated from the doping concentration. Note that the conductivity
increases as the doping concentration increases, as expected.
Similar to our discussion of pure silicon, the resistance of the sample can be calculated from the resistivity and the physical
dimensions. Ohm’s law can then be used to relate the current through the sample to the applied voltage. (At higher voltages, the
sample will deviate from ohmic behavior due to velocity saturation, as previously discussed.)
Note that the current is dominated by electrons, the majority carriers.
Resistivity vs. Dopant Concentration

The resistivity of N-type silicon decreases as the doping concentration increases, as expected. The same is true for P-type silicon,
discussed later.
(On this graph, the reason for the difference between the two is the higher mobility of electrons vs. holes, thus making the N-type
sample more conductive than a P-type sample with the same dopant concentration.)
Aside: Mobility is not a constant
P+ P+
source: S.M. Sze, Physics of Semiconductor low temperature high temperature

Devices, John Wiley & Sons, 1981. (low kinetic energy) (high kinetic energy)
There are two scattering mechanisms which impede the motion of a carrier through the material, reducing the mobility. Lattice
scattering (aka. phonon scattering) refers to the interaction of the carrier with vibrating Si atoms in the material. The amount of
lattice scattering increases with increasing temperature (because the atomic vibration increases). Ionized impurity scattering refers
to the interaction of the carrier with an ionized dopant (or other impurity) atom. The amount of impurity scattering increases with
increasing dopant concentration.
Mobility varies with doping concentration. For lighter doping, µ is relatively constant wrt. doping concentration - ionized
impurity scattering is negligible, lattice scattering is dominant. For higher doping, ionized impurity scattering can no longer be
neglected, and µ declines with increasing doping concentration.
Mobility varies with temperature. For a lightly-doped semiconductor, ionized impurity scattering can be neglected. Lattice
scattering dominates, and µ decreases with increasing temperature. For a heavily-doped semiconductor, ionized impurity
scattering can not be neglected. However, the ionized impurity scattering component actually decreases as temperature increases,
because the carriers have a higher kinetic energy and are less susceptible to the coulombic attraction of an ionized impurity. This
is the reason for the small positive-slope region in the µ vs. T graph (which appears only for the heavier-doped cases, shown
toward the bottom of the graph). This positive-slope region is small, however, because the lattice scattering component dominates
as the temperature rises, resulting once again in a negative slope.
P-Type Silicon - Example: Boron
1 2 2
H He He
3 4 5 6 7 8 9 10
11 12 13 14 15 16 17 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
nucleus (5 protons 5
+ 5 neutrons) core electrons (2)
(inner shells) B
10.811
n=1
valence electrons (3) n=2
1s22s22p1
We will now discuss P-type silicon. The discussion will be analogous to N-type silicon.
P-type dopants are found in column 3 of the Periodic Table, hence having 3 valence electrons. Common P-type dopants are boron
(B) and indium (In); we will use boron for example.
P-Type Silicon - Bonding Diagram (T = 0 K)
Si
Si Si Si Si
Silicon hole
Si B Si Si
B
Si Si Si B
Boron
Bonding Diagram: Silicon Doped with Boron (P-Type)

(Absolute Zero)
Boron has only three valence electrons. When incorporated into silicon, one covalent bond will be vacant as shown. Thus, boron
contributes holes to the material. Because a hole is a vacancy that will “accept” and electron, the boron dopant atoms are called
acceptor atoms.
P-Type Silicon - Energy Band Diagram (T = 0 K)
n=p=0
EC
Ei
E
EG = 1.1 eV
EF
EA
EV }~ 0.1 eV
Holes provided
by Boron atoms
Energy Band Diagram: P-Type Si (Absolute Zero)
On the band diagram, the holes from the boron atoms reside at the acceptor energy level, EA, just above the valence band.
Note that the Fermi level has moved down toward the valence band. The higher the dopant concentration, the closer it is to the
valence band (see previous slide showing Fermi level vs. dopant concentration for N-Type and P-Type silicon).
Note also that, at absolute zero, there are no charge carriers available for conduction. There are no electrons in the conduction
band, and no holes in the valence band. (If a voltage is applied across this material, there is no where for the electrons to move in
the valence band - recall that they require holes to facilitate their movement.)
P-Type Silicon - Very Low Temperature
EC
Ei
EG = 1.1 eV
EF
EA
EV
Energy Band Diagram: P-Type Si

(Freeze Out)
As the temperature rises above absolute zero, some electrons in the conduction band gain enough thermal energy to rise to the
acceptor level, EA. Note that this is equivalent to a hole moving from EA to the valence band. Again, this is a statistical process.
This is the Freeze Out temperature region.
P-Type Silicon - Low Temperature
Extrinsic where NA is the concentration of
p>n boron atoms (atoms/cm3)
Temperature
p ≈ NA Region
EC
Si Si B
thermal
generation
Ei
B Si Si
thermal
generation EF
EA
Si Si B EV
Holes provided
by Boron atoms
Energy Band Diagram: P-Type Si Energy Band Diagram: P-Type Si

At some temperature, all of the holes will have moved from EA to the valence band. This makes the sample more conductive.
Recall that we will treat holes as independent, positive charge carriers.
Thermal generation will also begin to take place. However, the number of holes created by thermal generation is negligible
compared to the number provided by the boron atoms, so p ≈ NA .
This is the extrinsic temperature region.
Holes are now the majority carriers, p > n. Electrons are the minority carriers. The material is called P-type because the majority
carriers are Positive. (Again, note that the sample is macroscopically neutral.)
P-Type Silicon - Room Temperature
p>n Extrinsic
Temperature
p ≈ NA Region
EC
Si Si B
Ei
B Si Si
EF
Si Si B EA
EV

(Room Temperature) (Room Temperature)
At room temperature, more thermal generation takes place.
P-Type Silicon - High Temperature
p → ni Intrinsic
Temperature
n = p = ni Region
electrons approach their intrinsic
concentration (n ≈ ni)
EC
Si Si B
Ei
B Si Si EF
EA
Si Si B EV
many more holes created
thermally (p ≈ ni)

(High Temperature) (High Temperature)
At very high temperatures, enough holes will be created by thermal generation to overshadow the (fixed) concentration of holes
from the boron atoms. Thus, n and p approach their intrinsic value, ni . EF approaches its intrinsic value, Ei. This is the intrinsic
temperature region.
P-Type Silicon - Useful Equations
Freeze-Out Temperature Region
p = NA− =
NA
NA- = conc. of ionized acceptor atoms (cm-3)
§ EA − EF · gA = spin degeneracy of acceptor level [= 4 (standard value)]
1 + gA exp¨ ¸
© kBT ¹
Extrinsic & Intrinsic Temperature Regions

These equations hold for nondegenerately doped Si (EF - EV < 3kBT) in the extrinsic and intrinsic temperature regions
§ EV − EF ·
p = NV exp¨ ¸
© k B T ¹
§ Ei − EF · § p·
p = ni exp¨ ¸ EF = Ei − kBT ln¨ ¸
© k BT ¹ © ni ¹
n p = ni2
extrinsic temperature region: p ≈ NA
intrinsic temperature region: n = p = ni
Equations for calculating carrier concentrations and Fermi level. Similar to those discussed previously for N-type silicon.
P-Type Silicon - Conduction
σ)
resistivity (ρ
σ = qµ
µnn + qµ
µpp ≈ qµ
µpNA (Ω.cm)−1 1
ρ= (Ω.cm)
σ
resistance (R)
ρL I
R= (Ω)
A R
L = length of sample (cm) Si
A = cross-sectional area of sample (cm2)
electrons
A holes
Ohm’s Law
- +
V=IR
V = applied voltage (volts) V
I = current (amps)
current is dominated by holes
(majority carriers)
Note that the current is dominated by hole flow (the majority carriers).
This concludes our discussion of P-type silicon. Note that many of the earlier slides presented during the discussion of N-type
silicon also contained related information about P-type silicon (in particular, some of the graphs). It is advised that you take a
moment to review these slides and take note of this.
Donor & Acceptor Energy Levels

This chart shows donor and acceptor energy levels of various dopants (impurities) in Si, Ge, and GaAs.
The levels below midgap are acceptor levels unless otherwise indicated by a “D” and are measured wrt. the top of the valence
band. The levels above midgap are donor levels unless otherwise indicated by an “A” and are measured wrt. the bottom of the
conduction band.
These values were determined from measured ionization energies for these various impurities in Si, Ge, and GaAs.
Mid-Gap States (Traps)
contaminant
T atom (trap)
EC EC
2 1
ET trap site ET trap site
Ei Ei
EG = 1.1eV EG = 1.1eV
1 2
EV EV
indirect thermal generation indirect recombination
There are no states inside the band gap for truly pure silicon.
However, as shown on the previous slide, various contaminants can introduce allowed energy states inside the band gap. These
impurity states (aka. traps) act as “stepping stones” for carriers to traverse the band gap, thus facilitating generation and
recombination. For example, an electron in the valence band can gain enough energy to jump into a trap state inside the band
gap, and then subsequently gain energy to jump to the conduction band (called indirect thermal generation). Similarly, an
electron and hole might meet at an impurity (trap) site in the silicon and recombine there (called indirect recombination) as shown
above. (The electron might be trapped first by the impurity atom and then the hole arrives later, or visa-versa.)
The most influential traps are those near mid-gap. They are the most effective recombination-generation (R-G) centers, because
they place a “stepping stone” about half way between the valence and conduction bands. Noteworthy contaminants are sodium
(Na), potassium (K), and iron (Fe), which are common impurities encountered during manufacturing. The cleanroom
manufacturing environment goes to great lengths to minimize contaminants.
Key distinctions between contamination (traps) and doping (donor/acceptor levels): (1) doping is intentional and controlled; (2)
doping produces donor and acceptor energy levels very close to the band edges, whereas contaminants tend to produce deeper
energy states near mid-gap; (3) trap sites are distinct points (or perhaps small clusters) encountered at specific locations in the
silicon sample, whereas dopant is spread throughout the sample in a more uniform fashion; (4) donors and acceptors contribute
charge carriers to the sample, whereas traps introduce R-G centers.
Aside: Silicon Crystal Structure
diamond unit cell (e.g. Si, Ge) zincblende unit cell (e.g. GaAs)

We have been using 2-D schematic depictions of the silicon bonding structure, to illustrate the basic concepts of covalent bonding, thermal generation and
recombination, conduction, etc.
However, if we look inside a silicon solid at the atomic level, we see that the silicon atoms are arranged in the 3-D crystal structure shown here, called the
diamond structure (the same crystal structure that carbon assumes when it forms diamond). This collection of atoms, known as the “unit cell”, is repeated to
form the whole solid. Germanium also has the diamond structure. Gallium arsenide (GaAs) has a very similar structure called zincblende. The parameter a
is called the lattice constant; it is 5.4 angstroms for Si and 5.6 angstroms for Ge and GaAs.
The crystal structure determines the spatial arrangement of Si atoms, and hence the potential field that an electron sees as it moves inside the crystal. Modern
physics treats the electron as a matter wave* moving through the crystal and reflecting from the crystal planes formed by the Si atoms. deBroglie described
matter waves by the expression p = h/λ, where p is the momentum of the electron (a particle property), λ is its wavelength (a wave property), and h is
Planck’s constant. Since the kinetic energy of the electron is E = ½mv2 (m is the mass of the particle and v is its velocity) and the momentum is p = mv, it
follows that p=√(2E). Thus, deBroglie’s expression relates the kinetic energy of the electron to its wavelength.
The crystal structure determines the energies/wavelengths that are allowed to exist inside the solid. The band gap represents those electron energies
(wavelengths) which are forbidden – these waves undergo destructive interference when they reflect from the crystal planes. This explanation of the origin
of the band gap is complimentary to the one provided earlier (based on energy level splitting in accordance with the Pauli exclusion principle).
* Aside: Matter waves were first described by the physicist deBroglie, who proposed that particles exhibit wave-like behavior. This is complimentary to
Planck’s earlier demonstration that waves exhibit particle-like behavior. For example, light is often thought of as a wave, exhibiting wave behaviors such as
interference and diffraction. However, it is sometimes necessary to treat light as a particle (photon), e.g. blackbody radiation, the photoelectric effect, etc.
Similarly, we tend to think of electrons as particles, but they have also been shown to exhibit wave behavior such as diffraction. Whether it is appropriate to
treat electrons (or light) as a particle or wave depends entirely on the situation being considered. The two models – particle and wave – are considered
complimentary (as opposed to contradictory), and can be used together to obtain a complete description or model.
Exercise
Suppose the sample shown here is doped with an Arsenic (As) concentration of 5x1016 cm-3. 1.0 cm
(1) Is this sample N-type or P-type, and how do you know this?
(2) If 0.5 V is applied across the sample, how much current flows (assume it is ohmic)? 0.15 cm Si
(3) Is this current dominated by electrons or holes, and how do you know this?
0.30 cm
Suppose the sample is doped with Indium (In) instead (same concentration). Repeat parts 1 – 3 above.
Explain why the N-type sample conducts more current than the P-type sample.
Solution
Arsenic is an N-type dopant, because it is in column 5 on the Periodic Table and hence has five valence
electrons. Majority carriers are electrons, hence current is dominated by electrons.
§ ·
( )
2
¨
σ = qµnND = (1.602 E − 19coul.) 1350 cm ¸ 5E16 −3 = 10.8 −1 −1
conductivity
¨ V ⋅s¸
cm Ω cm
© ¹
1 1
resistivity ρ= = = 0.092Ω ⋅ cm
σ 10.8
ρL (0.092Ω ⋅ cm)(1.0cm)
resistance R= = = 2.05Ω
A (0.15cm)(0.30cm)
V 0.5V
Ohm’s law I= = = 0.243 A = 243mA
R 2.05Ω
Indium is a P-type dopant, because it is in column 3 on the Periodic Table and hence has three valence
electrons. Majority carriers are holes, hence current is dominated by holes.
§ ·
( )
2
conductivity ¨
σ = qµpNA = (1.602 E − 19coul.) 480 cm ¸ 5E16 −3 = 3.84 −1 −1
¨ V ⋅s ¸
cm Ω cm
© ¹
resistivity 1 1
ρ= = = 0.26Ω ⋅ cm
σ 3.84
ρL (0.26Ω ⋅ cm)(1.0cm)
resistance R= = = 5.78Ω
A (0.15cm)(0.30cm)
V 0.5V
Ohm’s law I= = = 0.086 A = 86mA
R 5.78Ω
The N-type sample has a lower resistance and hence conducts more current because electrons have a higher mobility than holes (µn >
µp).
2
The
PN Junction
Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham 2-1
This is the second module in a five-module introduction to semiconductor device physics. The modules are:
2. The PN Junction
4. The MOSFET
5. Small Circuits
Understanding the physics of the PN junction is an important step toward understanding the MOSFET transistor, because the source and drain regions of the
MOSFET are PN junctions. The PN junction is also an important microelectronic device in its own right; we will see that it functions as a diode.
Objectives of this module:

• Understand what the depletion region is and how it forms
• Understand what the built-in voltage is and how it forms
• Understand the band diagram for a PN junction at equilibrium
• Understand the behavior of the PN junction under forward bias
• Understand the behavior of the PN junction under reverse bias
• Understand the ideal diode behavior, and compare it to a real diode
• Understand reverse junction breakdown
Looking Back: We are prepared to understand the physics of the PN junction because we understand, from the previous module, the behavior of N-type and P-type
silicon.
Looking Ahead: We will study the MOS capacitor in the next module, then combine this with our knowledge of the PN junction to understand how a transistor
works.
PN Junction - Schematic Diagram
N-Type Si P-Type Si
N P
PN
Junction
P+ P+ B- B-
P+ P+ B- B-
N P+ P+ B- B-
P
P+ P+ B- B-
εbi,Vbi
εbi, Vbi Built-in electric field, voltage
W Width of Depletion Region W
P+ Uncovered phosphorous ion Depletion
B- Uncovered boron ion Region
When N-type and P-type materials are put in contact, a PN junction is formed.
Diffusion drives majority carriers across the junction, in response to the concentration difference (gradient), exposing or
“uncovering” dopant ions in the vicinity of the junction, as shown. However, an electric field builds up (due to the uncovered ions)
in a direction opposing diffusion, and at some point these competing effects balance one another and an equilibrium is reached.
There is a depletion region near the junction, and a built-in electric field (voltage) in this region.
We will discuss all of this in more detail.
PN Junction - Energy Band Diagram
EC EC
EF
Isolated
E N-Type &
P-Type
EF Materials
EV
EV
N P
EC PN
Junction
qVbi
E EF Fermi levels
aligned at
equilibrium
EV
W
We can construct an energy band diagram for the PN junction. We start with the energy band diagrams for N-type and P-type
material, discussed previously.
The key to combining them is to understand that the Fermi levels must align at equilibrium. As long as the Fermi levels are not
aligned, carriers will flow across the junction, because it is energetically favorable for them to do so.
Visualize putting the top two diagrams together, then sliding them vertically until the Fermi levels line up.
Diffusion Illustration
Fish Tank Example
glass fish water-tight remove

tank partition partition
Water
Water Blue Ink
Ink
Isolation Contact Equilibrium
water and ink not in contact diffusion begins uniform concentration
This is an example to illustrate the concept of diffusion. Diffusion is a natural process that takes place when a concentration
difference (gradient) exists in a system. Diffusion refers to transport from areas of higher concentration to areas of lower
concentration, until a uniform concentration is achieved throughout (at which point there is no longer a concentration gradient,
and diffusion ceases).
PN Junction - Diffusion & Drift
N P
N e- * h P
Isolation Contact - Diffusion Begins
hole diffusion
electron diffusion
W
P+ B-
P+ B-
P+ B-
N P+ B-
P N P
P+ B-
P+ B-
-
+ - electron drift
+ εbi hole drift
Equilibrium: Drift = Diffusion Drift & Diffusion Compete
Diffusion:
N-type material has a high concentration of free electrons. P-type material has a high concentration of holes. Similar to the fish tank example, when the two
materials are placed in contact, diffusion begins. Electrons diffuse from the N-type side (higher concentration) into the P-type side (lower concentration).
Holes diffuse from the P-type side (higher concentration) into the N-type side (lower concentration). If there were no charge involved, this process would
continue until a uniform concentration of electrons and holes was achieved throughout the entire sample (at which point a concentration gradient would cease
to exist, and diffusion would stop).
Drift:
However, diffusion is not the only force at work in this system. Notice that, as diffusion takes place, dopant ions are exposed or “uncovered” near the
junction. In other words, when an electron diffuses out of the N-type side, it leaves behind a positively-charged phosphorous dopant ion; when a hole
diffuses out of the P-type side, it leaves behind a negatively-charged boron ion. Note that these ions are bonded into the silicon lattice and are not mobile;
only the free electrons and holes can move. Also, note that the electrons and holes recombine as they traverse the junction, as would be expected.
This region of uncovered, fixed charge near the junction is called the depletion region because it is depleted of mobile charge carriers (i.e. free electrons and
holes). This uncovered charge gives rise to an electric field in the depletion region, and as diffusion continues more charge is uncovered (the depletion
region grows wider) and the electric field increases. This is called the built-in electric field, giving rise to a built-in voltage. Electrons and holes are charged
particles, and hence their motion will be influenced by this electric field; as discussed in module 1, motion of a charged particle due to an electric field is
called drift.
Equilibrium:
Note that the electric field is oriented so as to oppose diffusion, i.e. diffusion is driving electrons from N-side to P-side, whereas the electric field drives
electrons from P-side to N-side. Obviously there will come a point at which these two forces, drift and diffusion, are equal but opposite, and equilibrium will
be established. The depletion region and built-in voltage remain. At this point, the Fermi levels will be aligned on the band diagram (see next slide).
Introduction to Semiconductor Device Physics / PN Junction / rev 4.3 Tom Cunningham 2 - 10

PN Junction - Diffusion & Drift (cont.)
EC
EC
EF
Contact
EF
EV
EV
Electron Diffusion Recombination
EC
EC
Drift & Diffusion EF
Compete EF time
EV
EV
Hole Diffusion
W
EC
qVbi
EC
EF
Equilibrium EF Fermi levels aligned
EV
EV
W
This tells the same story, but from an energy band perspective.
Before we begin, it is important to reiterate that electron energy increases going upward on a band diagram, and hole energy
increases going downward. As discussed in the previous module, electrons like to sink (roll downhill) and holes like to float (roll
uphill).
Immediately after contact, electrons diffuse from N-side to P-side. Holes diffuse from P-side to N-side. They recombine in the
depletion region, as shown.
The band diagrams slide vertically wrt. each other as drift and diffusion compete. The potential of the P-side is being raised wrt.
the N-side, as the uncovered charge gives rise to a built-in voltage. The potential “hill” or “barrier” (built-in voltage) across the
depletion region gets bigger as the bands slide, making it more difficult for carriers to diffuse across the junction. When the Fermi
levels have aligned, it is no longer energetically favorable for carriers to move from one side to the other. The barrier is
sufficiently high so as to impede further diffusion.* Drift and diffusion have balanced each other, and there is no net movement of
carriers across the junction – equilibrium has been established.
Finally, it is important to note that equilibrium is established very rapidly after contact – it is instantaneous for all practical
purposes.
* Aside -- Technical Note: It is a dynamic equilibrium (as opposed to a static equilibrium) because there are carriers crossing the junction, but there is no
net movement of carriers. This tiny population of carriers arises from thermal generation of minority carriers inside the depletion region or in the quasi-
neutral regions (described later), where they can drift across the junction due to Vbi. It also arises from the fact that, statistically, some majority carriers in the
far “tail” of the Fermi distribution will have enough energy to overcome the barrier and diffuse across the junction. The key point is that, at equilibrium, drift
counterbalances diffusion. At any “snap shot” in time, the net flow of electrons across the junction is zero, and the net flow of holes across the junction is
zero.

The Depletion Region: A Closer Look
Si Si P Si Si B
W
P+ B-
P Si Si B Si Si
P+ B-
N P
thermal
generation
P+ B-
Si Si P +
ε bi
- Si Si B
thermal
generation
Si Si P+ Si Si B-
fixed ions,
fixed ions, depleted of
depleted of holes
electrons
P+ Si Si B- Si Si
Si Si P+ Si Si B-
thermal
thermal
generation
generation

A closer look inside the PN junction.
The N-type and P-type bulk regions or neutral regions, away from the junction, have the bonding diagrams discussed earlier for
doped silicon. Nothing new here.
However, in the depletion region on the N-side, note that there are uncovered, positively-charged phosphorous ions. The free
electrons (i.e. the fifth valence electrons discussed earlier) diffused out of this region and into the P-side.
Similarly, in the depletion region on the P-side, note that there are negatively-charged boron ions. One way to understand this,
treating holes as independent positively-charged particles, is to say that the holes diffused to the N-side leaving behind boron
dopant ions with a net negative charge. An equivalent way of understanding this is to observe that the electrons that diffused into
the P-side from the N-side now fill the holes in the boron-doped bonding diagram, as shown; i.e. recombination has taken place, as
stated earlier. The presence of this electron gives the boron atom a net negative charge.

Summary - PN Junction at Equilibrium
εbi , Vbi
P+ P+ B- B-
P+ P+ B- B- Schematic
N P+ P+ B- B-
P Diagram
P+ P+ B- B-
EC
qVbi Energy
Band
Diagram
EF
E
EV

The built-in voltage (Vbi) is a “hill” or “energy barrier” on the band diagram, and exists only across the depletion region (as
indicated by the sloped bands), because all of the charge is contained there. (Note that this is an idealization.)
The magnitude of the built-in voltage (i.e. the height of the hill) is equal to the difference between the two Fermi levels before
contact. It follows that increasing the dopant concentration in one or both sides of the junction will result in a larger built-in
voltage.
* Note: To be specific, equilibrium means: (1) no applied voltage; (2) no electric or magnetic fields present; (3) thermal
equilibrium (no thermal gradients in the device); (4) no mechanical stress; (5) no external sources of excitation (e.g. no light or
radiation).

Equilibrium - Energy, Voltage, Field, & Charge
metallurgical junction
N W P
-xn 0 xp
E
EC or EV
Electron Energy (from band diagram)
x
V
E
Voltage Vbi V =−
x q
ε
Electric Field 0
x ε = − dV
dx
ρ abrupt junction
qND
2
ρ ~−d
+ V
Charge Density 0 2
dx
- x
NAxp = NDxn -qNA

This graph shows the electron energy, voltage, electric field, and charge density (charge per unit volume) as a function of position (x) across the PN
junction at equilibrium (x = 0 is the junction line, sometimes referred to as the metallurgical junction). This is an abrupt junction or step junction
because the doping concentration changes from ND to NA abruptly (step function at the metallurgical junction), and hence the charge density changes
abruptly from +qND to -qNA. (In contrast to a graded junction, where the doping concentration, and hence the charge density, changes gradually – such as
the linearly graded junction discussed later in this module.)
xn and xp denote the width of the depletion region in the N-type and P-type sides, respectively, and thus the depletion region extends from –xn to +xp (i.e.
W = xn + xp). Note that all of the “action” takes place inside the depletion region; the bulk regions away from the junction are neutral (i.e. flat bands, no
net charge, no electric field, no voltage drop).
The energy curve is taken from the band diagram (Ec or Ev) . The band diagrams we have been using thus far are somewhat idealized, in that the outer
edges of the depletion region are assumed to be sharply defined and the charge becomes zero right at the edges (step functions). A more realistic band
diagram is shown here, where the edges are not sharply defined, and the charge decays to zero at the edges.
The shape of the voltage curve can be obtained by flipping the energy curve (Ec or Ev) upside down, because E = -qV, or V = -E/q. This reinforces the
fact that a voltage drop exists where the energy bands are sloped (the steeper the slope, the greater the voltage drop). Stated another way, if the electron
energy is higher at one location than another, there must be a voltage drop between those two points (by definition).
The electric field plot can be obtained from the slope of the voltage plot, since ε = -dV/dx. The peak electric field occurs right at the junction.
The charge density can be obtained from the slope of the electric field, since ρ ∼ -d2V/dx2.* Again, we often idealize the depletion charge as two
“blocks” of uniform charge as shown by the dashed line in the diagram. This gives the triangular electric field plot shown by the dashed line. Charge
neutrality requires that NAxp = NDxn, a convenient expression relating the depletion depth on either side to the doping concentrations (intuitively, if the
doping concentration on one side is lower than the other, the depletion region in that side must be larger to uncover enough charge to achieve balance).
* Do not confuse the charge density here with the resistivity discussed in the previous module; they both happen to be represented by the Greek letter rho
(ρ), but they are different quantities.

PN Junction at Equilibrium - Useful Equations
The following equations are valid for an abrupt (step) junction with uniform doping on both sides.
Built-in Voltage
EFN = Fermi energy level, n-type side (eV) nn = electron concentration, n-type side (cm-3)
EFN − EFP kBT ª nnpp º EFP = Fermi energy level, p-type side (eV) pp = hole concentration, p-type side (cm-3)
Vbi = = ln « 2 » q = elementary charge (1.602x10-19 coul.)

kB = Boltzmann constant (8.62x10-5 eV/K)
ni = intrinsic carrier concentration (cm-3)
ND = dopant concentration, n-type (cm-3)
q q «¬ ni »¼ T= temperature (K)
kBT = thermal energy = 0.260 eV at 300 K
NA = dopant concentration, p-type (cm-3)
kBT/q = thermal voltage = 0.260 V at 300K
in the extrinsic temperature region, nn ≈ ND and pp ≈ NA
Depletion Region Width (equilibrium)

2εsVbi NA
xn = ⋅
q ND ( NA + ND ) 2εsVbi ( NA + ND )
W = xn + xp = εs = permittivity of semiconductor
(1.036x10-12 F/cm for Si)
xp =
2εsVbi
⋅
ND qNAND
q N A ( NA + N D )
Junction Capacitance (equilibrium)

εsA εsA
Cj 0 = = A = area of junction
W 2εsVbi ( NA + ND )
qNAND
If the doping concentration on each side of the junction is known, the built-in voltage, depletion region width, and capacitance
of the junction can be calculated for the equilibrium condition (i.e. no applied voltage). These equations are valid for an abrupt
(step) junction with uniform doping on both sides.
Built-in voltage: Note that the built-in voltage is simply the difference between the two Fermi levels before contact (dividing
by q converts energy to voltage). This makes sense based on our earlier discussion of how the built-in voltage arises - the band
diagrams slide vertically until the Fermi levels line up, thus the height of the potential hill is just the difference between the
Fermi levels prior to contact. Increasing the doping concentration on one or both sides of the junction will pull the pre-contact
Fermi levels farther apart, thus increasing Vbi. (Vbi is typically 0.5 – 0.8 volts.) Temperature dependence: This equation can be
misleading wrt. temperature. The kBT/q term in front suggests that Vbi increases as T increases. However, recall that nn and pp
will approach ni as the temperature increases, thus reducing Vbi. In the intrinsic temperature regime, nn → ni and pp → ni, thus
the natural log term goes to zero and Vbi → 0; i.e. both sides of the junction look like intrinsic silicon (as if there were no
junction at all) – both Fermi levels are at mid-gap (EFN = EFP = Ei) and there is no barrier.
Depletion region width: The depletion region can also be calculated from the doping concentrations. Temperature
dependence: Per the discussion above, as the temperature increases the Fermi levels move toward mid-gap and W is decreased.
In the intrinsic temperature region, EFN = EFP = Ei, indicating that both sides of the junction look like intrinsic silicon (as if there
were no junction at all), and W = 0. It can be shown that W goes approximately as T-3/2.
Junction Capacitance: The charge separation in the depletion region gives rise to a capacitance. The simplest model is to treat
it like a common parallel plate capacitor, with charge fluctuating in two thin sheets at the outer edges of the depletion region,
thus Cj = εsA/W (more on this later). More sophisticated models would take into account the shape of the charge distribution as
well as fringing capacitance.
Later, we will see how applying a voltage to the PN junction modulates W and Cj. The expressions presented here are valid only
at equilibrium.

PN Junction - Forward Bias
I
T Forward Biased: P-side at positive potential wrt. N-side
T Depletion Region Narrows
N P T Energy Barrier Height Decreases by amount qVA
T Some carriers overcome barrier - traverse depletion region
- + T Diode is “ON” - diffusion current I (~mA)
Forward Biased VA
PN Junction
q(Vbi-VA)
qVA EC
Energy
Band
Diagram
EFN
qVA
E EFP
qVA EV
Equilibrium (VA=0)
W Forward Biased
W(eq.)

We will now discuss what happens when a voltage is applied across the PN junction. Since a voltage source has two terminals,
positive and negative, it follows that there are two ways to bias the junction. They are called forward bias and reverse bias. We
will examine forward bias first.
When the N-side is held at a negative potential relative to the P-side, the PN junction is forward biased. The applied voltage (VA)
acts to reduce the height of the barrier or potential “hill”, as shown. Thus, some electrons can now overcome the barrier and
diffuse from the N-side to the P-side. Similarly, holes can diffuse from the P-side to the N-side. Hence, a diffusion current is
observed and the device is considered “on”.
We will take a more detailed look at forward bias shortly.

PN Junction - Reverse Bias
I0
T Reverse Biased: N-side at positive potential wrt. P-side
T Depletion Region Widens
N P T Energy Barrier Height Increases by amount qVA
T Carriers can not overcome barrier - no diffusion current
+ - T Diode is “OFF” - BUT, there is a tiny leakage current I0 (~pA)
Reverse Biased VA
PN Junction
qVA EC
q(Vbi+VA)
Energy
Band
EFP
Diagram
EFN qVA
E
qVA EV
Equilibrium (VA=0)
Reverse Biased
W(eq.)
W
With the opposite polarity of applied voltage, the N-side is held at a higher potential than the P-side, and the PN junction is reverse
biased. Notice that the applied voltage increases the potential hill on the band diagram, and the carriers can not diffuse across the
junction. The device is “off”. (A small leakage current does exist through the device, which will be discussed shortly.)
The PN junction behaves like a diode*, an electronic device that conducts current in one direction (polarity) but not the other.
* Note: Not all diodes are PN junctions. Other types of semiconductor diodes exist - e.g. Schottky diode, PIN diode, etc. The
right diode for the job depends on the application – they all have the same fundamental behavior characteristic of a diode (e.g. the
exponential forward I-V) but differ in the details (e.g. maximum switching speed, etc.). These various diodes are not discussed in
this course. However, this course does provide a basic background in device physics, so that you will be able to study and
understand these devices (and many others), e.g. by consulting an introductory text on the subject.

Forward Bias, A Closer Look . . .
Barrier = q(Vbi - VA)
n(E) = ³f(E)*gc(E)dE
Electron
Diffusion
Current
qVA
EC
from supply
recombination
EFN
• recombination qVA
•E FP
qVA EV
Hole from supply
Diffusion
Current
W
Lp Ln p(E) = ³[1-f(E)]*gv(E)dE
Quasi- Quasi-
-
Neutral Neutral
Region + Region
Lp= hole minority carrier diffusion length

VA Equilibrium (VA=0)
Ln = electron minority carrier diffusion length Forward Biased

A more detailed look at forward bias.
If you understood how equilibrium is achieved in the PN junction, you will recognize forward bias as tipping the scales back in favor of diffusion (vs. drift).
The Fermi levels are separated “in the direction of diffusion” by an amount qVA and are held there by the applied bias*. (When the applied bias is removed,
the Fermi levels will quickly re-align, restoring equilibrium.) Electrons in the tail of the Fermi distribution with energy greater than the (lowered) barrier
diffuse across the junction from N-side to P-side. Similarly, holes diffuse from P-side to N-side.
The electron minority carrier diffusion length (Ln) represents the mean free path of an electron injected into P-type material (i.e. wherein it is the minority
carrier). It is how far the electron will travel, on average, before recombining with a hole. Typically, this is on the order of a few microns. Obviously, it
depends on the dopant concentration on the P-side (NA) – for heavier doping there are more holes/cm3, so injected electrons will travel a shorter distance on
average before recombining. The hole minority carrier diffusion length (Lp) is analogous.
The region within Ln of the depletion region edge on the P-side is called the quasi-neutral region; it is where the recombination takes place. And similarly
for holes injected into the N-side.
The power supply provides new carriers to replace those that recombine, thus sustaining the current. Hence, the forward-bias diffusion current is determined
by the recombination rate in the quasi-neutral regions. (Note that some recombination also takes place inside the depletion region itself, but this is ignored
for the “ideal” diode discussed here.) A higher recombination rate means more current.
Note that the depletion region narrows in forward bias – less uncovered charge is required to sustain the reduced voltage drop (Vbi – VA).
* The applied voltage is shown “connecting to” the Fermi levels on the diagram because it shifts the Fermi distributions relative to each other by an amount
qVA (i.e. the electron potential on one side is lower than the other), and the easiest way to represent this is to treat the Fermi level like a “handle” which the
applied voltage can grab and slide vertically, translating the entire Fermi distribution with it.

Reverse Bias, A Closer Look . . .
Barrier = q(Vbi + VA)
from supply
electron drift qVA EC
current
thermal
generation
•E FP
EFN
• qVA
thermal qVA EV
generation
hole drift
from supply current
W
Lp Ln
Quasi- Quasi-
Neutral Neutral
Region
+ - Region
VA
Equilibrium (VA=0)
Reverse Biased
A more detailed look at reverse bias.
The Fermi levels are separated and held apart by the applied voltage. The barrier height is increased, thus further inhibiting
diffusion current across the junction. If you understood how equilibrium is achieved in the PN junction after contact, you will
recognize reverse bias as tipping the scales in favor of drift (vs. diffusion).
Recall that electrons (minority carriers) are thermally generated throughout the P-side (assume the sample is at room temperature).
Those electrons generated inside the quasi-neutral region on the P-side can diffuse to the edge of the depletion region, where they
will be swept across by the electric field. Similarly, holes (minority carriers) thermally generated in the quasi-neutral region on the
N-side can diffuse to the edge of the depletion region and be swept across. Thus, a minority carrier drift current exists in the
device, referred to as reverse saturation current or leakage current. It is small, however, because the supply of minority carriers in
the quasi-neutral regions is small (the current is supply-limited). The reverse current or leakage current is governed by the thermal
generation rate. (Note that some generation also takes place inside the depletion region, but this is ignored for the “ideal” diode
discussed here.)
Note that the depletion region widens in reverse bias – more charge is required for the larger electric field (Vbi + VA).
Aside: Note that I0 is present in the device under forward bias as well, because thermal generation is always taking place.
However, I0 is negligible compared to the diffusion current.

Energy, Voltage, Field, & Charge Revisited
Reverse Bias Forward Bias
equilibrium
applied bias N W P N W P
-xn 0 xp -xn0 xp
E E
Electron Energy
x x
V V
Vbi+VA
Voltage
x Vbi - VA x
ε ε
Electric Field 0 0
x x
ρ ρ
qND qND
+ +
Charge Density 0 0
- x - x
NAxp = NDxn -qNA NAxp = NDxn -qNA

This graph shows the electron energy, voltage, electric field, and charge density for forward and reverse bias compared to
equilibrium. In reverse bias, the energy barrier or “hill” is increased, the voltage drop across the junction in increased (Vbi + VA),
the electric field in the depletion region is larger (in magnitude), and the depletion region expands to uncover more charge. Under
forward bias, the energy barrier is reduced, the voltage drop across the depletion region is reduced (Vbi – VA), the electric field is
smaller (in magnitude), and the depletion region shrinks. (Note that, per our earlier discussion, the idealized “block” charge
approximations have been used here for illustration purposes.)

PN Junction - Useful Equations Revisited
The following equations are valid for an abrupt (step) junction with uniform doping on both sides.
Depletion Region Width
2εs (Vbi − VA) NA

xn = ⋅
ND ( NA + ND )
q
2εs (Vbi − VA)( NA + ND ) VA = applied voltage (equilibrium VA=0;
W = xn + xp = fwd bias VA>0; rev bias VA<0)
qNAND
2εs(Vbi − VA) ND
xp = ⋅
q NA ( NA + ND )
Junction Capacitance
∆VA → ∆W → ∆Q
εsA Cj 0 εsA ∆W ∆W
C= = where Cj 0 =
2εsVbi ( NA + ND )
j
1
W N W P
ª Vº 2
«¬1+ V »¼
A
qNAND
bi electrons move to holes move to
cover/uncover P+ cover/uncover B-
ions as needed ions as needed

We revisit our earlier expressions for W and Cj to include the effect of the applied voltage VA. We also take a closer look at how the depletion region
responds to changes in applied voltage.
Depletion region width
The equilibrium depletion region width is calculated by setting VA = 0 (no applied voltage). Note that the depletion region widens under reverse bias (VA < 0)
and narrows under forward bias (VA > 0), as discussed previously.*
* Aside – Technical Note: This equation is not valid for V ≥ V , a condition which violates Kirchoff’s voltage law. Since all of the voltage drop occurs
A bi
across the depletion region for an ideal diode, W = 0 implies that there are no voltage drops in the device. The only way to remove this restriction is to allow
for the voltage drops in the quasi-neutral and neutral regions, which are not taken into account for the ideal diode but are in fact present in a real diode.
Junction capacitance
Note that under forward bias (VA > 0), W narrows and the capacitance increases*. Similarly, under reverse bias (VA < 0), W widens and Cj decreases. Thus,
the junction capacitance is modulated by the applied voltage. By substituting the expression for W, we can write the expression for Cj in terms of the applied
voltage VA, where Cj0 is the zero-bias depletion capacitance discussed previously. In order to tailor Cj to non-idealities or unknowns, such as the junction
grading, the exponent of “1/2” in this equation is sometimes replaced with a variable “m”, where m is typically a fitting parameter in the range 1/2 to 1/3.
* Aside – Technical Note: The expression for C is valid for small forward-bias voltages up to about V /2. Near this point, the capacitance begins to saturate
j bi
and then decrease somewhat. This is not reflected in the expression for Cj above.
A Closer Look: An incremental change in applied voltage ∆VA causes majority carriers at both edges of the depletion region to move, covering or uncovering
more depletion charge (e.g. B- and P+) as needed to sustain the new voltage (VA ± ∆VA). Thus, the junction has two sheets of charge fluctuating on either
side of a dielectric-like region of thickness W, analogous to a common parallel-plate capacitor**. Majority carriers have a very fast response (relaxation) time
(~10-10 – 10-12 sec.), and hence can keep pace with even high-frequency changes in VA (e.g. as from a small-amplitude ac signal that superimposes some
time-varying ∆VA about some dc bias VA ).
** The depletion region behaves like a dielectric (insulator) because it is a very high-resistance path (i.e. contains very few mobile charge carriers). Under reverse bias, changes in applied voltage
cause fluctuations in charge at the outer edges of W, with very little charge flowing across W. Thus, it approximates the behavior of a dielectric. Again, we note that this parallel-plate model is only
an approximation; more sophisticated modeling can be done, taking into account the actual charge distribution, fringing capacitance, etc.

PN Junction - Drift & Diffusion Currents
J = Jp + Jn The total current through the junction is the

sum of the electron current and hole current.
where:
Jn = Jn(drift ) + Jn(diff ) The electron current, in turn, is made up of drift and

diffusion current components. So is the hole current.
Jp = Jp (drift ) + Jp (diff )
ε = qµ nε
where:
Jn(drift ) = σ n
The drift current is calculated
from Ohm’s Law.
J (drift ) = σε = qµ pε
q = elementary charge (magnitude) = 1.602x10-19 coul.
p p µp = hole mobility [= 480 cm2/(V.s) for Si, room temp.]
and:
dn
Jn(diff ) = qDn The diffusion current is calculated
dx from Fick’s law.
dp DN = electron diffusion coefficient [= 33.75 cm2/s for Si at 300 K]

Jp (diff ) = − qDp Dp = hole diffusion coefficient [=12.4 cm2/s for Si at 300 K]
dx
J is the current density, i.e. the current per unit area through the junction. J = I/A, where I is the current and A is the cross-
sectional area of the junction.
The total current through the junction is the sum of the electron current through the junction and the hole current through the
junction.
The electron current, in turn, is made up of the electron drift current and the electron diffusion current. The hole current is made
up of the hole drift current and the hole diffusion current. (Note that at equilibrium the drift and diffusion components are equal
but opposite, maintaining a dynamic equilibrium and zero net current.)
The drift current can be calculated from Ohm’s Law. In the previous module, we used Ohm’s Law in the form V = I R. Here, we
use it in the equivalent form J = σ ε, where σ is the conductivity (discussed in the previous module) and ε is the electric field.
(To convert this back to the form V = I R, simply make the substitutions R=ρL/A, σ=1/ρ, and ε = V/L.)
The diffusion current can be calculated from Fick’s first law of diffusion, which states that the diffusion rate (particles per unit area
per unit time) is directly proportional to the concentration gradient (dn/dx or dp/dx). The proportionality constant, D, is called the
diffusion constant. Multiplying by q (the elementary charge) puts it in terms of coulombs per unit area per unit time, or current
density. (The negative sign in the hole diffusion equation results from the fact that the hole concentration gradient is in a direction
opposite to the electron concentration gradient).

Ideal Diode - Current-Voltage Characteristic
Ideal Diode: I-V Characteristic I

ª
I =I «
0 « exp
§
¨ qVA ·¸−1º»
«¬
¨¨
© kBT ¸¸¹ »»¼
0
VA
Ideal Diode: Reverse saturation/leakage current I0
2 ª Dn Dp º Reverse Bias Forward Bias

I 0 = qA ni « L nN A + L pN D » (Off / Leakage) (On)
¬ ¼
Dn = electron diffusion coefficient [= 33.75 cm2/s at 300 K]
Dp = hole diffusion coefficient [=12.4 cm2/s at 300 K]
I0 I diode circuit
Ln = electron minority carrier diffusion length [~ 10 µm]
symbol
Lp = hole minority carrier diffusion length [~10 µm]
N P
Diffusion coefficient can be calculated from mobility N P
+ - - +
D kBT
= (Einstein relationship) VA VA
µ q

The preceding current equations can be combined with the following assumptions to derive the ideal diode equation.
The ideal diode has the following assumptions:

• Abrupt PN junction, uniformly and nondegenerately doped on each side.
• Low-level injection (np << pp and pn << nn ). Under forward bias, the concentration of electrons being injected into the P-side (np) as minority carriers is
small compared to the concentration of holes (majority carriers) present in the P-side (pp) (note that pp ≈ NA). And similarly for holes being injected into the
N-side. The basic idea is that the amount of minority carrier injection is small, so the concentration of minority carriers in the quasi-neutral regions remains
small compared to the concentration of majority carriers, and recombination is very efficient.
• No series resistance. All of the voltage drop is assumed to occur across the depletion region. There is no resistance in the bulk (neutral) or quasi-neutral
regions, contacts, etc.
• No generation/recombination in depletion region (only in quasi-neutral regions).
• No external sources of carriers. e.g. no illumination, etc.
Note that the reverse saturation/leakage current is constant wrt. applied voltage; increasing the reverse-bias voltage makes the slope of the band diagram
steeper, but this does not change the current, which is supply-limited by the thermal generation rate in the quasi-neutral regions (see next slide). Band gap
dependence: I0 is larger for a semiconductor material with a smaller band gap EG (because ni is larger). Temperature dependence: I0 is larger for higher
temperature (because ni increases exponentially with temperature). Doping dependence: Note that doping either (or both) sides more heavily will reduce the
minority carrier concentration (per np = ni2) and hence I0.
The forward-bias current increases exponentially with applied voltage. If you visualize the Fermi distribution superimposed on the band diagram, and then
visualize lowering the barrier down this distribution’s tail, you can understand qualitatively why the forward current is exponential wrt. applied voltage, as
opposed to linear (ohmic) or sub-linear. You can also see why the “knee” of the forward-bias I-V occurs near VA = Vbi, where the barrier height is reduced to
zero. Increasing the voltage even a small amount beyond this point results in a very sharp increase in current. The PN junction is sometimes referred to as a
rectifying contact (as opposed to an ohmic contact), because the forward-bias voltage drop across the device is limited to (approximately) the knee voltage, as
the sharply-increasing portion of the I-V curve shows.

Reverse Current - Analogy
I0
I0 I0
h
waterfall I0
I0 h I0
I0
I0 I0
q(Vbi + VA)
I0 I0 I0
reverse-biased q(Vbi + VA)
PN junction

An analogy to explain why the reverse-bias current is saturated, i.e. constant wrt. the applied voltage.
Consider a river with current I0. Assume the river flows over a short waterfall: the current flowing down the waterfall and out of
the base of the waterfall must also be I0 (unless there is a large elephant drinking water at the bottom!). Now, assume that same
river encounters a tall waterfall instead of the short one. Still, it is the case that the water flowing down the waterfall and out of the
base of the waterfall is I0 (water is not being added or removed anywhere along the path). Basically, the current is supply-limited,
and the height of the waterfall has nothing to do with the amount of current. The height does influence the speed (kinetic energy)
with which water hits the bottom. Sitting under the short waterfall on a hot day might be pleasant, sitting under the tall one might
be painful - the water gains more kinetic energy, because it falls (accelerates) longer.
Similarly, increasing the reverse bias on a PN junction increases the height of the potential hill on the band diagram, but this does
not change the current (i.e. the number of electrons flowing down the hill per unit time), only the amount of kinetic energy the
electrons gain in crossing the junction. (If they gain too much kinetic energy, this can cause problems, as discussed later.) Like
the waterfall example, the current in a reverse-biased PN junction is supply-limited, and is not influenced by the height of the hill.

PN Junction Diode - Non-Idealities
IRs
Deviations from the ideal:
Generation / Recombination
in Depletion Region
slope ≈ q/2kBT
I=I
ª
«
0 « exp
§
¨ qVA ·¸−1º» + qAniW ª
«
exp
§
¨ qVA ·¸−1º»
slope = q/nkBT «¬
¨¨
© nkBT ¸¸¹ »»¼ 2τ 0
«
«¬
¨¨
© n 2 kBT ¸¸¹ »»¼
(n = 1 for ideal)
(f) Ideality Factor
τ +τ
| J/J0 |
τ =
n p
where 0
2
Forward bias (VA > 0): Exponential increase in recombination current.
~√VA VBR Reverse bias (VA < 0): Increase in generation current goes as W ~ √VA.
slope = q/n2kBT
n = diode ideality factor [n = 1 for ideal diode, n > 1 for non-ideal]
n2 = a slope factor for the second term [n2 → 2 is typical]
τn = electron minority carrier lifetime [~1µs typical]
τp = hole minority carrier lifetime [~1µs typical]
τ0 = effective (average) minority carrier lifetime
aside: Ln ≡ Dnτn
Lp ≡ Dpτp
q|VA|/kBT source: S.M. Sze, Physics of Semiconductor Devices, John Wiley
& Sons, 1981, p. 91; and G.W. Pierret, Modular Series on Solid
State Devices, vol. 2, Addison-Wesley Publishing, 1988, p. 83-85.

The ideal diode model is simple, but not realistic enough. This graph compares an ideal diode I-V to a real one. Note that the vertical axis is current density (i.e. J = I/A). It is normalized to (divided
by) the reverse saturation or leakage current density, denoted J0. Also note that it is the absolute value (magnitude) of the current, hence the forward-bias and reverse-bias I-V’s fit nicely into the same
quadrant of the graph. Also note that the horizontal axis is q|VA|/kBT, essentially a constant multiplied by the applied voltage (magnitude).
Different portions of the I-V curve are labeled to highlight the differences between the ideal diode and a real one. An ideality factor, n, is introduced into the exponential term of the ideal diode equation
to take into account deviations from the ideal forward-bias I-V slope (n = 1 for an ideal diode, and real diodes typically have n in the range of 1 to 2). This ideality factor takes into account non-idealities
in the diode structure or fabrication – e.g. the grading of the junction, which may be difficult to determine (assumed abrupt for the ideal diode). A second term has been added to the ideal diode equation
to account for generation and recombination in the depletion region (more on this below).
Non-Idealities - Reverse Bias:

e. Generation in the depletion region.* Thermal generation takes place inside the depletion region of a (real) PN junction (i.e. electron-hole pairs are liberated from Si-Si bonds, at some rate
determined by the temperature). Under reverse bias, these carriers are swept out by the electric field and contribute to the reverse current; hence the reverse current is higher than that of the ideal diode
(which ignores generation in the depletion region). Furthermore, recall that in reverse bias W widens as √VA. As W widens, generation takes place throughout a larger volume, and hence the reverse
current also increases as √VA, as shown on the graph. This is also captured in the equation presented above: For reverse bias (VA < 0), the expression rapidly reduces to -(I0 + qAniW/2τ0). The first
term is of course the ideal reverse saturation current. The second term is the generation current one would expect assuming that thermal generation takes place uniformly throughout the depletion region
at a constant rate (determined by the temperature). The constants τn and τp are the electron and hole minority carrier lifetimes, respectively. The lifetime is a measure of how long an excess minority
carrier will “survive” in a sea of majority carriers – i.e. if a minority carrier is generated in a sea of majority carriers, it will exist for a time τ (statistically) before recombining. (Note the relationship
between the minority carrier diffusion length L and the minority carrier lifetime τ.) The value of τ can vary widely depending on the fabrication details of the PN junction; it can take on values ~1ns to
~1ms, with typical values ~1µs. Note also that any impurities (mid-gap states/traps) present in the depletion region can act as generation centers and increase to reverse current.
f. Junction breakdown. When the reverse-bias voltage reaches the breakdown voltage (VA = VBR), a large reverse current is observed. This phenomenon is discussed in detail later.
Non-Idealities - Forward bias:

a. Recombination in the depletion region.* Electrons and holes traversing the junction under forward bias recombine in the depletion region (this was ignored for the ideal diode). Recall that each
time a recombination event occurs in the device, new carriers are supplied by the battery or power supply. Therefore, an increase in recombination rate necessitates an increase in the current through the
device. The second term in the equation accounts for recombination in the depletion region, which increases exponentially with forward-bias (VA > 0), because the concentration of carriers crossing the
junction increases exponentially. This term also contains a slope-fitting parameter, n2 (n2 → 2 is typical). This effect is most pronounced at lower applied voltages, before the depletion region shrinks
too much (W ~ √(Vbi – VA) → 0 for forward bias, causing the second term in the equation to disappear leaving only the ideal diode term – this corresponds to the (a)-to-(b) transition on the graph). Note
that any impurities (mid-gap states/traps) present in the depletion region can act as recombination centers, contributing to the recombination current.
b. Ideal behavior. In this region of the I-V, the ideal diode assumptions hold up very well.
c. High-injection. The low-level injection assumption of the ideal diode does not hold at higher applied voltages. High-injection of carriers across the junction reduces the recombination efficiency
(np → pp and pn → nn in the quasi-neutral regions), hence reducing the current through the device vs. the ideal diode.
d. Series resistance. The ideal diode assumes that all of the voltage drop occurs across the depletion region; i.e. the bulk regions and contacts have zero resistance. In a real diode, the resistance of
these regions can not be ignored. It can be modeled as a resistor Rs in series with the junction. For a given applied voltage VA, the voltage drop across this parasitic resistance (IRs ) reduces the voltage
drop across the junction (Vj = VA - IRs) and hence reduces the current. This effect is most pronounced at high currents, where the IRs drop is greater. Whereas the ideal diode equation predicts
unrealistically large currents for forward biasing beyond the “knee” voltage, in reality the current is ultimately limited by the series resistance effects.
* Generation and recombination in the depletion region can be thought of as a natural “restoring force” in the PN junction. When the carrier concentrations are reduced from their equilibrium values in
the general vicinity of the junction by a reverse-bias (widening of the depletion region), generation increases in an effort to increase the carrier concentrations back toward their equilibrium values.
Similarly, when the carrier concentrations in the depletion region are elevated by carrier injection due to forward bias, recombination increases so as to reduce them back toward their equilibrium values.

PN Junction Diode - Reverse Breakdown
I
Junction
Avalanche Breakdown Voltage Breakdown
2
VBR = εs ε NA + ND
CR
VBR 0
VA
2q NAND I0
ε CR = critical field for impact ionization [= 4x105 V/cm for Si]

Increasing the doping on either or both sides of
the junction decreases the breakdown voltage.

A large current arises when VA = VBR , called the reverse breakdown voltage or junction breakdown voltage. Note that breakdown
is not necessarily destructive to the diode.
There are two mechanisms for junction breakdown:

1. Avalanche Breakdown (impact ionization) - most common
2. Zener Breakdown (tunneling) - if both sides of junction are heavily doped

PN Junction Diode - Reverse Breakdown (cont.)
|VA| > |VBR| both sides heavily doped

impact *
ionization * |VA| > |VBR|
events
* - EC
*
EC direct
band-to-band
-
EV
+ tunneling
from supply
EV
an impact
ionization electron-hole
event EC pair creation
Si
+ narrow
EV bands
electron-hole Si
pair creation
Avalanche Breakdown Zener Breakdown

Avalanche breakdown begins when the applied reverse-bias voltage is so large that the minority carriers traversing the depletion
region gain sufficient kinetic energy to cause impact ionization. Impact ionization occurs when an energetic (aka. “hot”) carrier
collides with a Si atom, breaking Si-Si covalent bonds and forming electron-hole pairs. These electrons and holes are then
accelerated by the high electric field, and can go on to cause subsequent impact ionization events – i.e. an “avalanche” of energetic
carriers, causing a large reverse current. Note that impact ionization is typically caused by electrons; holes have a lower mobility
and are difficult to accelerate to impact ionization speed. Note also that the breakdown voltage decreases as the doping
concentration on either or both sides of the junction increases. Increasing the doping concentration will increase the difference
between the Fermi levels (EFN and EFP), thus creating a larger built-in voltage (potential hill) when they are combined to form the
junction. This larger built-in voltage means that less reverse-bias voltage is required to accelerate carriers to ionization speeds,
hence a lower breakdown voltage is observed for the device.
Zener breakdown occurs in PN junctions which are heavily doped on both sides. The band “stretching” becomes so severe that
direct band-to-band tunneling occurs. This results in a reverse “tunnel” current.

PN Junction Diode - One-Sided Junction
ND >> NA NA >> ND
W W
P+ B- P+ B-
N+ P+ B- P N P+ B- P+
P+ B- P+ B-
+
ε bi
- + ε bi
-
2εs (Vbi − VA) 2εs (Vbi − VA)

W= W=
qNA qND
VBR = εs CR ε 2
VBR = εs CR ε 2
2qNA 2qND

A one-sided junction means that one side is doped heavily (degenerately) and the other is not. The “+” indicates the heavily-doped
side (note: the “+” has nothing to do with electrical charge in this case, it only indicates which side is heavily doped). The PN
junctions shown above are one-sided abrupt (step) junctions.
Aside: In module 4, we will see that the source and drain regions of the transistor (MOSFET) are one-sided PN junctions.
The equations for the depletion region width and breakdown voltage can be simplified, as shown. Note that they are more
sensitive to the doping concentration on the lighter-doped side of the junction. The depletion region is contained mostly in the
lighter-doped side (recall that NAxp = NDxn for charge neutrality), therefore the voltage drop occurs mostly in this side, and this side
dominates the electrical characteristics of the diode. This side will also have a higher minority carrier concentration (per np = ni2),
and thus the larger leakage current component of I0.

Breakdown Voltage vs. Dopant Concentration


This graph shows the avalanche breakdown voltage vs. dopant concentration for a one-sided abrupt PN junction (NB denotes the
dopant concentration on the lighter-doped side of the junction). The dashed line indicates the dopant concentration beyond which
the Zener (tunneling) mechanism will dominate the voltage breakdown characteristic.

Aside: Linearly Graded Junction
metallurgical junction (NA = ND) implant profiles
NA(x)
N W P §− 2·
exp¨ x ¸
Q
NA( x ) = NA(x)
A πDt ¨ 4 Dt ¸
© ¹ abrupt graded
-xn xj xp
~ abrupt junction
NA - ND ~ linearly graded x
junction ND
slope = a ND
graded
0 junction illustration of shallow (abrupt)
Si x vs. deep (graded) junction
x surface xj xj
(abrupt) (graded)
NA – ND = ax
ρ ª12ε (V −V ) º
S bi A
3
W=
« qa »
+
¬ ¼
0 - x
ρ = −qax for -xn ≤ x ≤ xp 2kBT ª aWo º
ρ = 0 otherwise Vbi = ln « »
where W0 is the equilibrium
depletion region width (VA = 0)
q ¬ 2 ni ¼
ε Cj =
εAS
x W
1
§ 2ε ·2
4
ε
3 s 1
VBR =
3
2 ¨¨ ¸¸ a −
2
© q
C
abrupt junction (for comparison) ¹

Up to this point, we have been considering abrupt (step) junctions, where the doping concentration, and hence the charge, change abruptly (step function) at the metallurgical junction (xj). We
now examine what happens when non-abrupt junctions are formed.
For example, consider the common case where a P-type dopant such as boron is implanted into the surface of an N-type region, as illustrated above. (The situation for N-type dopant implanted
into a P-type region is analogous.) As implanted, the boron lies in a thin sheet in the Si surface. Subsequent thermal cycles will cause the boron atoms to diffuse, driving them deeper into the
sample (and laterally as well – diffusion is three dimensional). The boron concentration profile NA(x) is depicted in the graph above and described by the Gaussian function shown, where Q is
the implant dose in atoms/cm2 (the area under the curve), A is the implanted area, x is the depth into the sample (x = 0 denotes the Si surface in this equation), t is the total time for which
diffusion has taken place, and D is the diffusion coefficient* in cm2/s (depends on the dopant species and the semiconductor material, and increases exponentially with temperature). The
metallurgical junction is defined as the point where NA = ND. Higher temperature and/or longer diffusion time are conducive to diffusion and result in a greater (deeper) junction depth. Also
note that smaller atoms like boron have a higher diffusion coefficient than larger atoms such as indium or arsenic.
The profile for a shallow junction is shown on the graph, where the implanted boron is not diffused much into the sample (e.g. a shallow implant followed by rapid thermal annealing). This may
be treated as an abrupt junction - e.g. the source and drain regions of a MOSFET (discussed in module 4).
However, if the implanted boron is diffused deeper into the sample the result is a graded junction profile, where the net doping (NA – ND) changes gradually near the junction**. Shown above is
the special case of a linearly graded junction, where the net doping changes linearly (NA – ND = ax) in the vicinity of the junction and hence the charge density is modeled as two triangular
regions (where ρ = -qax). a is called the grading constant and has units of cm-4 (i.e. cm-3 per cm of x). The symmetry of the linearly graded junction requires that xn = -W/2 and xp = W/2 always
(as measured from the metallurgical junction). Grading the junction tends to make the electric field parabolic instead of triangular, and reduces the peak field.
Expressions are given above for the depletion region width, built-in voltage, junction capacitance, and reverse breakdown voltage of a linearly graded junction. Note that W has a cube-root
relation to the applied voltage, vs. the square-root relation for the abrupt junction. Also note that the expression for W contains Vbi, and visa versa, and thus an iterative solution is required for
these quantities.
Qualitatively, the physics of the graded junction is the same as for the abrupt junction (forward and reverse bias, diffusion and drift current, recombination/generation, reverse breakdown, etc.)
but the quantitative details change, as reflected in the mathematical expressions above for the special case of a linearly graded junction, where the grading constant a emerges as an important
quantity. The ideal diode model also assumed an abrupt junction, as noted at the time, but again the qualitative shape of the I-V characteristic remains the same, and the ideality factor n can be
used to adjust for junction grading (in practice no junction is perfectly abrupt).
• Previously, we encountered the diffusion coefficients/constants for the mobile charge carriers - electrons (Dn) and holes (Dp) - as they pertain to carrier diffusion inside a PN junction. Here,
we are using the diffusion coefficient of the dopant atom (D) - in this example, the diffusion of boron atoms in order to form a PN junction in N-type material. Although they are related, in that
they both arise from Fick’s first law of diffusion, be careful not to confuse them – one pertains to the diffusion at the atomic level to form a PN junction in the first place, the other pertains to the
diffusion of electrons and holes in an established junction.
** When P-type dopant is added to a region that is already N-type, or visa versa, this is called compensation. In other words, the effective doping concentration is the net doping concentration
|NA - ND|.

Aside: Non-Uniformly Doped Silicon
n(x)
= ND(x)
1 2
x
lower doping higher doping

concentration N-type Si concentration
§ EF − Ei1 ·
n1 = ni exp¨ ¸
© kBT ¹ EC
§ EF − Ei 2 ·
EF
n 2 = ni exp¨ ¸
© kBT ¹
n2 § Ei1 − Ei 2 · § qΨ12 · Ei
= exp¨ ¸ = exp¨ ¸
n1 © kBT ¹ © kBT ¹
EV

This is a topic that properly belongs in module 1. However, it was deferred to this point because we are now in a much better
position to tackle it, having discussed such topics as band bending, Fermi level alignment at equilibrium, etc.
Shown above is a case where the doping concentration (ND) varies with position (x) in a silicon sample. In the extrinsic
temperature region (e.g. near room temperature), it follows that n(x) = ND(x). The doping concentration gets higher in the
direction of increasing x, and hence so does the free electron concentration.
The band diagram shows how the bands bend to reflect the changing dopant concentration. To the left (smaller x) the dopant
concentration is lower, thus the free electron concentration is lower, and thus the Fermi level is farther from EC (closer to Ei) on the
band diagram. To the right (larger x) the sample is doped more heavily, so the electron concentration is greater, and the Fermi
level is closer to EC (farther from Ei). Note that the sample is at equilibrium, so the Fermi level EF is flat throughout the sample.
The Fermi level is like the water surface of a lake – it is flat (at equilibrium) regardless of the contour of the bottom of the lake.
(Similar to the PN junction, the shape of this band diagram can be constructed visually by considering thin “slices” of
progressively heavier-doped samples being assembled from left to right. The bands between two adjacent “slices” will bend such
that the Fermi levels align at equilibrium. When this is done for all “slices” throughout the sample, the band diagram shown in the
bottom diagram is the result. The band diagram for any arbitrary doping profile -- N-type, P-type, or both (e.g. compensation or a
junction) -- can be constructed using this method.)
Note that there are bent bands at equilibrium, indicating that there is a non-zero built-in electrostatic potential in the sample at
equilibrium. (This is analogous to the built-in voltage of a PN junction.)
Per the discussion in module 1, we can write expressions for the electron concentration at two arbitrary points 1 and 2 as shown
above. These can then be combined to get the ratio of the electron concentrations at these two points. The quantity Ei1 – Ei2 can be
expressed in terms of Ψ12, the electrostatic potential difference between the two points. In other words, the electrostatic potential
difference is Ψ = ∆Ei/q (= ∆EC/q = ∆EV/q ). (More on electrostatic potential in module 3.)

Exercise: Back-to-Back PN Junctions
E B C
N P N
In the space below, draw the band diagram for this structure at equilibrium.

Draw the band diagram for this N-P-N structure at equilibrium (assume that the sample is at room temperature, that each region is
uniformly doped, and that both junctions are abrupt). Hint: Remember that the Fermi levels must be aligned at equilibrium.
Don’t worry too much about the quantitative details, just try to get the qualitative picture right.
Label the depletion regions and built-in voltages on your diagram.

Exercise: Back-to-Back PN Junctions (cont.)
E B C
N P N
- + - +
VEB VBC
Draw the band diagram for this structure (E-B junction forward biased and B-C junction reverse biased).

Suppose the device is constructed such that the P-region is much narrower than Ln (the minority carrier diffusion length of
electrons). If we forward bias the E-to-B junction and reverse bias the B-to-C junction (see diagram), what would happen?
Specifically, would current flow through the device from E to C?
Have you ever seen this device before?

Exercise: Solution
E B C
N P N
EC •••••••••••••• qVbi qVbi ••••••••••••••

EF
Equilibrium
oooooooooooooooooo
EV
W W
EC ••••••••••••••
EF ••••••••••••••
Applied Voltages
EV ooooooooooooooo

When the E-B junction is forward biased, electrons flow from E to B. Since the B region is narrower than Ln, the electrons diffuse
through the B region (most of them, anyway) and are swept into the C region by the reverse-biased B-C junction. Hence, electrons
flow from E to C under these biasing conditions.
This device is called a Bipolar Junction Transistor, or BJT. Specifically, it is an NPN BJT. (A PNP BJT can also be
constructed, and its behavior is analogous, though the voltage polarities are opposite and the current is dominated by holes.)
The region labeled E is called the Emitter – under forward bias it emits or injects carriers into the B region, which is called the
Base. Most of the carriers diffuse across the base and are swept into the C region, called the Collector. A small fraction of them
recombine in the base, giving rise to a small base current. In typical applications, the (small) base current is used to control the
(larger) current flow through the device. Thus, the BJT behaves like an amplifier (i.e. the emitter-to-collector current is an
amplification of the much smaller base current). In digital electronics applications, the analog nature of the emitter-to-base current
is ignored, and the device is treated like a simple switch - i.e. on (conducting current) or off (not conducting).
Later, in module 4, we will study transistors, though our focus will be on a related but different style of transistor called the
MOSFET. While the physics of the BJT and the MOSFET are quite different, understanding PN junctions (and this N-P-N band
diagram) will help us understand the MOSFET.

3
The
MOS Capacitor
Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham 3-1
This is the third module in a five-module introduction to semiconductor devices. The modules are:

2. The PN Junction
4. The MOSFET
5. Small Circuits
Understanding the MOS capacitor is a key step toward understanding the MOSFET transistor, because the gate region of the MOSFET is a MOS capacitor.
The MOS capacitor is also an important semiconductor device in its own right, with a variety of applications in microelectronic circuits.
• Understand the band diagram for an ideal MOS capacitor

• Understand accumulation, depletion, inversion, and strong inversion (threshold)
• Understand the surface potential, and its relationship to the gate voltage and threshold voltage
• Understand how gate oxide thickness and substrate doping affect the surface potential and threshold voltage
• Understand how C-V testing is performed, and explain the shape of the C-V curve
• Understand the band diagram for a real (non-ideal) MOS capacitor, including the work function mismatch, flatband voltage, and oxide charge effects
• Understand all of the above for both a P-type MOS capacitor and an N-type MOS capacitor
Looking Back: We are prepared to study the MOS capacitor because we understand the electronic properties of N-type and P-type silicon from the first
module.
Looking Ahead: We will combine our knowledge of the MOS capacitor with our prior study of the PN junction to understand how a transistor (MOSFET)
works.
MOS Capacitor (Ideal) - Equilibrium
Metal (aka. the Gate)

Oxide (aka. the Gate Oxide)
Semiconductor
P-type
Three possible biasing regimes:

• Accumulation
• Depletion
• Inversion
“MOS” is short for Metal-Oxide-Semiconductor.
A capacitor is a circuit element which stores charge.
The MOS capacitor is formed using a metal such as aluminum for the “top plate” or gate, silicon dioxide (SiO2) as the dielectric or
gate oxide, and a semiconductor material such as silicon (N-type or P-type) as the “bottom plate” or substrate.
We will use P-type silicon for illustration, then summarize for the N-type case by analogy at the end of the discussion.
There are three possible biasing conditions for a MOS capacitor; they are called accumulation, depletion, and inversion. We will
study each in detail.
MOS Capacitor - Accumulation
- - - - - - -
M
O
- S o o o o o o o
VG Holes accumulate underneath
+ the oxide to balance the charge
on the metal/gate - surface
P-type “looks” more P-type
ps > NA
ps = hole concentration at semiconductor surface (cm-3)
The MOS capacitor is biased into accumulation when the gate is held at a negative potential relative to the substrate.
Recall that P-type material has an abundance of holes (the majority carrier). The negative bias on the gate causes holes to
accumulate underneath the gate oxide at the surface of the semiconductor. However, the holes can not travel through the oxide to
the negative terminal, because it is an insulator (dielectric) and hence is not conductive. The holes remain accumulated underneath
the oxide. The more voltage applied, the greater the accumulation.
The surface of the semiconductor “looks” more P-type than the bulk, i.e. ps > NA, where ps is the concentration of holes at the
surface and NA is the dopant concentration in the P-type semiconductor.
MOS Capacitor - Depletion
VG < VT + + + + + + +
Depletion M
O
+ S B- B- B- B- B- B- B- Depletion
W Region
VG
-
P-type
QG = -QD Uncovered charge in the depletion region (QD)

balances charge on gate (QG)
Charge in the depletion region

QD = qANAW (A = gate area)
As VG increases → QG increases → W increases → QD increases → QG = QD
When the gate is held at a positive potential relative to the substrate, the MOS capacitor is biased into depletion (provided that the
applied voltage is not greater than some threshold voltage, VT, described later). Holes are repelled from the semiconductor surface
by the positive charge on the gate, and thus the surface is depleted of majority carriers, leaving only the uncovered boron dopant
atoms. The charge in this depletion region balances the gate charge. As the applied voltage is increased, the depletion region
widens, uncovering more charge to maintain this balance.
The applied voltage drops across the gate oxide and the depletion region.
MOS Capacitor - Inversion
VG → VT +++++++
++++++++++++++
Inversion Electrons (minority carriers) pile up
M underneath the oxide → surface “looks” N-
O
+ S • • • • • • • type → surface inversion
B- B- B- B- B- B- B-
VG W
- B- B- B- B- B- B- B- (wider)
QG = - (QD + Qn)
P-type
VG = VT Surface looks as N-type as bulk is P-type

Strong ++++++++++++++ → strong inversion → threshold voltage
++++++++++++++
Inversion M
(Threshold) O
+ S ••••••••••••••
B- B- B- B- B- B- B- W = WT
VG (maximum)
- B- B- B- B- B- B- B-
P-type Depletion region reaches its maximum
width (WT) at threshold
As the applied voltage is increased further, electrons (minority carriers) begin to pile up underneath the gate oxide, forming an
inversion layer. The semiconductor surface is now starting to “look” N-type, hence the term “inversion”. Now, the charge on the
gate is balanced by the charge in the depletion region and the charge in the inversion layer.
When the threshold voltage (VT) is reached, the surface is “as N-type as the bulk is P-type”; i.e. the concentration of electrons in
the inversion layer (ns) is equal to the concentration of holes in the bulk substrate (NA). This will be a very important concept when
we discuss the transistor (MOSFET).
Introduction to Semiconductor Device Physics / MOS Capacitor / rev 4.3 Tom Cunningham 3 - 10
MOS Capacitor - Inversion (cont.)
VG > VT +++++++++++++++++++
+++++++++++++++++++
Beyond
M
Threshold O
+ S ••••••••••••••••••••••••
B- B- B- B- B- B- B- W = WT
VG (maximum)
- B- B- B- B- B- B- B-
P-type
As the applied gate voltage increases beyond threshold, the surface becomes more strongly inverted (ns increases).
Note that beyond threshold further increases in gate charge are compensated by increasing charge in the inversion layer; the
depletion region has reached its maximum width (W = WT) at threshold.
MOS Capacitor (Ideal) - Band Diagram, Isolated Materials
Ideal MOS Capacitor: φM = φS
M O S
EVAC
EC
qφM qφS
EC
EG(SiO2) ≈ 9 eV EG(Si) = 1.1eV

Ei
EFM EFS
delocalized electrons EV
P-Type
EVAC = vacuum level (free electron)

φM = metal work function EV
φS = semiconductor work function
We can construct an energy band diagram for the MOS capacitor. We will first consider an ideal MOS capacitor.
We begin by considering the band diagrams of the isolated components, before they are brought into contact. A work function φ is
defined for both the metal and the semiconductor; it is a measure of the amount of energy required to remove an electron from the
material entirely (i.e. to the vacuum level, EVAC), and is measured from the Fermi level as shown. For an ideal MOS capacitor, we
assume that φM = φS (note that this is equivalent to assuming that the Fermi levels line up).
Aside: If you are familiar with the photoelectric effect, you might have seen the work function φ before. Albert Einstein received
the Nobel Prize in Physics for his theoretical explanation of the photoelectric effect in the early 1900’s. The photoelectric effect
occurs when ultraviolet light is shined onto a metal surface, causing electrons to be “knocked out” of the metal surface by the
incident photons. If the incident light is of frequency ν, then the photon energy is E = hν (where h is Planck’s constant), and the
kinetic energy of the electrons emitted from the metal is E = hν - φ, where φ is the work function of the metal. In other words, φ is
the minimum amount of energy required to pull an electron out of the metal, and any additional energy supplied by the photon is
turned into the kinetic energy of the electron (in accordance with the conservation of energy).
MOS Capacitor (Ideal) - Band Diagram, Equilibrium
M
O
S Ideal MOS Capacitor: φM = φS
P-type
M O S
EVAC
qφM qφS
EC
EG(SiO2) EG(Si)
Ei
EFM EFS
EV
The materials are brought into contact to form the MOS capacitor. The Fermi levels align at equilibrium (analogous to the PN
junction discussion). Because we assume that the work functions are equal for the ideal case, there is no band bending (all energy
bands are flat) at equilibrium.
MOS Capacitor (Ideal) - Band Diagram, Accumulation
M
O
- - - - - - -
ε, VG
- S o o o o o o o +Qp
VG
+
P-type -QG
qVOX
M O S
EC
- EFM
EG(Si)
Ei
+
EFS
EV
M O S
Holes (majority carriers) accumulate underneath the
oxide to compensate the gate charge → surface
“looks” more P-type (ps > NA)
When the MOS capacitor is biased into accumulation, band bending occurs as shown (the potential energy of electrons in the
semiconductor is lowered wrt. the metal). Recall that hole energy increases downward on a band diagram (“holes like to float”).
Therefore, they follow the energy gradient and accumulate at the semiconductor surface, as previously discussed.
Recall that a voltage drop exists where bands are bent, i.e. across the oxide and the semiconductor surface. No voltage drop exists
where bands are flat.
The charge is represented in the upper right diagram. The negative charge on the gate is compensated by the equal but opposite
charge in the accumulation layer.
MOS Capacitor (Ideal) - Band Diagram, Depletion
+ + + + + + +
M
O
0 < VG < VT
+ S B- B- B- B- B- B- B-
W +Q G
VG
ε, VG
- W
P-type
-Q D
qVOX
M O S
VG = VOX + ΨS
VOX = voltage drop across oxide
ΨS = surface potential (voltage drop across W)
EC
+ qΨS qφB
EG(Si)
Ei -
EFS
qΨS
EFM EV
W
M O Depletion S
Region
In depletion, the bands bend as shown (the potential energy of electrons in the semiconductor are raised wrt. the metal).
Note that the electric field (voltage) drops across the oxide and the depletion region (where the bands are sloped). VOX is the
voltage drop across the oxide. ΨS is the surface potential, and represents the voltage drop across the depletion region of the
semiconductor. Therefore, VG = VOX + ΨS.
The quantity φB on the band diagram is the bulk potential (sometimes called the Fermi potential), the difference between the Fermi
level and the intrinsic Fermi level in the bulk of the semiconductor (i.e. far away from the surface, in the neutral region).
The charge diagram shows that the positive charge on the gate is balanced by the equal but opposite charge in the depletion region.
MOS Capacitor (Ideal) - Band Diagram, Inversion
+++++++
M
++++++++++++++
VG → VT ΨS → 2φ
φB
O +QG
+ S • • • • • • •
B- B- B- B- B- B- B-
ε, VG
VG W W→WT
- B- B- B- B- B- B- B- (wider)
P-type -QD
-Qn
qVOX
M O S
VG = VOX + ΨS
EC
Ei dips below EF → surface “looks”
+
N-type → onset of surface inversion
ª q(ΨS − φB) º
ns = ni exp«
¬ kBT ¼
ª q (ΨS − 2φB) º
» = NA exp«
¬ kBT »
¼ ΨS
qΨ
qφB
Ei
EFS
-
EV
EFM
W
(wider)
M O S
As VG gets closer to VT, electrons (minority carriers) begin to pile up at the silicon surface underneath the oxide, following the
gradient of the band diagram. These electrons come from thermal generation inside the depletion region.
The equation above relates the surface electron concentration ns to ΨS and φB. Note that for ΨS = φB, ns = ni (and hence EF = Ei at
the surface) as expected. This point where the surface looks intrinsic is the demarcation between depletion and inversion. As ΨS
increases beyond this “intrinsic” point, Ei dips below EF near the surface, indicating that the surface now looks N-type. This is
called surface inversion.
The charge diagram shows that the charge on the gate is now compensated by the depletion charge and the the inversion charge.
An incremental increase in gate charge causes both to increase somewhat to compensate.
* Note also that ns is not actually zero in depletion, but it is negligibly small - ns is much less than NA for ΨS << 2φB (negative
exponent).
MOS Capacitor (Ideal) - Band Diagram, Strong Inversion (Threshold)
++++++++++++++
M
O
++++++++++++++
VG = VT ΨS = 2φ
φB
+ S •••••••••••••• +QG
ε, VG
B- B- B- B- B- B- B- W = WT
VG (maximum)
WT
- B- B- B- B- B- B- B-
P-type -QD
-Qn
qVOX
M O S
VG = VOX + ΨS
EC
ΨS = 2φB → surface is as N-type as the

bulk is P-type (ns = NA) → “strong”
inversion → threshold voltage Ei
+ ª q(ΨS − φB) º
ns = ni exp«
¬ kBT
»
¼
= NA exp«
¬ kBT »
¼
ΨS
qΨ
qφB
EFS
EV
-
EFM
W = WT
(maximum )
M O S
At threshold, Ei lies as far below EF at the surface as it does above EF in the bulk. In other words, the surface is as N-type as the
bulk is P-type (ns = NA), and ΨS = 2φB. This is one common definition of the threshold voltage*.
*Technical Note: “Strong” inversion is sometimes defined as ΨS = 2φB + 6kBT/q (and hence ΨS = 2φB is “moderate” inversion).
(For a sense of scale, φB is about 0.4V for normal doping levels and 6kBT/q = 0.16V at room temperature.) This places VT well into
the exponential turn-on for ΨS > 2φB (positive exponent), where ns is significantly larger than NA and hence a “strong” channel is
present. The definition of the “strong” inversion or “threshold” point is somewhat arbitrary, because it is the assignment of a
discrete “turn-on” point to what is fundamentally an analog turn-on characteristic. For our purposes here, we will continue the
discussion in terms of the most basic and straightforward definition of threshold voltage, ΨS = 2φB, but we will mention the
alternate definition from time to time as well.
MOS Capacitor (Ideal) - Band Diagram, Beyond Threshold
+++++++++++++++++++
+++++++++++++++++++
VG > VT ΨS > 2φ
φB
ε, VG
M +QG
O
+ S •••••••••••••••••••••••• WT
B- B- B- B- B- B- B- W = WT
VG (maximum)
- B- B- B- B- B- B- B-
-QD
P-type
-Qn
qVOX M O S
VG = VOX + ΨS
EC
Ei
+
More electrons pile up at
semiconductor surface (ns > NA)
ª q(ΨS − φB) º
ns = ni exp«
= NA exp«
ΨS
qΨ
qφB
EFS
EV
-
» »
¬ kBT ¼ ¬ kBT ¼
EFM
W = WT
(maximum )
M O S
At threshold, the depletion region has reached its maximum width. Further increases in gate voltage are compensated by an
increase in the electron concentration in the inversion layer as depicted in the charge diagram; any increase in W is negligibly
small.
Additional gate charge beyond threshold is compensated by an increase in inversion layer charge, rather than depletion region
expansion, because ns increases exponentially with ΨS for ΨS > 2φB (positive exponent), whereas the depletion region expands as
√ΨS (see equation, next slide). Once a good channel forms, it effectively “shields” the depletion region below (i.e. the electric
field lines emanating from the gate charge terminate on the channel charge and are not “felt” at the far edge of the depletion
region). Hence, the inversion charge dominates the sub-gate dc electrostatics beyond threshold.
Summary:
P-Type MOS Capacitor Applied Surface Potential Surface carrier Additional gate charge
biased into: voltage concentration compensated by:
Accumulation VG < 0 ΨS < 0 ps > NA accumulation of holes (majority

carriers) at surface
Depletion 0 < VG < VT 0 < ΨS < φB ps < NA additional depletion charge
ns < ni (expansion of depletion region)
Inversion 0 < VG < VT φB ≤ ΨS < 2φB ni ≤ ns < NA additional depletion charge and
additional inversion layer charge
Strong Inversion 0 < VT ≤ VG ΨS ≥ 2φB ns ≥ NA additional inversion layer charge
MOS Capacitor - Useful Equations
MOS capacitor voltage drops (ideal): VG = VOX + ΨS
These equations assume the MOS
Depletion region width: capacitor is in the extrinsic temperature
region (e.g. around room temperature).
2εS 2εS
W= ΨS P-type W= ΨS N-type
qNA qND
Bulk potential:
Ei (bulk ) − EF kBT § NA ·
φ =
B = ln¨ ¸ P-type
q q © ni ¹
Ei (bulk ) − EF kBT § ND ·
φ =
B =− ln¨ ¸ N-type
q q © ni ¹
Definition of strong inversion (threshold): ΨS = 2φB (alternate definition: ΨS = 2φB + 6kBT/q)
Maximum depletion region width (occurs at threshold):
2εS 2εS
WT = (2φB ) P-type WT = (2φB ) N-type
qNA qND
Useful equations for the MOS capacitor.
A Closer Look at the Surface Potential (Ideal)
kBT ª q (ΨS − 2φB ) º
VG = ΨS − γ ΨS + exp « »
q ¬ kBT ¼
2εsqNA γ is called the body

where: γ= P-Type factor - contains all the
C ' OX physical attributes and
constants
2εsqND ε
also note: γ= for N-Type C ' OX =
OX
(gate capacitance
C ' OX t
OX
per unit area)
ΨS
2φB + 6kBT/q
2φB
VG ≈ Ψ S − γ Ψ S
φB VT VT
(our definition) (alternate def.)
0 depletion inversion inversion inversion VG

(weak) (moderate/strong) (strong)
It is desirable to minimize VOX and maximize ΨS , meaning that the gate voltage has maximum influence over the
semiconductor surface. The importance of this will become more obvious when we discuss the MOSFET transistor in the next
module.
Since surface potential can not be measured directly, it is useful to have an expression relating ΨS to the applied gate voltage
VG. This is given above (for a detailed derivation, the reader is referred to Chapter 2 of Operation and Modeling of the MOS
Transistor, Y.P. Tsividis, McGraw-Hill, 1987). The expression is plotted as ΨS vs. VG (although the equation can not be solved
explicitly for ΨS ). For weak inversion, the steeper slope indicates that large changes inΨS are required to accommodate the
gate charge from small changes in VG. In strong inversion, however, only slight changes in ΨS are required, because of the
strong exponential response of the inversion charge to ΨS as discussed previously. (This graph also makes it clear why some
authors prefer that threshold be defined as ΨS = 2φB + 6kBT/q, where the surface potential has saturated somewhat.)
Aside -- Looking Ahead: The weak-inversion slope is very important because it influences MOSFET parametrics. Optimal
MOSFET performance is achieved by maximizing this slope, which corresponds to minimizing the body factor γ. As γ → 0,
VG → ΨS, as if none of the gate voltage dropped across the oxide (VOX = 0). This gives the gate voltage maximum control over
the semiconductor surface, resulting in a sharper on-off transition for the transistor and a lower threshold voltage, which
translates into a higher drive current and hence faster circuits. Minimizing γ in turn means minimizing the gate oxide thickness
tox and the substrate doping NA (this can be seen from the equation for γ above, and is discussed further in the next slides).
*Note on nomenclature: COX is used to represent the oxide capacitance, εOXA/tOX (in Farads). C’OX is used to denote oxide
capacitance per unit area, εOX/tOX (e.g. Farads/µm2). This module and the next one will use these two quantities often.
MOS Capacitor - Surface Potential & Gate Ox Thickness
VG = VOX + ΨS
Thinner Oxide Thicker Oxide

MOS M O S
+VG +VG
ΨS ΨS
0 W y
0 W y
For a thinner gate oxide, there is less voltage drop across the oxide (lower VOX) and hence more voltage drop across the depletion
region in the semiconductor surface (higher ψs). Therefore, the gate voltage has more control over the semiconductor surface, and
strong inversion (threshold) will be achieved at a lower applied gate voltage; i.e. the threshold voltage VT will be lower. As
previously mentioned, a lower threshold voltage is advantageous for a transistor (MOSFET), as it typically means that the
transistor will produce a higher drive current, which in turn allows for faster transistor circuits.
MOS Capacitor - Surface Potential & Doping
Lighter Doping Heavier Doping
MOS MOS
VG = VOX + ΨS
+VG +VG QG = -QD

QD = qANAW
ΨS ΨS
0 W y y
0 W
Lighter doping necessitates a wider depletion region (to uncover enough fixed ions to balance the gate charge). The depletion
region can be thought of as an insulator (i.e. very few mobile charge carriers, very high resistance). VG must drop across the
oxide (VOX) and the depletion region (ΨS). The wider the depletion region, the larger the voltage drop in the semiconductor, i.e.
larger ΨS.
MOS Capacitor (Ideal) - Threshold Voltage Calculation
Threshold Voltage
P-Type MOS Capacitor kBT § p ·

where φ =
B ln¨ ¸
q © ni ¹
2εSqNA 2φB p ≈ NA for extrinsic temperature
VT = 2 φB + region (e.g. room temp.)
C ' OX
ε
C ' OX =
OX (gate capacitance
per unit area)
tOX
N-Type MOS Capacitor

kBT § n ·
where φ = B ln¨ ¸
2εSqND 2φB q © ni ¹
VT = 2 φB − n ≈ ND for extrinsic temperature
C ' OX region (e.g. room temp.)
ε
C ' OX =
per unit area)
t OX
Threshold voltage expressions. Note that the threshold voltage is smaller (in magnitude) for thinner gate oxide and/or lighter
silicon doping, as previously discussed.
Temperature Dependence of VT: The temperature dependence of VT comes from φB. As the temperature increases, φB decreases
due to the fact that p → ni. Recall that the P-type substrate/well will approach intrinsic behavior at higher temperatures, i.e. p → ni
(as discussed in module 1), so φB → 0 (i.e. EF → Ei), so VT → 0. Thus, threshold voltage decreases with increasing temperature.
MOS Capacitor (Ideal) - AC Behavior & The C-V Curve
The C-V Test: A
M
~ O
dQ
S
C=
dV
VG
P-type
VG slow dc ramp VG slow dc ramp

low-frequency high- frequency
ac signal ac signal
time time
0 0
Low-Frequency Test High-Frequency Test
Capacitance is a measure of how effectively a capacitor handles charge. In dc terms, it is the proportionality constant between the
voltage applied across the capacitor and the amount of charge stored, Q = C V (i.e. a device with a higher capacitance stores more
charge for a given applied voltage). For ac voltage signals, it is better thought of as a measure of how the charge on the capacitor
changes in response to changes in the applied voltage, C = dQ/dV (a device with a high capacitance exhibits a large change in Q
for a small change in V, and thus is very responsive to changes in the applied voltage).
The capacitance-voltage characteristic of the capacitor is measured using the C-V test described here. A small-amplitude ac signal
is superimposed on a slow dc ramp of the gate voltage. The transient currents in the circuit are measured, and used to calculate the
charge (i = dQ/dt), which is then used to calculate the capacitance as a function of the applied voltage VG.
We will consider two cases, a low-frequency ac signal vs. a high-frequency signal. We will see that the frequency of the signal
does not affect the C-V of the device in accumulation or depletion, but has a pronounced effect on its inversion behavior.
Aside – Technical Note: The slow dc ramp makes this a “quasi-static” test, allowing the device to maintain thermal equilibrium as
it is being tested. The idea here is to increment the dc gate voltage a small amount, then use the ac signal and measure the transient
currents to calculate the capacitance, then increment again to the next dc gate voltage point. Repeating this over the dc voltage
range of interest, with slow and gradual increases in the dc voltage, generates the “quasi-static” C-V curve.)
MOS Capacitor (Ideal) - The C-V Characteristic
equivalent +Q G
circuit VOX, COX t OX
+ ε A -QG
COX =
OX
VA t
OX
+Q S
C P-Type Si - ΨS, CS W
εA
CS =
S
-QS
εOXA W
C ≈ COX = εOXA
tOX C ≈ COX =
tOX low frequency
COXCS COX
C= =
Accumulation COX +CS 1 + εOXW
εStOX COX
COX
Depletion
COX COXCS COX

C= =
CS
COX +CS 1 + εOXWT COX
Inversion εStOX
CS(min)
high frequency
0 VT VG
The Key to Understanding the C-V Behavior: Majority Carriers Respond Fast, Minority Carriers Respond Slow!
Majority carrier relaxation time (aka. dielectric relaxation time): How quickly the majority carriers can respond to a non-equilibrium condition and restore equilibrium,
typically 10-10 - 10-13 sec. For example, if we moved all the holes in a P-type semiconductor to one side of the substrate, the time it takes for them to redistribute to an
equilibrium condition is the relaxation time.
Minority carrier lifetime (ττ): As discussed in module 1, this is the mean time that minority carriers will exist before recombining, typically on the order of 0.01 to 0.1 sec
(note: orders of magnitude slower than the majority carrier relaxation time!). Since the recombination rate equals the generation rate at thermal equilibrium, this is also the
mean time between generation events. Essentially, it is the time associated with R-G of minority carriers.
Qualitative Description of the C-V Characteristic
Accumulation: A change in gate charge is compensated by adding/removing holes at the semiconductor surface. This is similar to an ordinary parallel-plate capacitor, with
charge fluctuating on either side of the oxide dielectric layer. Thus it has a capacitance COX = εOXA/tOX . This is true at both low and high frequencies, because the charge
compensation is performed by the movement of holes (majority carriers), and their response (relaxation) time is more than sufficient to keep up with the fluctuations even if
they are very rapid.
Depletion: A change in gate charge is compensated by a change in the width (depth) of the depletion region. In other words, an increase in gate charge causes holes to retreat
from the edge of the depletion region, thus uncovering more B- depletion charge. A reduction in gate charge causes holes to encroach into the edge of the depletion region, re-
covering some B- charge. Hence, the depletion region fluctuates about its dc value (W) in response to the applied ac signal. This is analogous to a fluctuating charge on the
two sides of a double-layer insulator, i.e. COX and CS in series*. As VG → VT, W → WT (max. value) so CS declines to its minimum value and so does the overall capacitance C.
This is true at both low and high frequencies, because the charge compensation is performed by the movement of holes (majority carriers), and their response (relaxation) time
is more than sufficient to keep up with the fluctuations even if they are very rapid.
Inversion. Low Frequency (f < 100 Hz): Changes in gate charge are compensated by changes in inversion charge. These changes in inversion charge come about via R-G.
In other words, as the gate charge increases, thermal generation increases near the surface of the depletion region to supply more electrons to the inversion layer. As the gate
charge decreases, recombination increases to reduce the inversion charge. Because the frequency is low, R-G can keep up. Once again, charge is fluctuating on either side of
the gate oxide, i.e. like an ordinary parallel-plate capacitor with a capacitance COX = εOXA/tOX . High Frequency: The relatively slow R-G process is not able to
supply/eliminate minority carriers fast enough to provide inversion-charge compensation for the ac signal. The number of carriers in the inversion layer remains fixed, and
changes in gate charge are balanced by the much faster majority carrier response instead – i.e. the depletion region fluctuating about its dc value WT as holes move at the edge
of the depletion region. Per the discussion above, this is like having COX and CS in series, but W = WT (max. value) so CS is at a constant, minimum value.
* The depletion region can be treated like an insulator/dielectric since it contains (almost) no mobile charge carriers and hence is very non-conductive, like an insulator. If we make the simplifying
assumption that all of the B- depletion charge is located in a sheet at the edge of the depletion region, we can treat the depletion region like a parallel-plate capacitor with a dielectric of thickness W
and hence a capacitance of CS = εSA/W. (This is the same approach we took in module 2 to calculate the capacitance of a PN junction. This simple parallel-plate model is only a rough
approximation of the capacitance; more sophisticated models do exist and take into account the actual charge distribution in the depletion region as well as fringing capacitance, etc.)
MOS Capacitor - Qualitative Description of the C-V (cont.)
(a) M O S (b)
accumulation depletion
∆QG
+Qp
+QG W
-QG ∆QP
-QD
∆QD
∆QG
COX
COX
CS
(d)
(c)
∆QG ∆QG inversion
inversion
(high-frequency)
(low-frequency)
+QG
+QG
WT WT
-QD -QD
-Q ∆QD
∆Qn n -Qn
CS(min)
COX
COX
This diagram shows the charge fluctuations in response to the applied ac signal, to reinforce the concepts discussed in the
previous slide.
Diagram (a) shows how the charge is modulated in response to the applied ac voltage when the MOS capacitor is dc biased into
accumulation. Changes in the gate charge (∆QG) are compensated by changes in the accumulation charge (∆QP) at the
semiconductor surface. The device behaves like a common parallel-plate capacitor. The holes (majority carriers) can move fast
enough to keep up with even a high-frequency ac signal.
Diagram (b) shows how charge is modulated when the MOS capacitor is dc biased into depletion. Fluctuations in gate charge are
compensated by the depletion region fluctuating about its dc width (i.e. holes cover/uncover B- depletion charge as needed). The
device behaves like two parallel-plate capacitors in series, with the gate oxide as one dielectric region and the depletion region as
the other. Again, it is holes (majority carriers) which move in response to the gate charge fluctuations, and they are fast enough to
keep up with even a high-frequency signal.
Diagram (c) shows how charge is balanced when the MOS capacitor is dc biased into inversion and the applied ac voltage is at a
low frequency. Changes in gate charge are compensated by changes in the inversion charge (via R-G of minority carriers). The
minority carrier R-G response is slow (compared to the majority carrier response), but if the ac signal is slow enough the device
will balance charge via this mechanism. This gives rise to charge fluctuating on either side of the gate oxide, like an ordinary
parallel-plate capacitor.
Diagram (d) shows the capacitor dc biased into inversion, but with a high-frequency ac signal. Fluctuation in gate charge is
compensated not by inversion charge (the minority carrier response is much too slow) but rather by the depletion region
fluctuating about its dc value (i.e. by majority carrier movement near the edge of the depletion region). The device once again
behaves like two parallel-plate capacitors in series. However, we know that the depletion region is at its maximum width (WT) in
inversion (VG ≥ VT), and is therefore at its minimum capacitance (CS = εSA/WT). The capacitance of the gate oxide is constant
(COX = εOXA/tOX), and these two capacitances combine to yield a minimum, constant capacitance for the device, as shown on the
C-V curve.
Real MOS Capacitor - Band Diagram, Isolated Materials
For a real (non-ideal) MOS capacitor, φM < φS
M O S
EVAC
EC
qφM
qφS
EG(SiO2) ≈ 9 eV
EFM EC
EG(Si) = 1.1eV
Ei
(aluminum)
EFS
EV
EV
Let us consider a real (non-ideal) MOS capacitor, where the work functions are not equal.
We will consider an aluminum gate for example, as historically this is the most common choice (we will consider poly-Si gates in
the next module).
For an aluminum gate over a silicon substrate, φM < φS. This is generally true regardless of whether P-type or N-type silicon is
used as the substrate. The value of φS depends on the position of the Fermi level EFS, which of course depends on the doping (type
and concentration). We will continue to use P-type silicon for illustration; the N-type MOS capacitor will be summarized at the
end.
Real MOS Capacitor - Band Diagram, Equilibrium
+ + + + + + +
equilibrium
W Vbi
B- B- B- B- B- B- B- (no applied voltage)
ΦMS ≡ φM - φS
P-type
Vbi Vbi = - ΦMS (built-in voltage)
source: Solid State Electronic Devices,

B.G. Streetman, Prentice Hall, 1990.
EC
EG(Si)
Ei
ΨS = ΦMS
qφB
EFM EFS
EV
M O S
W
(aluminum)
Because φM < φS, the bands bend as shown above when the Fermi levels align* at equilibrium (no applied voltage).
The quantity ΦMS (≡ φM - φS) is the work function mismatch. Because φM < φS for an aluminum gate over silicon, ΦMS is a negative
number. This is generally true for both N-type and P-type Si, as shown on the graph above (ΦMS vs. doping concentration).
As indicated by the band bending, the device has a built-in voltage Vbi equal to -ΦMS. The device is in depletion at equilibrium as
depicted on the band diagram (i.e. ΨS = ΦMS).
* Electrons can not flow through the oxide (an insulator) to facilitate this equilibration. So to visualize how this works, imagine connecting a wire between
the gate and substrate while they are isolated, and then assembling the MOS structure. Electrons will flow through the wire and the band diagrams will slide
vertically wrt. one another until the Fermi levels have aligned (equilibrium). In practice, if electrical contact is made to the MOS capacitor, there is always
some “back door” path like this by which equilibration can take place (e.g. through a power supply or battery).
Real MOS Capacitor - Band Diagram, Flatband
VFB = -Vbi = ΦMS
M Vbi VFB
O
- S
VFB VFB VG = VOX + ΨS + VFB
+
P-type Vbi VFB = Flatband Voltage
for an ideal MOS Capacitor, VFB = 0
for an Al gate on Si, VFB < 0
EC
Ei
EFM VFB
EFS
EV
(aluminum)
A voltage can be applied to the gate to compensate for the work function mismatch and “flatten” the bands; this voltage is called
the flatband voltage, VFB. Applying a negative gate voltage VFB = -Vbi (= ΦMS) will attract holes to the semiconductor surface
and reduce the depletion region to zero (W = 0, ΨS = 0), shifting the band diagram to the flat-band condition as shown above
(zero net voltage across the capacitor).
Real MOS Capacitor - Oxide Charge

If there is a non-negligible amount of oxide charge, the flatband voltage becomes:

Qi
VFB = ΦMS − Flatband voltage w/ Qi = effective net oxide charge
oxide charge included COX = oxide capacitance = εOXA/tOX
COX ΦMS < 0 for Al gate over Si
Another non-ideality is the presence of charge in the gate oxide.
There are four general categories of oxide charge:

• Mobile ionic charge: due to contaminants (e.g. Na+, K+, Li+), usually from the processing environment
• Oxide trapped charge: from plasma processing, or hot electron injection (in a transistor)
• Fixed oxide charge: due to unoxidized Si within ~20 Å of the Si-SiO2 interface
• Interface states (traps): due to dangling/incomplete bonds at the Si-SiO2 interface
These charges contribute to band-bending at equilibrium, and are taken into account in the flatband voltage. Historically, these
charges (particularly the mobile ionic charge) inhibited the development of high-quality MOS devices because they were not well
understood and were difficult to control. Modern manufacturing processes minimize the amount of oxide charge, enabling the
mass production of high-quality, high-performance MOS devices.
Note that, for ΦMS < 0, positive oxide charge (Qi > 0) will push the P-type semiconductor surface further into depletion (i.e. will
require more B- charge under the gate to compensate the positive charges in the oxide). Negative oxide charge will work against
ΦMS, reducing the degree of depletion. Qi is almost always positive, for both P-type and N-type substrates (wells).
Real MOS Capacitor - Surface Potential Revisited
Adding the flatband voltage into the previous (ideal) relationship:
VG = VFB + VOX + ΨS
kBT ª q (ΨS − 2φB ) º

VG = VFB + ΨS − γ ΨS + exp « »
q ¬ kBT ¼
2εsqNA
recall: γ= P-Type
C ' OX ε
C ' OX =
OX
where:
t
OX
2εsqND
or: γ= N-Type
C ' OX
The flatband voltage, which accounts for the work function mismatch and any oxide charge, is added into our previous derivation
of the relationship between the applied gate voltage and the surface potential.
MOS Capacitor – Threshold Voltage Revisited
Threshold Voltage
kBT § p ·
P-Type MOS Capacitor
where φ =
B ln¨ ¸
q © ni ¹
VT = VFB + 2 φB + region (e.g. room temp.)
C ' OX ε
C ' OX =
per unit area)
(VFB < 0 for Al gate on Si → Increases P-type VT in magnitude) tOX
N-Type MOS Capacitor

kBT § n ·
where φ = B ln¨ ¸
2εSqND 2φB q © ni ¹
VT = VFB − 2 φB − n ≈ ND for extrinsic temperature
ε
(VFB < 0 for Al gate on Si → Decreases N-type VT in magnitude)
C ' OX =
per unit area)
t OX
The flatband voltage must also be added to the ideal threshold voltage calculation.
Note from the foregoing discussion that, for an aluminum gate over P-type silicon (and reasonably low amounts of oxide charge)
the flatband voltage is negative (i.e. negative potential on gate relative to substrate) and hence reduces the threshold voltage for a
P-type MOS capacitor per the equation shown above. This makes sense: the capacitor is biased slightly into depletion at
equilibrium, thus strong inversion (threshold) will be achieved at a lower applied voltage.
(VFB is generally negative for an aluminum gate over N-type silicon as well, and will serve to increase VT in magnitude in that
case.)
Real MOS Capacitor - C-V Characteristic Revisited
C P-Type Si
VFB
ε A
OX
t
OX low frequency
Accumulation ideal
real Depletion
Inversion
high frequency
0 VT VT(ideal)
VG
The MOS capacitor is slightly in depletion at equilibrium, and hence the whole C-V curve is shifted to the left by an amount equal
to the flatband voltage.
As previously noted, the threshold voltage of a P-type MOS capacitor will be reduced (vs. the ideal case), because the capacitor is
already biased into depletion at equilibrium.
MOS Capacitor - N-Type Si at a Glance
VG = 0 VG < 0, |VG| < |VT| VG < 0, |VG| = |VT|
- - - - - -------------
P+ P+ P+ P+ P+ W o o o o o o oo
WT
N-Type N-Type N-Type
Equilibrium (ideal) Depletion Strong Inversion

(Threshold)
VG > 0 VG < 0, |VG| → |VT|
+ + + + + + + + - - - - - - - - -
•••••••• o o o o
W
N-Type N-Type
Accumulation Inversion
This is a summery of an (ideal) N-type MOS capacitor. It is analogous to P-type (note that the voltage polarities are reversed).
MOS Capacitor - N-Type Si at a Glance (cont.)
Depletion VG = VOX + ΨS
VG < 0, |VG| < |VT| ΨS < 2ϕB
W
Equilibrium (Ideal)
VG = 0
EFM •••••••••• EC
EFS
- ϕB
Ei +
M O S (N-Type)
EV
o
EC
EFM
EFS
Ei
VG = VOX + ΨS
EV Inversion
ΨS → 2ϕB
VG < 0, |VG| → |VT|
W ps → ND
EFM •••••••••• EC
EFS
Accumulation - ϕB
Ei +
VG > 0
o
o EV
o
••• •••••••••• EC
EFS
EFM
+ Ei -
Strong Inversion (Threshold)
EV
VG < 0, |VG| = |VT|
VG = VOX + ΨS
ΨS = 2ϕB
WT
ps = ND
EFM
ΨS •••••••••• EC
- ϕB
EFS
Ei
+
o
oo
oo
o EV
o
This is a summary of the band diagrams for an (ideal) N-type MOS capacitor. It is analogous to P-type.
Also note that the equations provided in this module are written for both N-type and P-type MOS capacitors.
MOS Capacitor - N-Type Si at a Glance (cont.)
N-Type Si
C
ε A
OX
low frequency tOX
Accumulation
Depletion
Inversion
high frequency
VT 0 VG
The C-V curve for an (ideal) N-type MOS capacitor.
For a real (non-ideal) aluminum-gate N-type MOS capacitor, ΦMS < 0 and hence VFB < 0. The C-V curve shown above will be
shifted to the left by an amount VFB (i.e. the device is in accumulation at equilibrium, and VT is increased in magnitude).
4
The
MOSFET
4-1
Introduction to Semiconductor Device Physics / MOSFET / rev 4.3 Tom Cunningham
This is the fourth module in a five-module introduction to semiconductor devices. The modules are:
2. The PN Junction
4. The MOSFET
5. Small Circuits
The transistor is the heart of modern electronic devices, allowing integrated circuits to perform logic functions and store information (memory). In this
module, we will combine the concepts of the previous three modules to understand how transistors work.

• Show that the MOSFET consists of two PN junctions (source and drain) separated by a MOS capacitor (gate)
• Identify the various layers and features of the MOSFET
• Understand the similarities and differences of N-channel vs. P-channel MOSFETs
• Understand MOSFET operation as a voltage-controlled switch
• Understand the different biasing regimes of the MOSFET – subthreshold, linear, saturation
• Understand the band diagram of the MOSFET in these biasing regimes
• Understand the I-V curve of a MOSFET
• Understand how the channel length and gate oxide thickness affect the performance of the transistor
• Understand how circuit speed is related to transistor drive current and RC delay
• Understand some short-channel effects and challenges associated with shrinking transistor dimensions
Looking Back: We are prepared to study the MOSFET because we understand the physics of the PN junction and the MOS capacitor from the previous
modules.
Looking Ahead: At the end of this module we will understand how transistors work. In the next module, we will combine transistors together to build some
basic logic and memory circuits.
4-2
MOSFET - Layer/Feature ID
Metal-Oxide-Semiconductor Field-Effect Transistor
Top & Cross-Section View Source-to-Drain
(Layered) Cross-Section
Source Gate Drain metal lines

• • •
contact / via
Source Gate Drain
interlayer
• • •
dielectric
(ILD)
N+
poly-Si gate
gate oxide N+ N+
source / drain P
regions
isolation Source: Gate: Drain:

PN Junction MOS Capacitor PN Junction
substrate / well (Diode) (Diode)
4-3
MOSFET stands for Metal-Oxide-Semiconductor Field-Effect Transistor.
The MOSFET consists of a source, gate, and drain. Current flows from the source to the drain under the influence of the gate voltage. (Note that the
MOSFET structure is symmetrical; i.e. which end is the “source” and which is the “drain” is determined by the applied voltages, which will be discussed
shortly. The side that carriers flow out of is called the source, and the side they flow into is the drain.)
The source and drain regions in the semiconductor are PN junctions. The gate region is a MOS capacitor. We will combine our knowledge of these to
understand the physics of the MOSFET.
Other features of the structure include the metal lines (typically aluminum or copper), which carry signals among transistors to form the circuit, and the
interlayer dielectric or ILD (typically SiO2) which isolates the metal lines from one another and from the silicon substrate. In modern integrated circuits there
are typically several layers of metal, separated by layers of ILD for isolation, and vertical connections are made between metal layers by vias (typically
tungsten or copper). Also note the isolation oxide, which electrically isolates neighboring transistors.
In our discussion of the MOS capacitor, we used a metal gate. Early MOSFETs were fabricated with aluminum gates, however, modern transistors use a
heavily (degenerately) doped poly-silicon* gate. The poly-Si gate has certain processing advantages (e.g. can withstand higher processing temperatures than
aluminum and has certain patterning advantages). The poly-Si gate is doped simultaneously with the source and drain regions in a self-aligned gate process,
which helps to optimize the alignment of the gate to the source/drain regions. More on poly-Si gates later.
* The term “poly-silicon” is short for “poly-crystalline silicon”. Poly-Si does not have a perfect crystal structure like single-crystal silicon. On a molecular
level, poly-Si consists of “grains” - within a grain the silicon has the single-crystal structure, but the crystal orientation is not preserved across grain
boundaries.
Note: Enhancement-mode (“normally off”) MOSFETs are discussed here, as they are the predominant choice for modern IC production. Depletion-mode
(“normally on”) transistors are not discussed.
4-4
MOSFET - Two Types
source gate drain

source gate drain
• • • • • •
N+ P+
device
structure N+ N+ P+ P+
P N
N-Channel Transistor P-Channel Transistor
gate
gate
circuit
symbol source drain source drain
4-5
There are two types of MOSFET, N-channel and P-channel (the term “channel” will be explained shortly). The device structure is
the same, only the doping differs, as shown.
4-6
Part 1 – Large Geometry MOSFET
4-7
We will divide our study of the MOSFET into two parts. First, we will study the large-geometry MOSFET. In Part 2, we will
extend this study to small-geometry (short-channel) MOSFETs.
4-8
The Basics - Turning the MOSFET On & Off
source gate drain

• • •
MOSFET at Equilibrium
(no applied voltages)
N+ N+
depletion
P region
•
backside/well
4-9
The MOSFET is actually a four-terminal device, when the backside contact is considered (this may also be referred to as the body,
substrate, tub, or well contact or “tap”).
We will use the N-channel MOSFET for example. The operation of the P-channel transistor is analogous, and will be summarized
later.
The N-channel transistor is shown here at equilibrium, i.e. no applied voltages. Note the depletion regions formed by the source
and drain PN junctions. If the width of these depletion regions is negligibly small relative to the gate length and width, the
transistor is considered a large-geometry MOSFET. We will study the physics of large-geometry MOSFETs first, and then extend
this to small-geometry MOSFETs in Part 2.
The MOSFET behaves like a microscopic electrical switch in digital applications, and we will start by understanding how to turn it
on and off. (In analog applications the MOSFET behaves like a microscopic amplifier. The focus of this course is digital
applications, but the concepts can be applied to analog applications as well.)
4 - 10
The Basics - Turning the MOSFET On & Off (cont.)
VGS = 0 +VDS
• •
No Applied Gate Voltage reverse-biased PN junction:

MOSFET is “OFF” depletion region widens,
N+ N+ only leakage current
VGS < VT +VDS

• •
Subthreshold
MOSFET is “OFF”
N+ N+
MOS capacitor is
biased into depletion,
P only leakage current
4 - 11
For normal operation, the source and backside are grounded, and a positive drain-to-source voltage VDS is applied. With VGS = 0
(the gate-to-source voltage), the device is considered to be OFF. Note that the source PN junction is zero-biased and the drain PN
junction is reverse biased, so there is only a small leakage current in the device.
For VGS << VT, the MOS capacitor is biased in depletion. As VGS approaches VT surface inversion begins, but is not sufficient to
turn the device on (see next page). The transistor is still considered to be OFF (only a tiny drain current due to junction leakage and
subthreshold current). Note that the voltage under the gate increases from source to drain due to the presence of VDS, hence so does
the depletion layer width W.
4 - 12
The Basics - Turning the MOSFET On & Off (cont.)
VGS ≥ VT +VDS
ID •
ID •
At or Beyond Threshold
MOSFET is “ON”
•••••••••••••••••
N+ N+
Note: The depth of the channel is exaggerated for

illustration purposes in this diagram. It is actually more
like a “sheet” of charge right under the gate oxide.
4 - 13
When VGS = VT (threshold voltage), strong inversion occurs in the MOS capacitor, forming an inversion layer or channel of
electrons underneath the gate oxide. This channel shorts the source and drain regions, forming a conductive path. Once this
channel is formed, electrons flow from source to drain under the influence of VDS, giving rise to the drain current ID. The transistor
is ON.
The MOSFET behaves like a microscopic, voltage-controlled switch. The gate voltage determines whether the switch is open (no
current) or closed (current).
Note that the channel is formed by the gate voltage (vertical electric field). This is where the term Field Effect Transistor (FET)
comes from.
* In the diagram above, the drain current ID is shown flowing in the direction of conventional current. Conventional current, by
definition, flows from the positive terminal to the negative terminal (in this case, ground) and hence is always opposite to the
direction of electron flow. As noted in module 1, the slides in this course show currents in the direction of conventional current
flow unless otherwise specified.
4 - 14
MOSFET - I-V Characteristic
ramp VDS
constant VGS > VT
ID
•
•
For a constant gate voltage
(above threshold), ramp VDS
and measure ID.
•••••••••••••••••
N+ N+
ID
constant VGS
ID(SAT)
Saturation
Linear
0 VDS(SAT) VDS
4 - 15
The graph above is the DC current-voltage (I-V) characteristic of the MOSFET. It shows the drain current vs. source-to-drain
voltage for a constant gate voltage. For VDS < VDS(SAT), ID increases linearly with VDS (ohmic behavior). Near VDS(SAT), the
current begins to saturate. Beyond VDS(SAT), the current is constant (saturated) and does not increase with VDS. VDS(SAT) is called
the saturation voltage. ID(SAT) is the saturation current, aka. drive current.
We will discuss the physics behind this I-V characteristic in detail.
4 - 16
MOSFET - Band Diagram
Equilibrium Applied Drain Voltage
source gate drain VGS = 0 +VDS

• • • • •
N+ N+ N+ N+
P P
•
backside/well
reverse
biased
drain
•••••••••••••• qVbi
•••••••••••••• qVbi •••••••••••••• EC
EC
EF ••••••••••••••
EF
qVDS
oooooooooooooooo
oooooooooooooooooo
EV
EV
W
W W
W
4 - 17
The source and drain regions form two back-to-back PN junctions, hence the band diagrams shown here. (These should look
familiar - see the exercise at the end of the PN Junction module.)
4 - 18
MOSFET - Subthreshold
VGS small VDS
0 → VT
+ • ID • +
Gate MOS capacitor is

biased into depletion N+ e- N+
leakage
•••••••••••••• q(Vbi-ΨS)
EC
EF ••••••••••••••
ooooooooooooooo
EV
W from previous band

W diagram, for reference
4 - 19
The source barrier height is reduced a small amount by the surface potential (ΨS), slightly forward biasing the source diode. There
is not enough gate voltage to produce a good channel (VGS < VT), but some electrons are present in the region underneath the gate,
and a small amount of subthreshold current (aka. leakage current) does flow from source to drain under the influence of VDS.
Increasing VGS increases ΨS, further reducing the barrier height and increasing the subthreshold drain current IDS.
The transistor is still considered OFF (but leaky) in this subthreshold regime. The threshold voltage VT represents the OFF-to-ON
transition point in gate voltage.
Subthreshold leakage current is undesirable in a MOSFET – it leads to increased static power consumption and may contribute to
other non-idealities such as noise or latchup. A well-designed transistor will have low leakage and an abrupt turn-on transition at
VT.
Remember that the subthreshold characteristics of the MOSFET are dominated by the source diode.
4 - 20
MOSFET - Subthreshold (cont.)
+VGS µeff +VDS

• •
N+ • N+
electron
effective/surface mobility illustrated
dVGS dVGS
Subthreshold Swing: S= = ln(10)
d (log 10 ID ) d (ln ID )
kBT ª CD º
S≈ ln(10) «1 + »
q ¬ COX ¼
4 - 21
This graph shows the drain current vs. applied gate voltage (with some nominal drain voltage applied). Ramping the gate voltage
causes a progressively stronger channel to form underneath the gate, and the drain current increases exponentially (notice the log
scale).
Observe, however, that the trend begins to flatten out at higher gate voltage. Although more electrons are being pulled into the
channel, the effective mobility (aka. surface mobility) decreases, and the drain current begins to level off. Effective/surface
mobility, µeff, is generally lower than the mobility in the semiconductor bulk. Surface mobility is depicted in the diagram above –
the carrier undergoes scattering events with the oxide interface due to the presence of the vertical electric field (gate voltage) as it
traverses the channel. As the gate voltage is increased, more scattering takes place, and the effective/surface mobility is reduced.
The gate swing voltage (aka. subthreshold swing), S, is an important parameter for understanding the OFF-to-ON transition of a
transistor. It is the change in gate voltage required to cause a decade (power of ten) increase in the drain current. In the case
shown here, S = 50 mV.
A small swing voltage is desirable. As S → 0, the transistor approaches the behavior of an ideal switch, which turns on abruptly in
a “step function” manner. As S increases, a “softer” (more gradual) turn-on is observed. As S → ∞, it becomes impossible to turn
the transistor on and off at all.
Note that the swing voltage is sensitive to the ratio CD/COX. Since CD = εsA/W and COX = εOXA/tOX, the swing voltage is sensitive
to the ratio tOX / W – i.e. the relative thickness of the gate oxide and the depletion region. Recalling our discussion of the MOS
capacitor, the gate voltage drops across the oxide and the depletion region (VGS = VOX + ψS). For the gate voltage to have
maximum influence over the semiconductor surface, we desire minimum voltage drop across the oxide and maximum voltage drop
in the semiconductor (depletion region). As previously discussed, the way to accomplish is to: (1) reduce tOX by using a thinner
gate oxide; and/or (2) increase W by reducing the dopant concentration NA underneath the gate. These result in a lower body factor
γ (i.e. ΨS increases steeply with VG), a lower subthreshold swing (S) (i.e. ID increases steeply with VG), and a lower threshold
voltage VT (i.e. a strong channel is present at a lower VG) – all this sums up to a better transistor.
4 - 22
MOSFET - Linear Regime
VGS ≥ VT VDS < VDS(SAT)

+ • ID • +
N+ N+
•••••••••••••• ID
EC
EF ••••••••••••••
N-type channel, behaves
like a resistor (ohmic)
EV
oooo
oooo
oooo from previous band
ooo
hole current diagram, for reference
negligible
4 - 23
When the gate voltage exceeds the threshold voltage (VGS ≥ VT), the transistor turns ON. The source barrier height is reduced to
near zero by the surface potential (ΨS), and the source diode is strongly forward biased. Electrons flow out of the source (diffusion
current) forming the channel. Electrons flow to the drain under the influence of VDS.
Increasing VGS (for a constant VDS) increases ΨS, sucking more electrons into the channel from the source, hence increasing the
drain current ID. As discussed previously, there is a limit to this: although the channel carrier concentration increases, the
effective/surface mobility decreases.
Increasing VDS (for constant VGS) increases the source-to-drain potential, linearly increasing ID - the transistor is in the linear region
of operation and the ID-VDS characteristic is ohmic. The channel is behaving like a simple resistor (as indicated by the band
diagram).
Remember that the behavior of the MOSFET in the linear regime is dominated by the Gate (MOS) capacitor.
Question: This band diagram is taken at a cross-section just under the gate oxide (through the channel). What does the band
diagram look like deeper into the substrate, e.g. through a cross-section near the bottom of the source/drain regions, out in the P-
type bulk, etc? (See next slide ...)
Inversion Charge - MOS Capacitor vs. MOSFET: In our discussion of the MOS capacitor, the inversion charge came from
minority carrier generation near the semiconductor surface. In the MOSFET, however, the inversion charge comes mainly from
the source via source barrier lowering (i.e. forward biasing the source junction). Electrons diffuse from the source into the region
under the gate to form the channel. Therefore, the MOSFET has a much better supply of electrons for the inversion layer (channel)
than the MOS capacitor. In other words, the inversion layer in the MOS capacitor is electrically isolated from the outside world –
thermal generation is its only source of electrons. The MOSFET inversion layer (channel) is electrically connected to the outside
world (power supply) through the source and drain. More on this later.
4 - 24
MOSFET - 3-D Band Diagram

4 - 25
These are 3-D band diagrams for the MOSFET. They show the combined influence of the gate and drain voltages, and at various
depths into the substrate.
Diagram (a) shows the orientation of the structure, with the gate facing out of the page. Diagram (b) shows the bands at
equilibrium. Diagram (c) shows an applied gate voltage but no drain voltage. Diagram (d) shows applied gate and drain voltages.
By observing the energy gradients on these diagrams, it is easy to see how electrons will “roll downhill” to the gate region (channel
formation, under the influence of VGS) and then “roll downhill” from source to drain (conduction, under the influence of VDS).
4 - 26
MOSFET - Linear Into Saturation
VDS → VDS(SAT) VDS = VDS(SAT)
ID → ID(SAT) ID = ID(SAT)
VGS ≥ VT VGS ≥ VT
+ • •
+ +• • +
N+ N+ N+ N+
P P
At VDS = VDS(SAT), the

channel is pinched off
at the drain edge
EC •••••••••••••• ID EC ••••••••••••••
ID(SAT)
EF EF
••••••••••••••
••••••••••••••
EV EV
4 - 27
Increasing VDS widens the depletion region at the drain end of the channel. The depletion region encroaches on the channel near
the drain, starting to “pinch off” the channel. At VDS = VDS(SAT), the channel is pinched off at the drain edge.
4 - 28
MOSFET - Saturation
VDS > VDS(SAT)
ID = ID(SAT)
VGS ≥ VT
+ • +• VDS(SAT) ≈ VGS - VT
∆L
N+ N+
No longer behaving like a simple

•••••••••••••• resistor. Now looks like a depletion
EC ID(SAT) region being fed by the channel.
EF
EV
••••••••••••••
4 - 29
For VDS > VDS(SAT), the pinch-off point pulls back from the drain. ∆L = 0 at VDS = VDS(SAT). As VDS is increased beyond
VDS(SAT), ∆L becomes larger.
VGS -VT is a useful approximation of the saturation voltage, VDS(SAT). At the source end of the channel, the whole gate voltage is
effective in inverting the surface (because the source is grounded, hence the voltage drop at the source end of the channel is always
simply VGS). At the drain end of the channel, however, only the difference between the gate and drain voltages is effective (VGS –
VDS). When the drain voltage equals VGS – VT, it follows that the voltage drop across the drain end of the channel is just VT, and
hence the channel (inversion) charge falls to zero at the drain end – i.e. pinch-off occurs and saturation begins. In other words,
when VDS ≥ VGS – VT , then VGD ≤ VT (VGD is the gate-to-drain voltage), and the channel is pinched off at the drain end.
Note that the subgate region is no longer behaving like a simple resistor. It now looks more like a reverse-biased junction being
fed by the channel. The next slide will explain this in more detail.
4 - 30
MOSFET - Saturation (cont.)
electrons VDS > VDS(SAT)
I0 ID(SAT) + •
(minority carriers)
electron
• ••••••••••
••••••••
channel •••••••
P • N+ ∆L N+ drain
•
W
- + P substrate/
well
Reverse-Biased VA
PN Junction Diode MOSFET in
P Saturation
ID
I constant VGS
ID(SAT)
Saturation
Linear
0
VA
I0

(Off / Leakage) (On) 0 VDS(SAT) VDS
4 - 31
Why does the drain current saturate?
A parallel exists between the reverse saturation current (I0) of a PN junction diode and the saturation current of a MOSFET. In
both cases, the current is constant with respect to applied voltage because the current through the depletion region is supply limited.
In the case of a reverse-biased PN junction, the carriers are supplied by minority carrier generation in the quasi-neutral region.
These carriers are swept across the depletion region by the applied voltage (VA). The current (I0) is very small because there are
few carriers available. Increasing VA does not increase the supply of carriers (only their kinetic energy as they traverse the
depletion region), therefore I0 is supply limited and constant wrt. VA.
For the MOSFET in saturation, the carriers are supplied by the channel (inversion layer). The electrons in the channel get swept
across the depletion region (∆L) by the applied drain voltage (VDS). Increasing VDS does not increase the supply of carriers (only
their kinetic energy as they traverse the depletion region), therefore ID(SAT) is supply limited and constant wrt. VDS.
The key difference is that the channel is a much better supplier of carriers than the minority carrier generation in a PN junction
diode, so ID(SAT) is a much larger current (~mA) than I0 (~pA).
Remember that the behavior of the MOSFET in saturation is dominated by the drain diode.
4 - 32
MOSFET - Saturation Analogy
Linear
ID
water in
water out
channel
source
drain
ID(SAT)
water in
Saturation
channel
source water out
drain
4 - 33
An analogy to illustrate saturation.
The top drawing shows a canal which is analogous to the MOSFET in its linear regime. The water droplets represent electrons and
the water current represents the the flow of electrons. The height of the hill represents VDS. By lowering the drain end (i.e.
increasing VDS) the hill becomes steeper and the current increases.
The bottom drawing depicts saturation. The drain becomes discontinuous with the channel (representing the pinch-off and pull-
back of the channel). There is a waterfall at the drain edge (analogous to the reverse-biased drain junction). Lowering the drain
end represents making VDS > VDS(SAT). The current is supply limited, and lowering the drain end does not increase the current
flow.
Note that in either case, increasing the gate voltage is analogous to making the water deeper – it will increase the current.
4 - 34
MOSFET - I-V Characteristic, Revisited
VDS(SAT) = VGS - VT
ID
VGS = +3 V
Saturation
Linear
VGS = +2 V
VGS = +1 V
0 VDS
aside
4 - 35
The I-V characteristic is shown for several gate voltages. Note that the drain current increases with increasing gate voltage, as
expected, but the basic shape of the ID-VDS curve remains the same.
Aside: Note that the plot has been extended to show VDS < 0. In this case, the drain junction becomes forward-biased and starts to
behave like a diode. The typical diode I-V characteristic is observed for VGS = 0 (gate grounded). For VGS > 0 the gate voltage
increases the magnitude of the drain forward-bias somewhat (try to visualize this on the band diagram), giving rise to the curves
shown to the right of the true diode curve. The MOSFET is not usually operated this way -- normal operation requires that the
drain be reverse-biased per the forgoing discussion. This is mentioned as an aside for completeness, because it is possible for some
transistors (particularly in analog circuits) to enter this region of operation under certain conditions.
4 - 36
MOSFET - Useful Equations
Threshold Voltage
kBT § p ·
N-Channel MOSFET
where φ =
B ln¨ ¸
q © ni ¹
VT = VFB + 2 φB + region (e.g. room temp.)
C ' OX
ε
C ' OX =
per unit area)
t OX
P-Channel MOSFET
kBT § n ·
φ = ln¨ ¸
2εSqND 2φB
where B
q © ni ¹
VT = VFB − 2 φB − n ≈ ND for extrinsic temperature
ε
C ' OX =
per unit area)
t OX
4 - 37
Recall these threshold voltage expressions from the MOS capacitor module. They can be used to approximate the threshold
voltage of an ideal (large geometry) MOSFET. Keep in mind, however, that the MOSFET inversion charge comes from the source
rather than from thermally-generated minority carriers in the substrate/well, so this is only an approximation.
4 - 38
Aside: Work Function Mismatch for Poly-Si Gate
Poly-Si gate P-channel transistor
Al-gate P-channel transistor
Poly-Si gate N-channel transistor Al-gate N-channel transistor

substrate/well
doping concentration
4 - 39
As previously discussed, modern MOSFETs are fabricated with poly-silicon gates instead of metal (aluminum) gates. The poly-Si gate is heavily
(degenerately) doped, like the source/drain regions.
This graph shows experimentally-determined values of the gate-to-substrate workfunction difference ΦMS (≡ φM - φS) for various gate materials (aluminum,
N+ poly-Si, P+ poly-Si, and gold) over N-type and P-type Si. (ΦMS can be determined experimentally by comparing the relative shifts in the C-V curves for
these various capacitors when fabricated on the same oxidized silicon substrate.)
Notice that the aluminum-gate capacitors have a negative value of ΦMS (i.e. φM < φS) and hence VFB (flatband voltage) for both N-type and P-type substrates
(wells), as discussed in module 3.
A modern N-channel transistor typically consists of an N+ poly-Si gate over a P-type substrate/well. The Fermi level in the N+ poly-Si is essentially at the
conduction band edge, and the Fermi level in the P-type substrate is below mid-gap. Therefore, the gate has a smaller work function (as measured between
EF and EVAC) than the substrate, and ΦMS (and hence VFB) is negative, as was the case for an aluminum gate. This means the MOSFET is in depletion at
equilibrium (no applied gate voltage), and VT is lowered by an amount ΦMS = VFB (ignoring oxide charge). As the substrate doping is increased, EF moves
down further from mid-gap, and ΦMS increases in magnitude, as shown on the graph.
A modern P-channel transistor consists of a P+ poly-Si gate over an N-type substrate/well. The Fermi level in the P+ poly-Si gate is essentially at the valence
band edge, and the Fermi level in the N-type substrate is above mid-gap. Therefore, the gate has a larger work function than the substrate, and ΦMS (and
hence VFB) is positive, as shown on the graph. This means the MOSFET is in depletion at equilibrium, and VT is less in magnitude by an amount ΦMS = VFB
(ignoring oxide charge). As the substrate doping is increased, EF moves up further from mid-gap, and ΦMS increases.
Notice that the N-channel and P-channel transistor ΦMS values are more closely matched to each other in magnitude when the transistors are fabricated using
poly-Si gates instead of Al gates. In other words, the two types of transistors are more similar to each other in terms of flatband voltage (magnitude) and
threshold voltage shift (i.e. both VTN and VTP are shifted down in magnitude by about the same amount). This can be an advantage in circuits which use both
types of transistors together (i.e. CMOS circuits, discussed in module 5).
4 - 40
MOSFET - Useful Equations (cont.)
ID-VDS Equation: Square-Law Theory
Drain Current - Linear Region

β
ZµeffC ' OX ª VDS º
( GS − VT ) −
L = channel length
ID = « V »VDS Z = channel width (perpendicular to L)
L ¬ 2¼ µeff = surface mobility [~ 500 cm2/V·s for electrons in Si at 300K, ~ 150 cm2/V·s for holes]
C’OX = gate capacitance per unit area = εOX/tOX
β = gain / transconductance factor
for VGS ≥ VT, VDS < VDS(SAT)
Drain Current - Saturation Region (Drive Current)
substituting VDS ( SAT ) = VGS − VT
ID ( SAT ) =
ZµeffC ' OX
2L
VGS −VT ( ) 2
for VGS ≥ VT, VDS ≥ VDS(SAT)
4 - 41
The Square Law Theory is a simple model of MOSFET operation. It assumes that the depletion region width for all points in the
channel remains fixed at WT, even when VDS > 0. Note that ID varies linearly with VDS when VDS is small (VDS << VGS – VT , i.e. VDS
<< VDS(SAT) ). As VDS approaches VDS(SAT), ID is reduced by the VDS2/2 term, and the ID-VDS curve starts to slope over leading
into saturation; this “slope over” transition region between linear and saturation is commonly called the triode region.
The multiplier out in front of the equation is sometimes referred to as the gain (aka. gain factor, transconductance factor), β, of the
MOSFET.
Note that the electron mobility is typically much greater than the hole mobility - the exact values depend a great deal on the
transistor design and process technology, but typically the electron mobility is 2 to 4 times greater than the hole mobility.
Therefore, all other factors being equal, an N-channel transistor will have a higher drive current than a P-channel transistor
(discussed later) - again, the difference is technology-dependent, but it is common to see N-channel transistors with 2 to 4 times
more drive current than the equivalent P-channel transistor.
Note also that surface mobility decreases with increasing temperature, due to the increased frequency of scattering events. Thus,
the MOSFET will have a lower ID at higher temperature.
The utility of the Square-Law Theory lies in its simplicity; it is useful for understanding general trends, basic inter-relationships,
etc.
4 - 42
ID-VDS Equation: Bulk-Charge Theory
ª 3
º½
µeffC ' OXZ °°§ 4VWφB «§ VDS · § 3VDS ·» °
2
VDS · °
ID = ® ¨ VGS − VT − ¸V DS − «¨1+ − ¨1 +
¸ © 4φB ¹» ¾ ¸ for VGS ≥ VT, VDS < VDS(SAT)
L ° © 2 ¹ 3 «© 2φB ¹ »°
°¯ ¬« ¼» °¿
Square-Law Theory kBT § NA ·
φ =
B ln¨ ¸
q © ni ¹
qNAWT qNAWTtOX
VW ≡ =
C ' OX εOX
1
½
°ª 2 º § VW ·°° 2εS (2ϕB )
2
° VGS −VT § VW · WT =
VDS ( SAT ) = VGS − VT − VW ®« + ¨ 1+ ¸ » − ¨¨©1 + 4ϕB ¸¸¹¾ qNA
° 2φB © 4φB ¹ °
Square-Law
° «¬ »¼ °
Theory ¯ ¿
4 - 43
The Bulk-Charge Theory is more complex than the Square-Law Theory, but gives results that are in better agreement with
experimental observations. It takes into account the fact that the depletion region width (“bulk charge”) varies from source to
drain, i.e. looking down the MOSFET channel, gate charge is not balanced solely by changes in the inversion charge, but also by
changes in the depletion layer charge.
The extra terms in the Bulk Charge model act primarily to reduce ID and VDS(SAT) wrt. the Square Law Theory. The accuracy of
the Square-Law Theory improves as the substrate doping and/or gate oxide thickness is decreased (i.e. as the body factor γ is
decreased). In fact, for NA → 0 (i.e. φB → 0) and tox → 0 (i.e. VW → 0), the Bulk-Charge Theory mathematically reduces to the
Square-Law Theory (because the multiplier in front of the second term goes to zero).
Many other models exist. Typically, accuracy is gained at the expense of simplicity. Many models are empirical or semi-
empirical. Many apply to only a certain subset of MOSFETs, such as those of a certain size or geometry, or those fabricated on a
particular fab process.
4 - 44

4 - 45
This graph compares the Square-Law Theory to the Bulk-Charge Theory. Note that the Bulk-Charge result approaches the Square-
Law prediction as the substrate doping is lowered.
4 - 46
Conductance
for VDS << (VGS – VT)
dID β [(VGS − VT ) − VDS ] ≈ β (VGS − VT ) linear

gd = =
dVDS
0 saturation
drain voltage
ZµeffC ' OX
where: β=
L
Transconductance
dID βVDS linear
gm = =
dVGS β (VGS − VT ) saturation
gate voltage
4 - 47
Conductance (g) is the reciprocal of resistance, i.e. g = 1/R. It measures the change in current for a given change in applied
voltage.
When the transistor is operated in the linear regime, it behaves like a simple resistor. The ID-VDS characteristic is a straight line,
the (constant) slope of which is equal to the conductance gd (aka. drain conductance or output conductance) of the device, i.e. the
change in drain current that results for a given change in source-drain voltage. To obtain an expression for gd, we differentiate the
ID-VDS relationship from the Square Law Theory wrt. VDS (to obtain an expression for the slope). Furthermore, in the linear region,
far from saturation, we can make the simplification that VDS << VDS(SAT) , i.e. VDS << (VGS - VT). We see that the resulting
expression for gd is constant wrt. VDS , as expected. It also shows that the conductance increases with increasing VGS , decreasing
VT , wider Z (channel width), and/or shorter L (channel length), as expected. Note that as VDS approaches VDS(SAT) = VGS – VT , the
conductance diminishes (triode region) and eventually becomes zero (saturation). This is also expected: the drain current does not
change with drain voltage in saturation (slope = 0), as previously discussed.
The transconductance (gm) measures how the drain current changes with applied gate voltage. It is obtained by differentiating the
ID expression from the Square-Law Theory wrt. VGS. For the linear region of operation, gm is proportional to VDS. In saturation
(i.e. substituting VDS = VGS – VT, or differentiating the square-law expression for ID(SAT) directly) the transconductance is seen to
be proportional to VGS. (These facts can be verified by careful inspection of the ID-VDS plots for various values of VGS.) As
expected, the transconductance increases for decreasing VT , wider Z (channel width), and/or shorter L (channel length).
The conductance and transconductance are useful for modeling the behavior of transistors in circuits, especially when ac signals
are applied to the transistors.
4 - 48
Aside: Back Bias / Body Effect
• •
Surface potential at threshold with back bias:
Ψs = 2φB + VBB
N+ N+
Threshold voltage with back bias:
P
2εSqNA 2φB + VBB
• VT = VFB + 2 φB +
-V BB C ' OX
q(Vbi + VBB)
EC •••••••••••••• ••••••••••••••
EF
oooooooooooooooooo
EV
4 - 49
We have studied the transistor with the backside/well contact grounded. We now study the case where the backside/well is biased
as shown*. Consider the effect on the source: the source diode is reverse biased by VBB, and hence the barrier height is increased to
Vbi + VBB, which increases the threshold voltage of the MOSFET. The net effect is that VT is increased – the surface potential at
threshold is now ΨS = 2φB + VBB. This also reduces subthreshold leakage and tends to make the subthreshold swing S smaller (i.e.
steeper ID-VGS slope). The effect on S is more pronounced for devices with a larger body factor γ. The MOSFET’s reaction to
backside biasing is sometimes called the body effect.
Back biasing was used as an electrical technique for increasing and tailoring the threshold voltage prior to the use of VT adjust
implants. It is still used in some specialized applications. For example, the Intel® StrongARM (aka. XScaleTM) microprocessor
employs this technique to reduce leakage current and achieve impressively low static power consumption, ideal for
mobile/handheld applications and systems with low thermal tolerances/budgets (such a closely-packed microprocessor banks).
(Note: This is just one of it’s power-saving techniques.)
* Note: One would not apply a +VBB bias to the substrate/well of an N-channel transistor. Doing so would forward bias the source
diode, hence the gate would no longer control the transistor (it would always be on). Similarly, one would not apply a –VBB bias to
a P-channel transistor. The backside bias can only be used to increase, not decrease, the threshold voltage.
4 - 50
MOSFET - Speed
+ Vcc
(logic 1)
V ID(SAT) R
0V
(logic 0) t
ideal
C
+ Vcc
(logic 1) t
t −
V ~e RC ~e RC
0V
(logic 0)
t
higher drive current real higher drive current reduces this
reduces this rise time, as fall time (pull down), as does
does lower RC time lower RC
4 - 51
The speed (maximum clock frequency) of a circuit can be very important, e.g. for a microprocessor.
The speed of a circuit/chip depends heavily on its architecture and design. Architects and design engineers have become quite
good at maximizing circuit speed.
Speed also depends a great deal on the transistors and interconnects (i.e. the fab process capabilities). Device engineers and
process engineers have become quite good at tweaking every last drop of performance out of the transistors. It is very challenging
to do this while maintaining good throughput, yield, and reliability.
The speed of a circuit depends on the amount of charge that must be moved to charge/discharge nodes (RC) and the current
available to move it (ID(SAT)). From the transistor and process technology standpoint, to maximize clock speed (frequency):
1. Increase the drive current, ID(SAT). This allows the transistor to charge an interconnect line faster, thus driving the next
stage (RC load) from logic 0 → 1 faster. It also allows a pull-down transistor to discharge a line faster, driving it from logic 1 → 0
faster.
2. Decrease the resistance and/or capacitance of the metal interconnect lines. This reduce the RC time delay of the circuit,
allowing signals to propagate faster.
4 - 52
MOSFET - Speed (cont.)
ID ( SAT ) =
ZµeffC ' OX
2L
VGS −VT ( )
2
source gate drain

• • •
tOX
N+ N+
L
•
backside/well
4 - 53
To increase drive current:
Reduce the channel length (L)
• Increased off-state leakage current
• Leads to short-channel effects (discussed later ): hot electron effects, DIBL/punchthrough, VT reduction, velocity saturation, channel length modulation
Reduce the threshold voltage (VT)
• Lighter substrate/well doping: leads to short channel effects (increases W at source/drain), of particular concern: degrades punchthrough margin
• Thinner gate oxide (tOX)
- Increased reliability concerns about oxide wearout, increased susceptibility to defects/pinholes in gate oxide
- Reduced dielectric breakdown voltage
- Increased gate leakage current (tunnel current)
- Increased susceptibility to electrostatic discharge (ESD) – during fabrication (plasma processing), or handling of the packaged chip (static charge build-up on pins)
-- Antenna (NAC) diodes are used to protect gates during fabrication
-- ESD protection circuits are included in the I/O pads
• Raise the gate dielectric constant (εOX), e.g. nitridation of gate oxide, high-K gate dielectrics, etc.
• Note: VT must stay above the noise margin (typically on the order of 0.1V): shallow VT adjust implants are used to raise the surface doping and hence |VT|
Increase the supply voltage
• Reliability concerns (e.g. gate oxide wearout, hot electron effects, latchup, etc.)
• Increased power dissipation and thermal concerns (ultimately limits circuit density and maximum speed of operation)
Temperature Dependence:
Increase the channel width (Z)
Note that surface mobility (µeff)
• Reduces transistor density (increases die size) decreases with increasing
• Increases gate capacitance (because increases gate area) temperature (due to increased
scattering w/ oxide interface and Si
To reduce RC: atoms) thus reducing β and hence
Reduce metal, via, and silicon-contact resistances ID(SAT). It can be shown that β and
ID(SAT) are proportional to T-1.5.
• silicided source/gate/drain contacts (Note: VT is reduced as temperature
increases, as discussed in module 3,
• good circuit layout practices – e.g. use larger and/or more contact openings (note: limits circuit density), optimize metal routing, etc.
but this effect is less pronounced
• copper interconnects (lower resistivity than aluminum) than the reduction in β). Metal
resistances also increase with
• thicker/wider metal lines (note: this will decrease R but increase C in general)
increasing temperature. Therefore,
Reduce parasitic capacitances in the circuit interconnects circuit speed decreases as
temperature increases. Note that
• low-K interlayer dielectrics (ILD)
leakage current (junction leakage
• thinner and/or narrower metal lines (note: this will decrease C but increase R), spaced farther apart (note: increased pitch will reduce circuit density) and subthreshold leakage) also
increases with increasing
• Manhattan layout (metal lines on alternating layers are orthogonal, minimizing overlap area)
temperature. (The increase in
Reduce parasitic resistances and capacitances in the transistors (discussed in more detail shortly) subthreshold leakage current is due
to the reduced threshold voltage.)
• shallow source/drain junctions (reduced junction capacitance), reduced gate-to-source/drain overlap (Miller) capacitance, etc.
• good layout practices can reduce series resistance
4 - 54
MOSFET - Parasitic Capacitances
metal 2
lines
ILD 1
metal 1
lines
gate vias /
ILD 0 oxide L contacts
Cgs Cgb Cgd
N+ LOV N+
Leff
Csb Cdb
4 - 55
This diagram shows the parasitic capacitances inherent in the MOSFET structure. They are called “parasitic” because they act as loads in the circuit – i.e. these capacitors must be charged and discharged as the
transistors change logic states (0 ↔ 1). This slows down the transistor circuit. (There may be more capacitances than these to consider, especially for advanced transistor designs. These are the most common
ones, and we will used them to illustrate the basic concepts.)
Parasitic Capacitances inside the Transistor:
The parasitic capacitances internal to the transistor limit its switching speed, i.e. how fast the device can charge/discharge its own capacitances in response to a change in applied voltage. The gate-to-
source/drain overlap capacitance is sometimes called the Miller capacitance (denoted Cgs and Cgd above). The overlap results from lateral diffusion of the source and drain implanted regions due to subsequent
thermal cycles in the fabrication process. It is desirable to minimize the overlap area in order to minimize this capacitance. However, note that in modern FET structures, the poly-Si gate is actually much
thicker than the channel is long (contrary to the diagram above, which is not to scale). Hence the fringing component of the overlap capacitance is non-negligible, and can not be reduced to zero even if the
actual overlap area is.
The gate capacitance Cgb is a two-sided story. When we consider the transistor as a driver, we want a high gate capacitance in order to create a stronger channel at a given applied gate voltage, thus increasing
the drive current and hence the circuit speed. But when we consider the transistor as a load, we would prefer to have a low gate capacitance. This trade-off must be effectively managed by circuit designers.
However, for a properly designed digital circuit, the trade-off is clearly in favor of using thinner gate oxides to maximize the drive current of the transistors. Aside: An additional capacitance in the gate comes
from poly depletion (not shown) – i.e. the fact that, unlike a metal gate electrode, a depletion region will form inside the poly-Si gate electrode at the poly-SiO2 interface. (And as you might expect, this poly
depletion will also affect other device parametrics such as the threshold voltage, since the applied gate voltage now drops across the poly depletion layer, the gate oxide, and the depletion region underneath the
gate.) This poly depletion region is minimized by heavily doping the poly-Si (specifically, at the poly-SiO2 interface).
We know that the source and drain regions are PN junctions, and hence each has a junction capacitance Cj associated with it (due to the fixed ionic charge in the depletion region). Recall that, to a first order
approximation, Cj = εsA/W, hence the capacitance can be reduced by using a lower doping concentration on the light (substrate/well) side of the junction, which will increase W. (This, however, will reduce
punchthrough margin, as discussed later, and may also affect other device parametrics such as threshold voltage.) As transistors are scaled down to become smaller and denser, the junctions must also be scaled
down (i.e. shallower junctions and less area) in order to maintain and maximize the speed performance. This can be accomplished with shallower source and drain implants, and by minimizing the thermal
cycles of subsequent processing in order to minimize diffusion (e.g. perhaps by using rapid thermal annealing (RTA), etc.). However, shallow junctions do create other processing complexities (e.g. the danger
of saliciding through the junctions), which must be managed. (Other courses address such issues in greater detail.)
Parasitic Capacitances in the Interconnects:
Parasitic capacitance is present where there is conductive material (i.e. metal or silicon) separated by insulator. Capacitance slows down the circuit, and causes capacitive coupling (noise/interference) between
neighboring signal lines. There is parasitic capacitance between metal-1 lines and the silicon surface, and between layers of metal (in the case shown here, between metal-1 lines and metal-2 lines). Thicker
ILD will reduce this capacitance, but there are practical limits on how thick the ILD can be from a processing standpoint. Using narrower metal lines will also reduce this capacitance (by reducing the
overlapping surface area), but of course this also raises the resistance of the metal lines (by reducing the cross-sectional area). A “Manhattan” layout, whereby the metal lines in alternating layers are
orthogonal, can also help to reduce the capacitance in the IC by minimizing the total metal-metal overlap area. There is also parasitic capacitance between adjacent, parallel metal lines. While reducing the
thickness of these metal lines will decrease this capacitance (by decreasing the sidewall area), it will also increase the resistance of the metal line (by reducing the cross-sectional area).
The resistances of the metal lines, and the parasitic capacitances between them, make up the RC load of the interconnect circuitry. Larger RC product results in larger propagation delay for signals, and hence a
slower circuit. Therefore, it is desirable to minimize RC.
4 - 56
MOSFET - Parasitic Capacitances (cont.)
Off Linear Saturation
(subthreshold) (triode)
COV 1 2
Cgs COX + COV COX + COV
2 3
COV 1 COV
Cgd COX + COV
2
Cgb COX 0 0
Csb Cj Cj Cj
Cdb Cj Cj Cj
ε
COV =
OX
where: ZL OV overlap (Miller) capacitance
MOS Capacitor: t OX
- Inversion layer is electrically isolated from the outside world
- Inversion charge comes from R-G of minority carriers
? ε
C =
OX
- Capacitance depends on frequency
OX ZL eff gate capacitance
MOSFET:
- Inversion layer (channel) is electrically connected to source/drain
what about the
MOS capacitor
t OX
εA
- Source is an ample supply of electrons at any practical frequency C-V frequency
dependence?
Cj =
- Charge fluctuates on either side of gate oxide (like parallel-plate) s j
- MOSFET gate capacitance is εOXA/tOX at any practical frequency PN junction capacitance
W 4 - 57
This table shows how to approximate the MOSFET internal capacitances using straightforward expressions that are reasonably accurate. Of course, more in-
depth modeling can be performed when more precise capacitance values are required (this typically involves integrating the charge distributions in the
regions of interest).
Off:
When the MOSFET is off (i.e. VGS << VT), no channel exists and hence Cgs = Cgd = COV, where COV is the gate-to-source/drain overlap (Miller) capacitance
discussed previously. COV can be calculated from the overlap area, using the expression above. The gate-to-substrate capacitance Cgb can be approximated
as the parallel-plate capacitance of the gate, CG (note that the effective channel length, Leff = L - 2LOV, is used in this expression). Csb and Cdb are the source
and drain PN junction capacitances, and can be approximated using the expression given for Cj (see PN Junction module). Note that none of these
expressions take fringing fields (perimeter capacitance) into account.
Linear:
In the linear operating regime, a channel is present from source to drain. A more precise definition of Cgs is that it is the gate-to-channel capacitance
represented as a lumped capacitance at the source end. And similarly for Cgd. The total gate-to-channel capacitance is CG, and we arbitrarily lump ½CG at
each end of the channel (sometimes it is necessary to revisit this “symmetrical” partitioning of COX and change the source-to-drain ratio). The channel
effectively “shields” the substrate from the influence of the gate (i.e. the capacitance associated with the subgate region has been accounted for in the gate-to-
channel capacitance), so Cgb drops to zero. Regarding the junction capacitances, recall that the depletion depth W will be greater at the drain end (reverse-
biased by VDS).
Saturation:
In saturation, the channel is pinched-off from the drain. There is no inversion charge at the drain end, and potential variations at the drain end do not
influence the channel charge. Therefore, there is no contribution to Cgd from the channel, and the overlap capacitance is all that’s left: Cgd = COV. In
saturation, the channel takes on a triangular shape as previously discussed (i.e. deeper channel at the source end, tapering off to zero at the pinch-off point
near the drain). The gate-to-source capacitance Csb is affected by the channel charge, and a detailed treatment of the triangular channel suggests that only
about 2/3 of CG should be added to Cgs.
Important Note on MOSFET Gate Capacitance: Consider the P-substrate/well MOS capacitor discussed in module 4 vs. the N-Channel (P-substrate/well)
MOSFET discussed here. Recall that the inversion capacitance of the MOS capacitor depends on the frequency of operation – at lower frequencies, the
inversion layer could respond (via minority carrier R-G) to provide charge balance; at higher frequencies, charge was balanced by depletion charge (majority
carrier response) because the minority carrier R-G process was not fast enough. It is important to note that the inversion layer in a MOS Capacitor is
isolated from the outside world; minority carrier generation is its only source of electrons. A very important difference exists for the transistor: the
MOSFET inversion layer (channel) is electrically connected to the outside world through the source and drain, and the channel charge comes from the
source (not from minority carrier generation). The source is an ample supply of electrons even at very high frequencies. So at any practical frequency of
operation, the MOSFET has charge fluctuating on either side of the gate oxide like a parallel-plate capacitor, hence Cg = εOXA/tOX. However, the C-V
information presented in the previous module is useful for understanding some fundamental aspects of device physics, and for characterizing discrete MOS
capacitors (e.g. during process development, as a fab process monitor, or for failure analysis purposes).
4 - 58
MOSFET - Series Resistance
source gate drain
• • •
Rs ID Rs
V’DS
N+ Rs Rs N+
VDS
P
•
backside/well
V ' DS = VDS − 2 IDRs
ZµeffC ' OX
ID = (VGS − VT )V ' DS
L
( Z / L) µeffC ' OX 2 µeffC ' OXRsZ

ID = (VGS − VT )VDS where: α =
R
1 + αR (VGS − VT ) L
4 - 59
It should also be noted that there are parasitic resistances associated with the source and drain regions. If these regions are silicided and the transistors
are laid out properly, these resistances can be largely ignored for most digital circuit applications. However, it may not be appropriate to ignore these
resistances for some analog and digital circuits, especially if a very aggressive fabrication process is used. In general this series resistance is undesirable
because it reduces drain current, contributes to the RC delay, and dissipates power in the form of heat.
This resistance has several components: (1) the resistance of the doped source/drain region; (2) the resistance associated with the metal-to-silicon
contact; and (3) the “spreading resistance” due to current crowding in going from the doped source/drain region to the “sheet” of inversion charge in the
channel. The resistance of the doped source/drain regions is minimized by doping them heavily (degenerately). The metal-to-silicon contact resistance
is minimized by using silicide in the fabrication process (a silicide is a metal-silicon alloy such as titanium silicide (TiSi2) or cobalt silicide (CoSi2)
formed at the interface to provide a lower-resistance contact).
We lump all three of these components into one constant Rs representing the total series resistance. We assume for simplicity that the source and drain
resistances are each equal to Rs. We designate V’DS to be the voltage drop across the channel alone in the absence of all series resistance. We let VDS be
the voltage drop across the device including the series resistances, such that V’DS = VDS – 2IDRs (by Kirchoff’s voltage law). We substitute this into the
IDS-VDS expression from the square-law theory, and assume that VDS << VGS – VT (so that we can ignore the VDS2 term for illustration purposes) and that
IDRs << VGS – VT (to ignore the reduction in the effective gate-to-source voltage). Observe that αR will be small for a conservative fabrication process
(larger L, thicker tOX, larger contact windows, etc.), hence the series resistance has a relatively small effect and ID will be close to the ideal case (where it
is assumed that Rs = 0). However, αR will be larger for a more aggressive process, and will reduce ID accordingly.
Of course, more sophisticated resistance modeling can be performed (though, typically, accuracy is gained at the expense of simplicity). This simple
model is presented to illustrate the basic concepts surrounding source/drain series resistance.
It should be noted that the poly-Si gate resistance can be considered as well, which consists of the resistance of the poly-Si (minimized by doping it
heavily) and the contact resistance (minimized by using silicide). With proper layout this resistance can be ignored for most digital circuit applications.
Its main effect is to reduce the effective gate voltage by placing an IR drop between the gate power source (signal) and the gate oxide.
4 - 60
MOSFET - Speed (cont.)
maximum
clock
frequency
Transistor Limited
(drive current)
Interconnect Limited
(RC)
ID(SAT)
4 - 61
By plotting the maximum clock frequency of the chip vs. the drive current, we can see where the circuit becomes RC limited --
a.k.a. “interconnect limited”, or “back-end limited” since the metal/ILD layers (and perhaps the chip package is included here too)
are the “back end” of the IC manufacturing process. In the RC limited regime, increasing the drive current of the transistors has
little or no effect on the speed of the circuit, because the limiting factor is the RC time (propagation) delay in the circuit
interconnects. Appreciable speed improvements can only be made by reducing the RC of the interconnect circuitry. For example,
this is the main reason why the industry has switched from aluminum interconnects to copper, because copper has a much lower
resistance. Another example is the use of low-k dielectrics* for ILD -- the lower dielectric constant means lower capacitance for
the interconnect circuitry.
Delays along the critical “speed paths” (bottlenecks) in the circuit can be reduced by improving the circuit design. Thus, it is
common to see subsequent versions/revisions of an IC become progressively faster, as the critical speed paths are identified and re-
engineered by the design team. So improving the speed of a chip is a joint effort between the design community and the
manufacturing / CMOS process development community.
* The name “low-k” refers to the common definition of the dielectric constant as k = ε/ε0 , where ε is the permittivity of the material in question and ε0 is the
permittivity of free space. Recalling that, in general, capacitance can be expressed as C = εA/t, where A is the overlap area and t is the thickness of the
dielectric, we see that lower k implies lower ε, which in turn implies lower capacitance. As previously discussed, ILD is typically made of SiO2 (perhaps
with small amounts of phosphorous to act as a contamination gettering agent), and the addition of fluorine can be used to form a low-k dielectric.
4 - 62
The P-Channel MOSFET at a Glance
VDS(SAT) = VGS - VT
ID
Saturation VGS = +3 V
VT < VGS < 0

ID
• -VDS N-channel
• Linear
MOSFET
VGS = +2 V
P+
VGS = +1 V
oooooooooo
P+ P+ 0
VGS = -1 V VDS
VGS = -2 V
Linear
N Saturation
VGS = -3 V
P-channel
MOSFET
4 - 63
The forgoing discussion has focused on the N-Channel MOSFET for illustration purposes, but the basic concepts are directly
applicable to P-Channel MOSFETs as well.
For the P-Channel MOSFET, the current carriers are holes rather than electrons, and therefore the polarities of the gate voltage,
threshold voltage, and drain voltage are negative, opposite to the case of the N-Channel device.
The basic operation of the device is analogous to that of the N-Channel MOSFET. A negative gate voltage greater than (in
magnitude) the threshold voltage is applied to invert the semiconductor surface in the channel region, creating a hole channel
which connects the source and drain. A negative drain voltage is applied to attract the holes, creating a drain current. For lower
drain voltage, the ID-VDS relationship is linear; for VDS ≥ VDS(SAT) (in magnitude), the drain current is saturated. Note that the
drain current flows in the opposite direction of the N-channel case.
As previously noted, holes have a lower effective mobility than electrons, and therefore, all other things being equal, a P-Channel
MOSFET will have lower drive current than an N-channel transistor. This can readily be seen on the graph above. And because
the lower mobility limits acceleration, “hot hole” effects (discussed later) are generally not observed.
4 - 64
Why Silicon?
Silicon is the semiconductor of choice for the modern digital IC industry:
S Good native oxide (SiO2)
S Low junction leakage
S Good thermal and mechanical properties
S Manufacturing maturity and lower cost
Counter points
- GaAs preferred for high-frequency analog devices and photonic devices
- SiGe, the future choice for high-speed circuits?
4 - 65
We are now at a good point to discuss why silicon is the semiconductor of choice for the modern digital IC industry, vs. other semiconductors such as
Germanium (Ge) or Gallium-Arsenide (GaAs). We also highlight some devices and applications where other semiconductors are preferred over Si, to
illustrate that the best semiconductor for the job depends on the job!
• Good native oxide (SiO2). Good adhesion properties, good dielectric properties, low-stress interface, easy to grow. High-quality gate oxides and isolation
oxides. Low density of interface traps (states) relative to other oxides (interface traps retard the motion of carriers in the channel, reducing the
effective/surface mobility). Germanium’s oxide (Ge2O3) is difficult to grow, is a poor-quality insulator, begins to dissociate at ~700 oC, and is water soluble
(there are lots of furnace cycles and water rinses in the fab process!). Gallium-arsenide also has a very poor native oxide, hence oxides are usually deposited
(not grown) on GaAs and generally are of inferior quality.
S Low junction leakage. Si has a larger band gap than Ge, thus reducing PN junction leakage current (I0). (Review the expression for I0 in the PN Junction
module – note that a larger band gap implies a lower ni and hence reduced leakage current.) This is very important for CMOS devices, especially as
transistor densities increase, because it reduces static power consumption and the non-idealities associated with leakage current (discussed previously).
S Good thermal and mechanical properties. Si has a higher thermal conductivity than Ge and GaAs, which is desirable for conducting heat away from
devices and circuits. Si is also a relatively robust material, unlike GaAs which is very brittle and hence difficult to work with in a manufacturing
environment. GaAs is also toxic and carcinogenic, requiring additional safety measures for workers and the environment, whereas Si is a much safer
substance to work with.
S Manufacturing maturity and lower cost. The first devices and integrated circuits were made using Ge. However, Si quickly replaced Ge, for some of
the reasons cited above, and now enjoys a maturity in terms of process technology that makes it much cheaper than other materials.
S Counter Points. GaAs has a much higher electron mobility than Si, and is the dominant technology for very high frequency analog devices (e.g. mixers,
multipliers, etc.). GaAs (and other hybrid semiconductors) is also preferred for photonic and opto-electronic devices, such as photodetectors and
semiconductor lasers, because it is a direct band gap material (not discussed). Silicon-Germanium devices have also been introduced, and are capable of
higher-speed operation than pure Si devices – such devices may gain popularity in future generations of digital integrated circuits.
4 - 66
Exercise: Linear I-V of a MOSFET
1. Derive an expression for the amount of inversion charge in an N-Channel MOSFET for a given applied gate voltage VGS ≥ VT. (Hint: Q = CV.)
2. If a source-to-drain voltage VDS is applied across this channel, derive an expression for the current through the MOSFET, assuming it is in the linear
region of operation (i.e. VDS << VDS(SAT) ). (Hint: the charge Q is injected into the channel at the source end by the forward-biased junction and drifts to
the drain under the influence of the source-to-drain electric field ε = v /µ

d n = VDS /L.)
3. What is the resistance R of the channel?
4 - 67
Are the equations you have derived here consistent with those presented earlier in this module?
4 - 68
Exercise: Linear I-V of a MOSFET - Solution
1. Only values of VGS above VT create inversion charge, therefore (VGS - VT) is the “effective voltage” for inversion.
ε A ε ZL
Q = CV = (V − V ) = (V − V ) = ZLC ' (V − V )
OX OX
GS T GS T OX GS T
t OX t OX
2. The drain current is the amount of charge moving across the channel per unit time. The forward-biased source junction injects a charge Q of electrons
into the channel, which will drift across the channel to the drain in a time t dictated by the source-to-drain electric field, effective electron mobility, and
channel length.
Q
ID =
t
L L L
2
ε = source-to-drain electric field
t =
vd
=
ε
µ eff
=
(V DS / L ) µ eff
= L
V DS µ eff
vd = drift velocity (speed) of electrons
Z µ eff C ' OX
ID = (V GS − V T )V DS
L
3. The conductance is readily obtained from the above expression. Resistance is the reciprocal of conductance.
ID ZµeffC ' OX
g= = (VGS − VT )
VDS L
1
R=
g
4 - 69
These equations are consistent with those presented earlier in this module. Note that we have only considered the linear region of
operation of the MOSFET here.
4 - 70
Part 2 - Small Geometry MOSFET
4 - 71
We will now study the physics of small-geometry (short-channel) MOSFETs.
4 - 72
MOSFET - Short Channel
source gate drain

• • •
N+ N+
L
•
backside/well
4 - 73
When the depletion regions at the source and drain junctions are a negligible fraction of the channel length (L) and width (Z), the
transistor is said to be a large-geometry MOSFET. Up to this point, we have been discussing large-geometry MOSFETs.
When the source/drain depletion regions are an appreciable fraction of L (but not Z), the transistor is called a short-channel
MOSFET. If the source/drain depletion regions are also an appreciable fraction of Z, it is a small-geometry MOSFET. In either
case, the behavior deviates from that of the large-geometry MOSFET. The presence of the depletion regions can no longer be
ignored, as they have a noticeable impact on the threshold voltage and the ID-VDS relationship. There are also some reliability
issues associate with short-channel transistors, such as hot electron effects.
Note that making the poly gate shorter will reduce L, and increase the short-channel behavior. Note also that reducing the
well/substrate doping will increase the depletion region width at the source/drain edge, also increasing the short-channel behavior.
(It is also worthwhile to note that making the gate oxide thinner will reduce the amount of short-channel behavior, as it gives the
gate more control over the channel region and makes the electric field lines more vertical in the depletion regions.)
* Technical Aside: For a large-geometry MOSFET, the source and drain depletion regions are of negligible size compared to the
length and width of the channel, and therefore the electric field lines are regarded as vertical for all points along the channel, even
near the source and drain (this is sometimes referred to as the gradual channel approximation). This essentially allows us to ignore
the “edge effects” and model the subgate electric field as one-dimensional. However, if the depletion regions are an appreciable
fraction of L only (or Z only, though this “narrow-width transistor” is not common) the subgate electric field becomes two-
dimensional. If they are an appreciable fraction of L and Z it becomes three-dimensional.
4 - 74
Short Channel MOSFET – Hot Electron Effects
Channel Hot Electron (CHE) Injection
peak electric
+VGS field region
• • +VDS
gate oxide •
N+ • N+
electron
Impact Ionization
peak electric
+VGS field region
• • +VDS
gate oxide ••••

N+ • *
o o N+
electron oo
ISUB
4 - 75
Channel Hot Electron Injection (CHE)
The drain voltage drops across a smaller length in a short-channel transistor, hence there is a higher electric field in the channel region. This high field
accelerates electrons to high velocities, hence they are called “hot” electrons. The peak field occurs near the drain junction. Hot electrons can be injected
into the gate oxide near the drain edge, where they become trapped charges. As the concentration of trapped charge builds up over time, the threshold
voltage shifts (increases for N-channel). At some point, the circuit may stop working properly. This is a reliability concern.
Note that CHE is not always a bad thing. While it is a very undesirable effect in MOSFETs, CHE is the key ingredient for devices such as Flash EEPROM
memory cells (discussed in module 5).
Impact Ionization
Hot electrons can gain enough kinetic energy to cause impact ionization at the drain junction (see the PN Junction presentation for more on impact
ionization). Electrons created via the impact can be injected into the gate oxide near the drain, where they become trapped; over time this trapped charge can
build up, shifting the threshold voltage until the circuit no longer works properly. This is a reliability concern. Holes created via impact ionization are
repelled by the drain voltage and diffuse into the substrate, where they contribute to the substrate current ISUB. Substrate current is generally undesirable
because it can have detrimental effects on the circuit (e.g. can trigger latchup, can cause poor refresh times in DRAM, can introduce noise in mixed-signal
circuits, etc.).
Note: Because holes have a much lower mobility than electrons, “hot hole” effects are usually not of concern in P-Channel transistors.
Hot electron effects are less of a concern at lower supply (drain) voltages. Also, LDD (Lightly-Doped Drain) or “tip” implants can be used to grade the drain
junction, thus reducing the peak electric field and suppressing hot electrons (see module 1 for information on graded junctions). This, however, reduces the
performance of the transistor, due to the increased source/drain capacitance.
Of additional concern are circuit nodes that are subject to ESD (electrostatic discharge) events or voltage overshoot/overstress – these transistors may
experience occasional source-drain voltage “spikes” that cause short bursts of hot electron activity; proper design guards against such circuit behavior.
4 - 76
Short Channel MOSFET – DIBL & Punchthrough
VGS = 0 ramp +VDS VGS > VT ramp +VDS
• • • •
N+
εdrain N+ N+ N+
Ws Wd Ws Wd
P P
ID DIBL / Punchthrough
VBR Punchthrough
observed
drain
Normal Junction
breakdown Breakdown
voltage
(short-channel FET) (large-geometry FET)
L 0 VDS
4 - 77
In a short-channel MOSFET, the source and drain may be close enough for the drain voltage to influence the source diode. The width of the depletion region
at the drain (Wd) is determined by the drain voltage (reverse-bias); Wd increases with VDS. For the ideal PN junction, it was assumed that the electric field
(voltage) exists only in the depletion region. For a real PN junction, however, the electric field extends somewhat beyond the depletion region edges (i.e. the
edges are not sharply defined). Hence, the drain voltage can influence the source junction if the source and drain are in close proximity.
DIBL: The source and drain are close enough that the drain voltage can influence the source junction. The drain voltage lowers the source barrier, forward
biasing the source diode somewhat and increasing the diffusion current. This is called Drain Induced Barrier Lowering, or DIBL (pronounced “dibble”).
With DIBL, the gate voltage and drain voltage both influence the source barrier (unlike a large-geometry MOSFET, where the source barrier is modulated by
the gate voltage only). DIBL gives rise to a lower threshold voltage (i.e. VT is now a function of VDS) and higher off-state leakage current, which is
undesirable because it increases static power consumption and may contribute to other problems (e.g. noise, latchup, etc.). DIBL can also cause the linear or
saturation drain current to exhibit a diode-like increase as a function of VDS, as shown above. If DIBL becomes severe enough, the drain voltage can
actually have more influence on the source barrier than the gate voltage does, interfering with the operation of the MOSFET.
Punchthrough: If the drain depletion region extends far enough to touch the source depletion region (i.e. Ws + Wd ≈ L), source-to-drain punchthrough has
occurred in the MOSFET. The source junction becomes forward biased by the drain voltage, and a source-to-drain current arises. This current, which flows
through the contiguous depletion region from source to drain, is called space charge limited current, and goes as VDS2/L3. Hence the transistor has a high off-
state leakage current, and if the punchthrough becomes severe enough, the transistor may not work at all (i.e. the gate can’t turn the transistor off).
DIBL and punchthrough can be thought of as different degrees of the same phenomenon. The terms are sometimes used interchangeably, though the term
punchthrough should be reserved for space charge limited current (i.e. source electrons injected into a depletion region connecting directly to the drain)
whereas DIBL refers to PN junction injection (i.e. source electrons injected across the source depletion region and into the P-type subgate region).
The shorter the gate, the more susceptible the transistor is to DIBL and punchthrough. Reducing the substrate/well doping also makes the transistor more
susceptible to DIBL and punchthrough, as this causes Ws and Wd to become larger. The transistor must be designed such that the drain can resist the “back
pressure” of VDS and avoid punchthrough.
4 - 78
Short Channel MOSFET – Threshold Voltage
WT
N+ rj rj N+
L’
W W
s d
VT
qNAWT rj § 2WT ·
∆VT = VT ( short ) − VT (long ) = ¨ 1+ − 1¸¸
¨
C ' OX L © rj ¹
(short-channel FET) (large-geometry FET)
L
4 - 79
For a large-geometry MOSFET, the threshold voltage is determined primarily by the gate oxide thickness and the doping concentration underneath the gate
oxide. The influence of the source/drain depletion regions is negligible, and VT is not sensitive to L.
For a short-channel MOSFET, the source/drain depletion regions make up a non-negligible fraction of the channel length, and their effect on VT must be
considered.
A close-up view of the source/drain edges shows the effect of lateral diffusion of the source/drain implants. The dopant diffuses laterally underneath the gate
edges, and has a rounded profile characterized by a radius rj (which is approximately the junction depth). (The amount of lateral diffusion is typically 0.7 to
1 times the vertical (downward) diffusion, depending on the details of the fabrication process.)
In order for a channel to be created beneath the gate, the silicon there must be depleted and then inverted. The source and drain depletion regions assist in
inverting the bulk region under the gate. In the illustration above, some of the B- subgate depletion charge (e.g. in the shaded triangular regions) is balanced
by the Phos+ charge on the N-sides of the source and drain depletion regions (rather than being balanced by the gate charge). Thus, less gate charge is
required to start inversion, and VT is reduced.
This effect is negligible for large-geometry MOSFETs – all the charge in the subgate region (i.e. a rectangle of length L) is assumed to be balanced by the
gate charge. However, for a small-geometry MOSFET, the charge compensation by the source/drain regions can not be ignored, and the gate is responsible
for balancing the charge in the trapezoidal region of side lengths L and L’. This geometry can be used to derive the expression above for ∆VT, the difference
between the short-channel and long-channel threshold voltage. By examining ∆VT / VT(long), the relevant quantity for gauging the degree of short-channel
behavior, we see that there is less short-channel behavior for thinner gate oxide (tOX), higher doping concentration (NA), shallower junction depth (rj), and
longer channel (L).
The VT dependence on L leads to a VT mismatch between long and short transistors. This is undesirable for some circuits. A halo implant can be used to
achieve a closer match between the long- and short-channel VT’s. (Other courses discuss such fabrication techniques in detail.)
4 - 80
Short Channel MOSFET – ID-VDS Relationship
§ VDS ·
ID ( SAT ) short = (1 + λVDS ) ID ( SAT )long = ¨¨1 + ¸¸ ID ( SAT )long
© | Va | ¹
short-channel
long-channel
ID
VGS = +3 V
Saturation
Linear
VGS = +2 V
VGS = +1 V
Va 0 VDS
4 - 81
For a large-geometry MOSFET, it was assumed that the drain depletion region width (Wd) was a negligible fraction of the channel
length (L), and hence could be ignored when considering the ID-VDS relationship in saturation. Any change in Wd due to VDS was
assumed to be insignificant, having no impact on the saturation characteristic.
For a small-geometry MOSFET, Wd is a non-negligible fraction of the channel length, and modulation of Wd by VDS can not be
ignored. As VDS is increased beyond pinchoff, Wd also increases, thus resulting in a smaller effective channel length Leff and an
increased drain current ID. Hence, the drain current is not constant wrt. VDS in the saturation regime for a short-channel MOSFET.
As gate length is reduced, the slope of the ID-VDS curve in saturation becomes greater.
The Early voltage, Va, is the extrapolated zero-current intercept of the saturation ID-VDS characteristic. It can be used for a semi-
empirical calculation of the short-channel saturation current, as shown in the equation above. Note that its reciprocal, λ (units of
V-1), is sometimes used instead. In this equation, ID(SAT)long is the long-channel saturation current (e.g. calculated from the square-
law theory). Observe that as Va → ∞, ID(SAT)short → ID(SAT)long, as expected. For a given Va, ID(SAT)short varies linearly with VDS.
4 - 82
Short Channel MOSFET – Velocity Saturation
Drain voltage for velocity saturation: ID(SAT) – VGS steps are linear
ID for velocity saturation
Vsat = Lεsat =
VGS = +3 V
vd ( sat ) L VGS = +2 V
ueff VGS = +2 V
Drain current and transconductance: VGS = +1 V
ID ( SAT ) ≈ ZC ' OX (VGS − VT ) µeffεsat

VGS = +1 V
vd(sat) 0 with velocity saturation VDS
gm ≈ ZC ' OXµeffεsat = ZC ' OXvd ( sat )

without velocity saturation
Vsat = drain voltage at which velocity saturation occurs

vd(sat) = saturation drift velocity
velocity channel
εsat = electric field for velocity saturation (assumed same for electrons/holes) saturation pinch-off
voltage voltage
| MOSFET Saturation Voltage | = min[ |Vsat| , |VGS - VT| ]

4 - 83
We discussed velocity saturation in module 1. Recall that electrons and holes reach a saturation drift velocity vd(sat) of about 107 cm/s, and the electric field
at which this occurs (εsat) is about 3x104 V/cm (3 V/µm) for electrons and 105 V/cm (10 V/µm) for holes. These values for εsat pertain to electron and hole
motion through bulk silicon; εsat values for carrier motion at the surface of a MOSFET depend on the transistor design and process technology but are often
in the range 0.5 - 3.5 V/ µm (for simplicity, a single value is often used for both electrons and holes).
In a short-channel MOSFET, the carriers in the channel may achieve velocity saturation at some drain voltage lower (in magnitude) than the pinchoff voltage
VDS(SAT) = VGS – VT (and hence the saturation current will be correspondingly lower). The expression for this velocity saturation voltage, Vsat, is given
above. If this occurs, the MOSFET ID-VDS curve will saturate at VDS = Vsat (due to velocity saturation) instead of VDS = VGS – VT (due to channel pinchoff).
In other words, the MOSFET can not produce more current ID in response to increases in VDS because the carriers can’t move across the channel any faster.
Thus, the observed saturation voltage of a MOSFET will either be Vsat or VGS – VT, whichever is lower (in magnitude). For long-channel devices, Vsat is very
large, and the saturation voltage will be VGS – VT (pinchoff). For short-channel devices, however, it is often the case that ID saturates due to velocity
saturation before (instead of) pinchoff, and the observed saturation voltage is Vsat.
The easiest way to tell whether the MOSFET saturation is due to velocity saturation of pinchoff is to observe the relationship between the saturation current
and the applied gate voltage. If it is quadratic (i.e. ID(SAT) goes as VGS2 similar to the square-law theory), the saturation is due to pinchoff. If it is linear, the
saturation is due to velocity saturation (i.e. increasing the gate voltage causes a proportional increase in inversion charge and hence drain current, as indicated
by the expression above).
Note from the equation above that ID(SAT) is independent of L for the case of velocity saturation! This can be understood by recognizing that the transit time
for carriers to traverse the channel under velocity saturation is directly proportional to L (t = L/vd(sat)). Assuming the channel charge is constant, it is also
directly proportional to L (Qn = qnsZL, where ns here is the charge per unit area in the “sheet” of inversion charge). The current is I = Qn/t, and hence L
cancels out. In other words, there is a constant charge flow per unit W, and L does not matter (provided of course that it is small enough to allow velocity
saturation in the first place, per the first equation above).
Note that because electrons and holes converge to the same value of vd(sat), as discussed in module 1, N-channel and P-channel MOSFETs tend to have the
same ID(SAT) under velocity saturation conditions, other things being equal. In other words, the performance advantage of N-channel transistors over P-
channel transistors largely disappears if the transistors are velocity saturated.
4 - 84
Aside: Modeling Non-Idealities & Small-Geometry Effects
empirical parameter modeling
models DIBL, and short-channel and subgate depletion region slope from
narrow-width effects on VT source to drain (δ → 0 as γ → 0)
Z 1 ½
µ 0C ' OX ®[VGS − VT ' ( L, Z , VDS )]VDS − (1 + δ )VDS 2 ¾
L¯ 2 ¿ for VDS < VDS(SAT)
ID =
ª VDS º
{1 + θ [VGS − VT ' ( L, Z ,VDS )] + θBVBS}«1 +
¬ Lεsat »¼ saturation
voltage
models effective mobility models velocity
dependence on vertical field saturation
Z 1 2½
µ 0C ' OX ®[ V GS − V T ' ( L , Z , V DS )]VDS ( SAT ) − (1 + δ )V DS ( SAT ) ¾
L¯ 2 ¿
ID ( SAT ) =
§ ∆L · ª VDS ( SAT ) º
¨1 − ¸{1 + θ [VGS − VT ' ( L, Z , VDS )] + θBVBS }«1 +
© L ¹ ¬ Lεsat »¼
models saturation ID-VDS slope,
due to channel length modulation for VDS ≥ VDS(SAT)
(∆L is a function of VDS)
µ0 = empirical parameter representing the low-field effective/surface mobility (in the absence of vertical field degradation)
δ = empirical parameter to model the fact that the depletion region is not uniform in depth from source to drain as the Square-Law model assumes
θ = empirical parameter to model the amount by which the vertical field (VGS - VT’) degrades the surface mobility
θB = empirical parameter to model the effect of back bias VBS (substrate bias wrt. source) on mobility (typically on the order of 0.01V-1)
εsat = critical source-drain electric field for velocity saturation
VT’(L,Z,VDS) = threshold voltage adjusted for DIBL and channel length and width effects: VT’(L,Z,VDS) = VT - ∆VT(L,VDS) + ∆VT(Z) Source: Y.P. Tsividis, Operation and Modeling
VDS(SAT) = the saturation voltage of the transistor (due to pinchoff or velocity saturation) of the MOS Transistor, McGraw-Hill, 1987.
4 - 85
The Square-Law model can be modified with terms which approximate small-geometry effects, as well as some other non-idealities which affect both large and small MOSFETs. This approach
represents a compromise between intuitiveness and accuracy: we retain the simplicity and intuitiveness of the Square-Law equation, but add in terms (containing empirical variables) that adjust the
ID-VDS relationship to account for these various effects. The typical alternative is to have highly empirical formulas, usually very narrow in applicability (e.g. to transistors of a specific fab process)
and not offering much intuitiveness (e.g. numerical solution algorithms and curve fitting), that give very accurate results for the intended application. Note that this modified Square-Law approach
only works if each effect is small when considered individually, such that any interactions among these effects are negligible.
Linear Region
• Threshold Voltage Modifications: VT is reduced from its ideal large-geometry value by DIBL (VDS lowers the source barrier, hence VT decreases with increasing VDS). VT also decreases with
decreasing L (because the gate really only has to compensate the subgate depletion charge in the trapezoidal region discussed earlier). However, VT increases with decreasing Z due to the fringing
electric field along the width of the gate -- this fringing field makes the depletion region extend somewhat wider than Z (the width of the gate electrode), hence there is more depletion volume that
must be compensated by the gate and VT is higher (in magnitude). For large Z this effect is negligible because the fringing depletion region is an insignificant fraction of the total gate width, but for
small Z it is not negligible and VT increases as the width narrows. If each of these three effects is small when considered individually, we can neglect any interaction terms and say that VT’(L,Z,VDS)
= VT - ∆VT(L,VDS) + ∆VT(Z), where the first term on the right is the ideal large-geometry threshold voltage, the middle term subtracts from this some delta due to DIBL and L, and the last term adds
to this some delta due to Z. The values of the ∆VT terms are usually determined semi-empirically for a particular process technology (theoretical treatments can be found in: Y.P. Tsividis, Operation
and Modeling of the MOS Transistor, McGraw-Hill, 1987, chapter 5). The change in VT due to hot electron effects (accumulation of gate oxide trapped charge) can also be included here if the
∆VThot-e(t) is included for some particular time of interest in the transistor’s life.
• Velocity Saturation is modeled by the right-most term in the denominator. When VDS is much less than the velocity saturation voltage (Lεsat), this term reduces to 1 and velocity saturation is
ignored. If VDS approaches Lεsat this term reduces the drain current (i.e. without this term, ID would be over-estimated because saturation of carrier velocity would not be taken into account).
• Mobility Degradation due to the vertical electric field (as discussed earlier) is also modeled in the equation above. This portion of the equation contains empirical parameters that depend on the
transistor design and process technology. θ is an empirical parameter that dictates how much the mobility is reduced by the vertical field (VGS - VT’ ). The empirical parameter θB models the effect of
back bias (substrate bias wrt. the source, VBS) on the mobility; it is small (on the order of 0.01 V-1) and is often omitted -- but doing so gives the erroneous result that the effective mobility increases
with increasing magnitude of VBS (because VT increases with VBS as discussed earlier, reducing the denominator) when, intuitively, the mobility will decrease because the back bias adds to the
vertical electric field strength. (Note: Keep in mind that vertical-field mobility degradation is observed in both large- and small-geometry FETs).
• The term 1+δ is an empirical factor which models the fact that the subgate depletion depth (charge) increases from source to drain, as previously discussed. This is not taken into account in the
Square-Law Theory (upon which the above equation is based), so this term is intended to correct for that. δ → 0 as γ → 0 (i.e. as tOX and NA are reduced), which is the case where the source-to-drain
depletion depth is approximately uniform and the accuracy of the Square-Law model improves (e.g. see previous discussion of Square-Law model vs. Bulk-Charge model). (Note: This applies to
both large- and small-geometry FETs).
Saturation Region
The equation for the saturation region is similar to that for the linear region, but with two key differences:
• Channel Length Modulation is taken into account by the left-most term in the denominator, where ∆L is a function of VDS that must be characterized for a particular transistor design / process
technology (see Tsividis, chapter 5, for a theoretical treatment). As VDS increases in saturation, ∆L becomes a larger fraction of L, hence 1 - ∆L/L decreases and ID increases with VDS, as expected (i.e.
positive ID-VDS slope in saturation). (For a large-geometry MOSFET, ∆L is a tiny fraction of L for any practical VDS, so 1 - ∆L/L ≈ 1 and channel length modulation is ignored.)
• VDS is replaced by VDS(SAT), the transistor saturation voltage (which may be due to channel pinch-off or velocity saturation, as previously discussed - the interested reader is referred to Tsividis,
chapter 5, for additional details). Note that VDS for the VT’ terms is not replaced by VDS(SAT), because DIBL continues even beyond saturation, i.e. the drain field continues to directly influence the
source even for VDS > VDS(SAT).
4 - 86
Appendix: The CMOS Fabrication Process
Isolation
P Well N Well
Si
(a) (b)
N+ Poly-Si P+ Poly-Si Poly-Si Gate Gate Oxide
N+ Source/Drain P+ Source/Drain
(d) (c)
4 - 87
This is a very basic illustration of a highly simplified CMOS process flow, to illustrate how integrated circuits (ICs) are manufactured. This course is not
about silicon processing per se; this material is included as a primer for those with little or no knowledge of standard CMOS fabrication processes, to give
them a basic understanding of how transistors are made, and help them integrate some of the concepts in this module and the next.
(a) Shown in step (a) is a very small portion of the bare silicon start wafer, just big enough for two transistors. There may be millions of transistors on a
single chip (aka. die), and perhaps hundreds of chips on a single silicon wafer (typically 4 - 12 inches in diameter), so this is indeed a tiny volume of the
wafer we are illustrating here. What takes place in these diagrams should be visualized as taking place over the entire wafer surface, fabricating millions of
transistors simultaneously. The start silicon wafer is supplied by a vendor, and the surface typically contains a thin (few microns) layer of P-type epitaxial
silicon (aka. epi) in which the transistors will be built. The crystal structure and doping of the epi are precisely controlled, unlike the bulk of the Si wafer (a
few hundred microns thick) which is mainly for mechanical support.
(b) Isolation trenches are etched in the silicon, defining which areas of the wafer surface will be “active” (i.e. where the transistors will be) and which are
“isolation” (i.e. containing SiO2 to electrically isolate neighboring transistors). This pattern is defined on the wafer surface by a process called
photolithography (in this case, using the isolation photomask), and the trench etch is performed with a plasma etch tool. The trenches are overfilled with
SiO2 by a chemical vapor deposition (CVD) technique, and the SiO2 is then polished back flush with the wafer surface, a process called planarization or
chemical-mechanical polish (CMP). Next, the N-well and P-well regions are doped using a process called ion implantation, whereby the wafer is bombarded
with high-energy dopant ions (e.g. phosphorous or arsenic for N-type, boron for P-type) that become imbedded in the wafer surface. Photolithography is used
to cover the N-well regions with photoresist during the P-well implant, and visa versa. Notice that all of the processes are “blanket” processes, i.e. thin film
depositions, photolithography, etches, ion implants, and planarization are performed globally over the entire surface of the wafer.
(c) Later in the process, the gate oxide is made on the wafer surface by a process called thermal oxidation, which takes place in a diffusion furnace. The
gate oxide is very thin (tOX ~101 - 102 Å) and must be of extremely high quality and purity for good MOSFET performance and reliability. Next, a layer of
poly-Si is deposited on the wafer surface by CVD, and the poly-Si pattern is defined by photolithography (using the poly/gate photomask) and then etched.
This step defines the gate length (L). Notice that the techniques involved in the fabrication process are “subtractive” in nature, i.e. a blanket layer is applied
to the wafer, and then material is removed (subtracted) to leave behind the desired pattern.
(d) The source and drain regions are made by ion implantation (the N-channel devices are covered by photoresist for the P-type source/drain implant, and
visa versa). Notice the self-aligned gate process discussed earlier: the poly-Si gate electrode is doped at the same time the source and drain are doped, and
the poly-Si shields the subgate region from the implant such that the source and drain are “self” aligned to the gate edges. A high-temperature anneal step
typically follows an implant, to heal the damage the implant did to the Si surface, drive (diffuse) the doped regions to the desired depth/dimensions, and
electrically activate the dopant. This may be done in a diffusion furnace, or a rapid thermal anneal (RTA) tool (which rapidly ramps up to and down from
the desired temperature, to minimize the amount of dopant diffusion, allowing for smaller and denser features).
4 - 88
Appendix: The CMOS Fabrication Process (cont.)
Contacts / Vias
(first layer)
Interlayer
Dielectric (ILD)
(e)
Repeat for
subsequent
metal/via layers
Metal
Interconnect
Lines
(first layer)
N-Channel P-Channel
MOSFET MOSFET
(f) 4 - 89
(e) A layer of SiO2 called interlayer dielectric (ILD) is deposited over the wafer surface by CVD and polished/planarized. The contact holes are defined by
photolithography (using the contact photomask) and etched. A metal such as tungsten is deposited over the wafer surface by CVD, filling in the contact
holes. The tungsten is then etched or polished back to leave tungsten only in the contacts.
(f) The first layer of metal interconnect lines (traces) is built next. Historically these metal lines have been made of aluminum, but more modern CMOS
processes use copper instead. For aluminum interconnects, a layer of aluminum is blanket deposited over the wafer surface by a technique called sputtering
or physical vapor deposition (PVD), and the metal lines are then patterned by photolithography (using the metal-1 photomask) and etched. For copper
interconnects, trenches are patterned and etched into the ILD, these trenches are overfilled with electroplated copper, and the copper is then etched or
polished back leaving copper only inside the trenches (metal lines). This technique of filling etched features with metal is called a damascene process; if the
vias and contacts are filled at the same time it is called dual damascene. The trenches must be lined with a copper diffusion barrier such as tantalum to
prevent any copper from reaching and contaminating the transistors. Copper is preferred over aluminum because it has a much lower resistance, and is less
susceptible to electromigration (a phenomenon that can cause voids to develop in the metal lines over time, posing a reliability threat). In a modern IC
fabrication process there are several layers of metal interconnected vertically by vias (the only difference between vias and contacts is that contacts touch the
silicon surface), and these are fabricated by repeating steps (e) and (f) for each layer. A layer called passivation is deposited over the top metal layer,
providing a hermetic seal. The passivation is patterned and etched, and solder bumps are electroplated; these bumps connect the top metal lines to the
traces/balls of the package in the flip-chip or C4 (Controlled Collapsed Chip Connection) assembly process.
To reiterate, this is a highly simplified illustration showing the major milestones in a generic CMOS process. More sophisticated features such as specialized
implants (e.g. tips, VT adjust, etc.), spacers, salicide, adhesion layers, hardmasks and anti-reflective coatings, etc., have been omitted for simplicity. Other
courses address silicon processing in much greater detail.
4 - 90
5
Small But Important
Transistor Circuits
Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham 5-1
This is the last module in a five-module introduction to semiconductor devices. The modules are:
2. The PN Junction
4. The MOSFET
5. Small Circuits
The goal of this module is to present the “big picture” surrounding all this device physics, i.e. to explain why we want to make transistors in the first place,
and how a bunch of “microscopic switches” can be used to make useful chips such as logic gates and memory cells. We will also see how these can be used
to make larger, more sophisticated circuits, like a microprocessor. We will obtain a high-level, big-picture understanding of how a chip is born – from design
to manufacture and test. And we will study the motivations, methodologies, and technical challenges associated with shrinking (scaling) the MOSFET and
advancing the state of semiconductor technology from one generation to the next.

• Explain what CMOS means
• Study a few basic CMOS logic gates: inverter, AND, NAND, OR, NOR
• Illustrate how these basic logic gates can be combined to make larger, more complex circuits
• Understand how semiconductor memory works in general, and build three basic memory cells: SRAM, DRAM, Flash EEPROM
• Provide a high-level overview of how a chip is born – from design and layout to manufacture and test
• Study the methodologies and technical challenges involved in shrinking (scaling) transistors and advancing the state of semiconductor technology
• Provide a brief overview of the history of Intel® microprocessors and Moore’s Law
Looking Back: We are prepared to understand CMOS transistor circuits because we understand how N-channel and P-channel MOSFETs work.
Transistors - So What?
Transistors are used to build:
Logic Memory
+Vcc
+Vcc
b b
A • o
•
o o
B • o
• • • • • • • •
• C
•
•
word line • •
(example: NOR gate) (example: SRAM cell)
(example: Pentium® 4 microprocessor)
Transistors can be used to build logic circuits and memory circuits. Logic circuits manipulate and transform data (bits), performing
logical operations (e.g. comparing pieces of data, encoding and decoding data, etc.) and arithmetic functions (e.g. addition,
multiplication, etc.). Memory circuits store information (bits) for future use. A typical chip will contain both logic and memory.
We will use transistors to build the following logic circuits:

• Inverter
• AND & NAND gates
• OR & NOR gates
• A simple control circuit
• A simple decoder
And we will study the following memory circuits:

• SRAM cell
• DRAM cell
• Flash EEPROM cell
CMOS
Complimentary Metal-Oxide-Semiconductor
B • S • G • D • S • G • D • B •
N+ N+ P+ P+
P N
CMOS stands for Complimentary Metal-Oxide-Semiconductor. When N-Channel and P-Channel MOSFETs are fabricated
together on the same chip, the chip or circuit is called CMOS. The term “complimentary” refers to the fact that N-channel and P-
channel transistors are turned on by opposite polarities of gate voltage.
Note that CMOS processing requires the fabrication of N-type and/or P-type wells (aka. tubs) in the silicon substrate. In an N-well
process, N-type wells are created in a P-type substrate. The P-channel transistors are then fabricated inside these N-well regions,
while the N-channel transistors are fabricated outside the wells in the P-type substrate. In a twin-well or twin-tub CMOS process,
both N-wells and P-wells are created in the substrate. N-channel transistors are then fabricated in the P-wells, and P-channel
transistors in the N-wells.
As we will see later, the complimentary behavior allows CMOS circuits to exhibit much lower power consumption than NMOS
circuits (i.e. all N-Channel transistors) or PMOS circuits (i.e. all P-Channel transistors). For this reason, CMOS circuits are the
technology of choice for most modern, large-scale digital circuits.
Logic Circuits
Transistors can be interconnected into circuits that perform logical operations (such as control circuits) and arithmetic operations
(such as binary mathematics). For example, a microprocessor contains circuitry that performs a wide variety of logical and
mathematical functions. In general, the more transistors a chip contains, the “smarter” it is.
The purpose of this section is to examine a few basic logic circuits for illustration.
CMOS Inverter
logic circuit symbol truth table Vin Vout
+Vcc 0V
+Vcc (logic 1) (logic 0)
•
Vin o Vout
0V
(logic 0)
+Vcc
(logic 1)
o βp
+Vcc +Vcc
• •
Vin • • Vout • •
transistor circuit
• •
βn
• Vout • Vout
• •
• •
Vin Vout
+ Vcc
• Pdynamic = CVcc2ftog = CVcc2KDfclk
•
• •
• S• G• D• •D G • S • •
+Vcc
transfer function
Vout current
N+ N+ P+ P+
P N
0V
Vin
A logic gate is a small number of transistors interconnected to perform some elementary logic operation. There are many different kinds of logic gates, performing various functions. Digital logic
circuits can then be constructed from these basic logic gates. We will look at a few logic gates to understand how they work. The inverter is the simplest logic gate. It takes a bit (a binary digit, i.e.
a 0 or 1) as input, and returns the opposite bit as output. In this sense, it performs the logical “not” function: if the input is a 1, the output is “not 1” or 0 (and visa versa). This functionality is
summarized in the truth table. A logic 1 denotes a high voltage, typically the supply voltage (+Vcc). Logic 0 means a low voltage, such as ground (0 volts). As previously discussed, transistors
behave like microscopic switches in digital electronics. Because transistors are on or off, digital circuits work in binary logic, i.e. the language of 0’s and 1’s. It is important to note that the output
of the inverter does not change instantly in response to a change in the input; because it takes time for the transistors to switch, and for the output terminal (load) to charge/discharge, there is some
“gate delay” or propagation delay through the inverter (typically on the order of picoseconds or nanoseconds, depending on the transistor technology and the circuit details).
CMOS Power Considerations:
Notice that the CMOS inverter consumes power (i.e. draws current) only during the brief transient period while it is switching between logic states (0 ↔ 1). This is the advantage of CMOS circuits
over other types of circuits (e.g. NMOS, TTL, etc.) - very low power. Power can be broken down into two components: static power (power consumed when the circuit is not switching, dc
component) and dynamic power (power consumed due to switching, ac component). Their sum is the total power. In CMOS circuits, static power arises mainly from off-state transistor leakage (e.g.
subthreshold leakage, junction leakage, and gate leakage), and hence increases as the transistor density increases, and of course gets worse for smaller channel lengths as discussed in module 4.
Dynamic power is consumed by switching nodes in the circuit, and arises from two current components: the overlap current and the charge/discharge current. During the act of switching, when
one transistor is in the process of turning off and the other is in the process of turning on, there is a very brief period of time during which both transistors are on and a conductive path exists from Vcc
to ground - the relatively small current that flows from Vcc to ground during this brief transient period is the overlap current. Note also that supply current must be delivered to the output node
(through the P-channel transistor) to charge the node up to Vcc when it makes a 0 → 1 transition. Similarly, charge must be removed from the output node (through the N-channel transistor) to pull it
down to ground when it makes a 1 → 0 transition. This is the charge/discharge current. Typically, the overlap current is negligible compared to the charge/discharge current. Note that it is often
desirable for the transistors to have equal gain (βn = βp) so that the inverter has equal current source and sink capabilities (i.e. equal times for 0 → 1 and 1 → 0 output transitions). This is usually
achieved by making the width (Z) of the P-channel transistor ~2.5 times larger than that of the N-channel transistor (to compensate for the fact that the effective hole mobility is ~2.5 times smaller
than the effective electron mobility.) The βn/βp (i.e Zn/Zp) ratio determines the position of the edge (“cliff”) in the transfer function (higher βn/βp moves it left).
Dynamic power increases with increasing clock frequency (at a higher clock rate there is more switching of logic gates per unit time, and hence more power is consumed). A straightforward circuit
analysis reveals that the dynamic power of a CMOS circuit is given by: P = CVcc2ftog = CVcc2KDfclk, where C is the total output capacitance being driven, Vcc is the supply voltage, and ftog is the toggle
frequency of the node in question, often expressed as some duty (toggle) factor KD times the clock frequency fclk. (E.g. for positive-edge triggered sequential logic, the worst possible case is a logic
node that toggles on every rising clock edge, hence going through a full cycle of its own (e.g. 0 → 1 → 0) every two clock cycles, thus KD = 0.5.) Note that the dynamic power dissipation increases
linearly with clock frequency, duty factor, and capacitance, and quadratically with supply voltage. In high-speed circuits, such as a microprocessor, the dynamic power (at operating clock frequency)
is typically orders of magnitude larger than the static power component.
Low power is important in mobile electronics, because it means increased battery life. It is also important in non-mobile applications because it means the chip runs cooler. The maximum transistor
density and maximum clock frequency of a high-speed circuit are often limited by the ability of a cooling system to remove heat from the chip. Also, charge leaks off dynamic nodes much faster at
higher temperatures, so minimum refresh times (e.g. for DRAM) are limited by thermal considerations as well. Thermal dissipation is an important consideration in chip design and packaging.
* Note the gray backside/well contacts in the transistor circuit. Specifically, note that the backside of the N-channel transistor is strapped to ground, while the backside of the P-channel transistor is
tied to +Vcc (these backside connections are often omitted or “implied” in circuit diagrams). This is why the P-channel transistor is turned on with 0 volts applied to its gate: the voltage drop across
the gate is Vcc and its polarity is such as to cause inversion. (This is equivalent to applying a negative voltage VGS with the backside grounded, as we described the operation of a P-channel MOSFET
earlier.) Note also that the PN junction formed by the wells (underneath the isolation oxide) is reverse biased and thus “self-isolating”.
Introduction to Semiconductor Device Physics / Small Circuits / rev 4.3 Tom Cunningham 5 - 10
CMOS Inverter - Layout
P-channel N-channel
transistor transistor
Vcc
poly-Si (gates) gnd
metal-1
via / contact
P source/drain (aka. diffusion)
N-well
N source/drain (aka. diffusion) source: Principles of CMOS VLSI Design,

Weste & Eshraghian, 1993, AT&T.
This is a circuit layout or cell layout for a CMOS inverter (in an N-well CMOS process). It is a top view, showing the layout of the
various regions and components of this logic gate.
There are design rules governing the layout. Considering poly-Si for example, there are design rules specifying the minimum poly
line width, minimum pitch (spacing) between poly lines, minimum poly-to-contact distance, etc. The design rules come from the
capabilities of the CMOS fabrication process, for example the critical dimension (CD) that can be resolved by the lithography and
etch processes, the tolerance in aligning one litho layer to another, the thermal budget and the amount of lateral diffusion that takes
place in the doped (implanted) regions, etc.
Aside: Latchup
source: Principles of CMOS VLSI Design,

We referred to the phenomenon of latchup in earlier modules.
Note that there are two parasitic Bipolar Junction Transistors (BJTs) inherent in the CMOS structure: a vertical PNP BJT formed by the P+ drain, N-well, and
P-type substrate, and a horizontal NPN BJT formed by the N+ source, P-type substrate, and N-well.
We have discussed the BJT only briefly, in the exercise at the end of the PN junction module. Therefore, the physics of latchup will not be discussed in
detail here. Rather, we will have a more general description.
Various non-idealities can trigger latchup in a CMOS circuit, such as noise, leakage current, transient current/voltage spikes, or radiation. Such an event can
cause one of the parasitic BJTs to turn on (i.e. the emitter-base junction becomes forward biased). These BJTs are arranged such that when one turns on it is
likely to turn the other one on. The parasitic circuit can operate with a gain > 1, meaning that the BJTs feed one another in a positive feedback loop. This
results in a large parasitic current, effectively shorting the supply voltage (VDD in this diagram) and ground (VSS). Typically, this latchup current causes the
device to self-destruct (the circuitry can not handle such a large sustained current). At the very least, it causes the circuit to become inoperable and “freeze”
(hence the name “latchup”), requiring that it be powered down and reset. Due to the high substrate currents that accompany latchup, it is often the case that
latchup in one CMOS transistor pair will spread to neighboring transistors, causing them to latchup as well.
Latchup Prevention: Latchup was an obstacle to the early adoption of CMOS technology. Modern circuit design/layout and silicon processing techniques
make circuits much less susceptible to latchup. To avoid latchup, it is desirable to reduce the gain of the parasitic BJTs. One popular technique is to use
silicon start wafers with an epitaxial (epi) layer on top of a heavily-doped substrate. This reduces Rsubstrate which reduces the gain and also provides a shunt
path for collector current of the PNP BJT. Another popular technique (which can be combined with the previous one) is to use retrograde wells – i.e. the
doping concentration at the bottom of the well is higher, reducing Rsubstrate, while the surface of the well is more lightly doped to preserve good MOSFET
characteristics. There are also some very effective layout techniques for combating latchup, such as the copious use of substrate/well contacts; placing VSS
contacts close to N+ source regions (to reduce Rsubstrate) and VDD contacts close to P+ source regions (to reduce Rwell); and the fabrication of guard rings in
I/O structures, where latchup is most likely to occur (guard rings act as “dummy collectors” and reduce the gain of the parasitic BJTs).
CMOS AND & NAND Gates
AND Gate
inputs output
logic 1 = + Vcc
A A B C
logic 0 = 0 volts
C 1 1 1
B
1 0 0
C = A and B = A • B 0 1 0
0 0 0
+Vcc
NAND Gate
•
A
A
o C = B
o C
B
o o
C = not (A and B) = A • B
• C
inputs output A •
A B C
1 1 0
1 0 1
B •
0 1 1
0 0 1
Transistors can be interconnected to make AND and NAND (“Not AND”) logic gates. (We will use 2-input gates for example, but
these principles can be extended to gates with more inputs.)
An AND gate returns a logic 1 only when all of its inputs (in this case A and B) are logic 1; otherwise, its output is logic 0. Thus,
the output bit can be calculated by multiplying the two input bits, as shown in the equation and the truth table. Another way to
look at it is in Boolean terms, where each input is evaluated as true (1) or false (0), and the output is true only when A and B are
true. This is the origin of the term “truth table”.
The NAND gate, as the name implies, always returns the opposite (compliment) of what an AND gate produces. This can be
observed by comparing the two truth tables. The bar in the equation means to take the compliment of the expression underneath.
The transistor circuit for a NAND gate is shown. By treating the transistors as switches, similar to the inverter example discussed
previously, we can see how this circuit generates the output shown in the truth table.
Again, note that this CMOS circuit conducts current between Vcc and ground only during the brief transient period while it is
switching, and thus consumes very little power.
CMOS NAND Gate – Layout
Vcc P-channel
transistors
B
A C
(out)
poly-Si (gates)
N-channel
metal-1 transistors
via / contact
P source/drain (aka. diffusion) gnd
N source/drain (aka. diffusion)
source: Introduction to VLSI Design,

Eugene D. Fabricius. McGraw-Hill, 1990.
This is a cell layout for a two-input CMOS NAND gate.
The color scheme has changed slightly from that used previously for the inverter layout, because this cell was created by a
different layout tool. Also, the MOSFET and contact regions are highlighted, making them easier to identify.
CMOS OR & NOR Gates
OR Gate
inputs output
A A B C
C 1 1 1
B
1 0 1
0 1 1
C = A or B = A + B
0 0 0
NOR Gate +Vcc
A
A
o C = B
o C A • o
B
C = not (A or B) = A + B
B • o
inputs output
A B C
• C
1 1 0
1 0 0
0 1 0
0 0 1 •
Transistors can be interconnected to make OR and NOR (“Not OR”) logic gates.
An OR gate outputs a 1 whenever one or more of its inputs is 1. In this case, the output is 1 when A or B is 1. In Boolean terms,
the output is true (1) when one or both of the inputs, A or B, is true.
The NOR gate, as the name implies, produces output that is opposite (complimentary) to the OR gate. The transistor circuit for a
NOR gate is shown for example.
CMOS NOR Gate - Layout
poly-Si (gates)
metal-1
via / contact
source: Introduction to VLSI Design,

Eugene D. Fabricius. McGraw-Hill, 1990.
NOR gate layout.
Exercise: 3-Input NAND Gate
1. Draw the truth table for a 3-input NAND gate.
2. Draw the circuit symbol.
3. Draw the transistor-level circuit for a 3-input CMOS NAND gate. Hint: You will need three N-channel
transistors and three P-channel transistors.
Exercise
Exercise: 3-Input NAND Gate - Solution
+Vcc
A B C Y
•
0 0 0 1
0 0 1 1
o o o
0 1 0 1
0 1 1 1
1 0 0 1
• Y
1 0 1 1 A •
1 1 0 1
1 1 1 0
B •
A
o
B Y
C C •
Solution
Example: A Simple Control Circuit
Burglar alarm for a room with one window and one door
signal from contact sensor

on window frame
window is
closed ? o signal to an alarm
horn or bell
sound the
alarm ?
door is
closed ? o
signal from contact
sensor on door frame
signal from a keypad

alarm control panel
system is
armed ?
Other types of basic logic gates exist, besides the five we have studied here (inverter, AND, NAND, OR, NOR); we will not
attempt to study them all. Our purpose here is simply to illustrate that transistors can be interconnected to make useful circuits,
such as the simple control circuit shown here. It controls a burglar alarm for a room with one window and one door.
The system has three inputs. When an input is “true” or “yes”, it is a assigned a value of logic 1. When it is “false” or “no”, it is
logic 0.
When the alarm is armed (alarm system is armed? = yes = 1) and both the window and door are closed (window is closed? = door
is closed? = yes = 1), both AND gates produce output of 0 and hence the OR gate has output 0 and the alarm is not sounding
(sound the alarm? = 0 = no).
If either the window or the door (or both) is opened while the alarm is armed, one (or both) of the AND gates will produce an
output of 1. This will cause the OR gate to produce output of 1, triggering the alarm.
This is certainly not the best burglar alarm in the world! But it illustrates how the basic logic gates we have studied in this module
can be used to create digital circuits that perform logical operations.
Note that any arithmetic operation is essentially a sequence of logic operations, hence logic circuits can be constructed to perform
mathematical calculations as well. Of course, a digital circuit will perform all of these calculations in binary (0’s and 1’s). Any
base-10 number can be represented as a binary number, including negative numbers and fractions. And any mathematical
operation can be performed on these binary numbers (e.g. addition, subtraction, multiplication, division, etc.).
Exercise: A Decoder
Using inverters and AND gates, construct a 2-bit decoder. The circuit has two 1-bit input lines and four 1-bit
output lines. For a given combination of inputs, one (and only one) output line will be selected (logic 1) as
indicated in the truth table below.
inputs outputs
A0 A1 W0 W1 W2 W3
W0
0 0 1 0 0 0
A0 W1
decoder 0 1 0 1 0 0
A1 W2
W3 1 0 0 0 1 0
1 1 0 0 0 1
This example will come in handy later when we discuss semiconductor memory.
(Aside: If you know how to count in binary, you will recognize this as a 2-bit binary-to-decimal decoder.)
Exercise: A Decoder - Solution
A0 A1
• •
o o
• W0
•
• W1
•
• W2
•
• W3
•
Note that this can easily be extended to handle more than two inputs. For example, for three inputs (A0 – A2), we would use three
inverters along with 23 = 8 AND gates, to decode all 23 = 8 possible combinations of the three inputs. Later, when we discuss
semiconductor memory, we will see an example of an 8-bit memory address decoder, which can decode an 8-bit memory address
and select one of 28 = 256 unique word lines (memory addresses).
Levels of Abstraction
functional blocks/units/modules
sub-blocks
reg
decoder
ALU reg
reg
MUX
logic gates
transistor
•
circuits
o o
•
•
The simple control circuit for our burglar alarm is very small and easy to design. But what about much larger, more complex circuits, like a microprocessor
containing millions of gates?
To make a large, complex circuit like a microprocessor, the circuit must be broken down into smaller blocks and sub-blocks, each of which can be designed
by an individual or small team; these blocks are then reassembled to form the whole chip. CAD (Computer Aided Design) tools make the design process
more efficient and robust.
There are different levels of abstraction when thinking about a circuit. The top level might be the entire system, e.g. the motherboard of a PC, containing
many chips on a printed circuit board (not represented in the diagram). The next level of abstraction might be an individual chip, e.g. the microprocessor.
The chip is divided into smaller functional blocks (aka. units or modules), some of which are logic circuits and some of which are memory circuits
(discussed later). Examples of logic units on a typical microprocessor are things like the instruction fetch unit, the instruction decode unit, the integer
unit/pipeline (performs mathematical operations on integers), the floating-point unit/pipeline (performs mathematical operations on decimal numbers), the
branch prediction unit (handles program flow control), etc. Examples of memory units would include things like the caches (local on-chip memory banks)
and the register files (banks of dedicated and/or general-purpose registers). There are some analog units as well, such as the I/O (input/output) units (which
transport instructions/data to and from the chip) and the clock unit (which controls the clock signals for the chip).
Each of these functional units can be further deconstructed into a circuit of still lower-level elements. Logic units can be deconstructed into lower-level
elements like multiplexers (MUX), adders, registers, counters, Arithmetic Logic Units (ALU), decoders, etc. Each of these, in turn, is made up of basic
logic gates such as inverters, NAND gates, NOR gates, etc. And as we have already seen, each of these gates has a corresponding transistor-level circuit.
Large and complex circuits must be approached with this hierarchy of abstraction in mind. As we ascend the hierarchy, a kind of “information hiding”
takes place, so that the design can be understood in progressively more general terms – more scope, less detail. Conversely, as we descend the hierarchy,
we have less scope but more technical detail. It is important to work at the right level of abstraction for the task at hand. It is also important to manage the
design project with this hierarchy in mind.
The Big Picture: How A Chip Is Born
or
cell set / custom +Vcc
d
logic design
ven
circuit design
•
o A o
Si
m
B • o
f ro
start Si
• C
chip
Process Flow
•
layout
Fab
finished wafer
E-Test transistor
Sort
ab
F
to Assembly
to mask shop Class Test
packaged
chip
photomask set
We are now in a good position to step back and view the big picture of how chips are born.
Design: As described previously, a very large circuit is typically broken up into smaller blocks and sub-blocks, each of which can be designed by an individual or small team, and these blocks are
then reassembled to form the whole chip. There are three basic approaches to IC design: ASIC, full-custom, and semi-custom. In the ASIC (Application-Specific IC) design methodology, design
engineers use computer-based design tools to create a gate-level logic circuit schematic (or equivalent description, e.g. a netlist) for the circuit to be built, like the schematic for our burglar alarm
control circuit. This gate-level circuit will later be translated into a transistor-level circuit during Layout (see below). In a full-custom design, engineers use computer-based tools to design the
circuit directly at the transistor level, rather than the logic gate level (i.e. no gate-to-transistor translation required). It is possible to gain better IC performance in this manner, but the trade-off is an
increase in design resources and design time. Also note that any analog circuits on the chip (e.g. I/O circuits) are custom designs. The semi-custom design strategy balances the performance vs.
design time/resources trade-off, by designing some parts of the circuit at the gate level (ASIC) and the more performance-critical parts at the transistor level (custom).
Verification: The circuit is simulated to verify that it meets functionality requirements and performance goals (speed, power, etc). To perform the functional verification, binary test vectors (aka.
test patterns) are applied to the input pins in the design simulation, and the output vectors/patterns are compared to the expected results. Timing analysis tools verify that the circuit meets all
setup/hold times, and help to identify the critical speed paths (bottlenecks) in the circuit. Reliability verification tools examine the circuit’s susceptibility to effects such as hot electrons,
electromigration, etc.
Layout: For an ASIC design, the gate-level schematic is laid out at the transistor-level using the cell library for the target CMOS process. Cells are placed in the layout which correspond to the
gates in the schematic. They are then interconnected with metal routing corresponding to the wires in the schematic. In this manner, the gate-level circuit schematic is translated into a transistor-
level circuit laid out for silicon. For a full-custom design, or the custom portions of a semi-custom design, there is no gate-to-transistor translation required, so the transistor circuit can be laid out
directly. In any case, computer-based layout tools help to automate the process and optimize the layout. Layout vs. Schematic (LVS) checks are performed to ensure that the layout corresponds
exactly to the circuit schematic. Design Rule Check (DRC) is performed to ensure that the circuit adheres to the design rules for the target CMOS technology. Parasitic extraction tools examine the
resistances and capacitances in the layout and calculate the associated delays in the circuitry; these are then fed back to the design engineers for further verification of the circuit timings, etc. The
design-layout cycle is typically iterated several times before the chip meets all requirements.
Photomasks: The layout database is then “fractured” into layers so that a set of photomasks can be manufactured. For example, all poly-Si in the layout is captured for the poly mask, all metal-1
for the metal-1 mask, all N-well for the N-well mask, all contacts for the contact mask, etc. There is one mask for each layer. A photomask consists of a glass or quartz plate with a chrome pattern
on its surface. For the metal-1 mask, for example, this chrome pattern is a replica of the metal-1 pattern in the layout database. (Other courses are available to explain the photomask manufacturing
process.)
Fab, E-Test, and Sort: The mask set is then delivered to the Fab, where it will be used to manufacture the chips on silicon wafers. The fab is a cleanroom manufacturing environment, to minimize
particulate defects which can jeopardize the yield and reliability of the chips. During the fabrication process, a technology called photolithography is used to transfer the mask pattern onto the wafer.
The masks are applied to the wafer sequentially in a layer-upon-layer sequence to build the chips. (Other courses are available to explain the fabrication process in detail.) The end result is a wafer
containing many chips, as shown above. The wafer is then sent to E-Test, where test structures in the scribelines (i.e. the dicing lanes between chips) are tested to evaluate the integrity of the
fabrication process. These test structures consist of discrete transistors, PN junction diodes, and MOS capacitors in various shapes and sizes; test structures for metal lines and contacts/vias; and
other structures. Parameters such as threshold voltage, effective channel length, drive current, subthreshold leakage current, junction breakdown voltage, and metal/contact/via resistances are
measured. E-Test data provides valuable insight into the fabrication process itself, and the yield, performance, and reliability of the chips. After E-Test, the wafers are sent to Sort, where the chips
themselves are probed to test their functionality, speed, and parametrics. For functional testing, the test hardware feeds the chip the same input test vectors/patterns that the designers used to
simulate the chip. Any chips that do not meet functionality or performance requirements are identified in the Sort database.
Assembly, Burn-In, and Class Test: The chips are cut (diced) from the wafers, and all functional chips (as identified at Sort) are mounted into ceramic or plastic packages; this process is called
packaging or assembly. The package protects the chip from the environment, and contains metal pins/balls which carry signals between the chip and the outside world. Some or all of the chips
may undergo high-temperature, high-voltage stress testing to ensure good reliability; this is called Burn-In. Class test is the final test for the packaged chips, and uses a test program similar to that
used at Sort. Class testing is usually performed under the worst-case operating conditions of the chip’s spec (e.g. maximum temperature and minimum supply voltage).
Validation: When a new chip is manufactured for the first time, prototype samples are evaluated in system-level or board-level testing. The goal is to identify any bugs or marginalities in the chip
in its application environment. Critical speed paths (bottlenecks) may also be identified. This information is fed back to design for improvement, which will typically necessitate circuit
modifications and hence some new photomasks. Several design-manufacture-test-validate cycles may be required before a chip is customer worthy.
This is how a chip gets from design to silicon. This is meant to be a big-picture overview; each of these topics could be discussed in much greater detail.
Memory
Transistors can also be interconnected to form circuits that store bits. In this section, we will study three types of memory:
DRAM, SRAM, and Flash EEPROM. Each of these is widely used in a variety of microelectronic devices, including personal
computers and mobile / handheld devices.
Memory Storage & Access – The Big Picture
address lines word lines (256) memory array
(8-bit address = 28 = 256 unique addresses) (each cell stores 1 bit)
data / bit lines
W0
• • • • • • • •
A0 BIT BIT BIT BIT BIT BIT BIT BIT
• CELL • CELL • CELL • CELL • CELL • CELL • CELL • CELL
Address Decoder
A1 W1
A2 • • • • • • • •
A3 BIT BIT BIT BIT BIT BIT BIT BIT
• CELL • CELL • CELL • CELL • CELL • CELL • CELL • CELL
A4
A5
A6
A7 W255
• • • • • • • •
• 0 • 0 • 0 • 1 • 0 • 0 • 1 • 1
this address (word

line) is selected b7 b6 b5 b4 b3 b2 b1 b0
these cells are read Sense/Write Sense/Write Sense/Write Sense/Write Sense/Write Sense/Write Sense/Write Sense/Write
from / written to (in R/W
parallel)
0 0 0 1 0 0 1 1
I/O data lines
(8 bits = 1 byte) read / write sense
amp circuitry
In addition to logic, transistors can also be used to make memory. Logic manipulates and transforms data, whereas memory stores data for future use. Each
plays a vital role in modern microelectronics; for example, a microprocessor contains large amounts of both.
Before discussing different types of memory, let’s understand how a semiconductor memory works in general. We will use the simple memory scheme
shown here for illustration.
A memory is an array of memory cells, each of which stores one bit. Each cell is a transistor circuit. (Later, we will study three memory cells: the DRAM
cell, the SRAM cell, and the Flash EEPROM cell.)
Reading a byte from memory:
A binary address is placed on the address lines; in this example, an 8-bit address is used and hence there are 8 address lines A0 – A7 . The address decoder is
an 8-bit decoder (analogous to the 2-bit decoder we designed earlier as an exercise). It accepts the binary address as input and selects the appropriate output
line or word line. Note that, with 8 bits (one byte), it is possible to specify 28 = 256 unique addresses (i.e. 256 word lines).
A voltage is placed on the selected word line, thus accessing each cell in that line simultaneously. In this example, there are 8 cells on each word line. Each
cell then places the bit it is storing (a 0 or 1) on its bit line (aka. data line). A sense amp (a.k.a. read/write circuit) is used to sense and amplify the bit so it
can be used by the outside world. Note that all 8 bits are read out simultaneously, as one byte (a.k.a. one “word”). Note also that the bit lines are shared
among word lines, but only one word line will be active at any given time, and only those cells will use the bit lines.
Storing (writing) a byte into memory:
The byte to be stored is placed on the bit lines. These bits are sensed and amplified by the sense amps. The address to which the byte should be stored is
placed on the address lines, and the address decoder selects the corresponding word line. This activates the memory cells on that word line (only), and they
accept and store the bits present on the bit lines.
How the cell stores a bit will be explained next; it depends on what kind of cell is being used. We will study three types of memory cells: a DRAM cell, an
SRAM cell, and a Flash EEPROM cell.
DRAM Cell
word line word line
• •
• access • • •
transistor storage access
storage
transistor
bit line
capacitor
bit line
capacitor
• • • • • • • •
• • • • • • • •
• • • • • • • •
• • • • • • • •
this row
address
is selected
• • • • • • • •
• • • • • • • •
no no no no no
charge charge charge
charge charge charge charge charge
this byte
is read or
written
0 0 0 1 0 0 1 1
First we will study DRAM, or Dynamic Random Access Memory. “Dynamic” refers to the fact that DRAM memory must be periodically “refreshed” or it
will lose the data it is storing. “Random access” refers to the fact that the word lines do not have to be accessed in any particular order; any byte or “word”
can be independently accessed when needed by supplying its address.
DRAM is used in personal computers as the Main Memory, storing the operating system, programs, and other important information.
The basic DRAM cell is quite simple, consisting of an access transistor and a storage capacitor. The capacitor stores the bit (charged = 1, no charge = 0).
Reading from DRAM: Notice that the transistor gates are connected to the word line (N-channel transistors are used here). The address from which data is
to be read is placed on the address lines, causing the address decoder to activate the appropriate word line. The transistors in the selected word line are
turned on (i.e. the switches are closed), and the storage capacitors are electrically connected to their respective bit lines. If there is charge on the capacitor, it
will be sensed on the bit line and amplified by the sense amp circuit; this will be interpreted as a the cell storing a 1. If there is no charge on the capacitor, the
sense amp circuitry will interpret this as storing a 0.
Storing (writing) into DRAM: The byte to be stored is placed on the bit lines. The address into which this byte is to be stored is placed on the address
lines, which causes the address decoder to activate the corresponding word line. This turns on the access transistors in this line, thus connecting the storage
capacitors to their respective bit lines. If there is charge on a bit line (i.e. an input bit of 1), it will charge the capacitor. The capacitor retains the charge
when the word line is deactivated, thus storing the 1. If there is no charge on the bit line (i.e. an input bit of 0), the capacitor will not be charged (or will be
discharged), and thus stores the 0. Note that, for a non-ideal capacitor, stored charge will leak away over time. A typical storage capacitor can retain its
charge for about 10 milliseconds. Therefore, each word line must be “refreshed” (i.e. the bits are read and then re-written) every few milliseconds to prevent
the data from being lost.
Note that DRAM is volatile memory, meaning that it stores its data (bits) as long as supply power is provided. If supply power is disconnected from the
DRAM, the data is lost.
DRAM Cell – Trench Capacitor
source gate
(bit line) (word line) plate bias
• • •
ILD
N+ N+
MOS
capacitor Planar Capacitor
source gate
(bit line) (word line) plate bias
• • •
ILD
N+ N+ poly-Si
Trench Capacitor trench oxide
MOS
capacitor
A popular design of the DRAM cell uses a trench capacitor. A deep, narrow trench is etched into the silicon. The sidewalls of this
trench are oxidized (forming the dielectric for the capacitor) and then the trench is filled with poly-Si to form the other “plate” of
the capacitor.
The primary advantage of this design is that it uses less silicon surface area than the planar capacitor. This allows for a denser
DRAM, storing more bits per unit area. This means the DRAM chip can be smaller (more die per wafer), for improved yield and
lower manufacturing cost. The main tradeoff is manufacturing complexity – there can be many technical challenges in the trench
fabrication module, especially as the trend continues toward narrower and deeper trenches (higher aspect ratio) and more stringent
charge storage requirements.
Aside – Some Technical Details: In a real DRAM cell, the “plate bias” is usually held at some positive supply voltage (VDD),
contrary to the previous schematic in which it is shown going to ground. This biases the capacitor into inversion; i.e. a depletion
region exists in the substrate and an inversion layer of electrons is present at the oxide interface. Whether the capacitor stores a 0
or a 1 is then determined by the sense amp circuitry according to whether (and how much) charge flows into or out of the storage
capacitor when it is accessed. This level of technical detail is beyond the scope of this course; our purpose here is simply to
demonstrate that a DRAM cell stores a bit in the form of charge on a storage capacitor, and that different strategies exist for
capacitor fabrication (e.g. planar vs. trench).
SRAM Cell
+Vcc
b b’
• inverter
inverter
access access
transistor o o transistor
• • • • • • • •
bit
line
word line • •
b b’ b b’
1 1 0 0
• o 0 o0 • • o 1 o1 •
storing a 1 storing a 0
SRAM stands for Static Random Access Memory. “Static” refers to the fact that the memory does not have to be periodically refreshed like DRAM does; the
SRAM cell will store the bit without refreshing.
The SRAM cell consists of two cross-coupled inverters; i.e. the output of one is the input of the other, in a static feedback loop. The SRAM cell is sometimes
referred to as a “bi-stable” memory element, meaning that it has two static or stable states, corresponding to the storage of a 0 or a 1 as shown. It is a
“regenerative” circuit, because the internal connections to power and ground ensure that the stored bit remains a “strong” 1 or 0 (i.e. the voltage level
accessible to the bit line is held at full-scale Vcc or ground and does not weaken or drift over time). This is why the SRAM cell does not require periodic
refreshing like the DRAM cell does.
It does, however, require supply power - SRAM, like DRAM, is volatile memory. If the supply power is removed, the regenerative feedback will stop and
the data will be lost.
There are two access transistors, which act like switches connecting the cross-coupled inverter pair to the bit line b and also to a “not bit” line b’ (which is
always the opposite, or compliment, of b). When the word line is activated, the two access transistors are turned on (switches closed), and the value stored
by the inverter pair is accessible to the bit lines. Sense amps (not shown here) then read these signals and present them to the outside world.
This 6-transistor design is known as the “6T” SRAM cell. It is very popular, due mostly to its storage stability, but other SRAM cell designs exist as well.
All of them involve some sort of static, regenerative feedback.
The primary advantage of SRAM over DRAM is speed - data can be retrieved from SRAM much faster than from DRAM in general, because it is easier to
read the bit value stored in an SRAM cell than it is to read the small charge stored on a DRAM capacitor, and because DRAM read/write operations must be
intermixed with the continuous refresh operations.
The main advantage of DRAM is its smaller cell size - one transistor and a trench capacitor, vs. the six transistors required for an SRAM cell. Therefore,
much higher density can be achieved with DRAM, and hence much lower cost per byte.
Therefore, SRAM tends to be used for fast (and expensive) memories with smaller storage capacity, such as the cache in a microprocessor. DRAM tends to
be used for slower (and much cheaper) memories with much greater storage volume, like the main memory of a PC.
SRAM Cell - Layout
inverter
inverter
poly-Si (gates)
metal-1
access
via / contact
transistors
N-well
source: Principles of CMOS VLSI Design,

Layout for a “6T” (6-Transistor) SRAM cell (in an N-well CMOS process). (The supply voltage in this diagram is called VDD and
ground is called Vss .)
Flash EEPROM Cell
Vt
Program Erase Read
Gate (V) 12 -10 5
0 Level 1
Source (V) 0 5 0
Drain (V) 5 Float 1
1 Level 0
Conventional
Flash Cell
Vt
00 Level 3
01 Level 2
10 Level 1
11 Level 0
StrataFlashTM
Cell (2 bit/cell)
EEPROM stands for “Electrically-Erasable Programmable Read-Only Memory”. “Read Only” is misleading - EEPROM can be programmed (i.e. written to)
and re-programmed (i.e. erased and re-written) as needed; however, it can not be programmed as fast as SRAM or DRAM, and is intended for applications
that require less frequent re-programming / writing. “Electrically-Erasable” means that voltage can be applied to erase the memory (whereas early EPROM
chips were erased by exposing them to heat and UV light, which was very slow and inconvenient). “Flash” refers to an EEPROM device structure that
allows the cell to be read, programmed, and erased much faster than earlier EEPROM cells.
Note that the cell is based on the MOSFET device structure, but has two poly-Si layers in the gate. The thin “tunnel oxide” is basically the gate oxide we
discussed previously. The ONO (oxide-nitride-oxide) is new to us, and is there to facilitate the trapping and storage of charge on the floating poly-1 gate.
Programming the Flash Cell: A high voltage is applied to the gate. A circuit called the Write State Machine (WSM) (not shown) pulses the drain voltage.
Channel Hot Electron (CHE) injection takes place, trapping electrons in the poly-1 gate (floating gate). This increases the threshold voltage (VT), which in
turn will decrease the drive current, ID(SAT). A logic bit 0 has been programmed/written/stored in the cell. A good Flash cell will hold this charge almost
indefinitely (i.e. a miniscule amount of charge leakage). Hence, Flash EEPROM memory is non-volatile, i.e. it retains its data without supply power. This is
useful for mobile and handheld electronic devices.
Reading the Flash Cell: The word line selects a row of cells, applying voltage to their gates. The applied drain voltage biases the transistor-like cells into
saturation, and each cell’s ID(SAT) is present on its bit line. Sense amp circuitry (not shown) compares the ID(SAT) of each cell to a reference cell to
determine the bit (0 or 1) stored in each cell. Note that reading a cell does not erase or alter its data (i.e. does not disturb the trapped charge).
Erasing the Flash Cell: A large negative voltage is applied to the gate of all cells to be erased (usually an entire “block”). The WSM pulses a positive
voltage onto the source lines, causing trapped electrons in the poly-1 gate to tunnel through the tunnel (gate) oxide and into the source. The WSM uses a
reference cell to determine when the cells have been fully discharged (i.e. all are logic bit 1).
Note that the Flash cells are always N-channel devices; the higher mobility of electrons (vs. holes) is conducive to CHE injection. However, while the Flash
memory cell array is NMOS, the periphery of the chip is CMOS. The periphery contains the logic, such as the WSM, the sense amp circuitry, the I/O, etc.
A word about Intel StrataFlashTM memory: StrataFlashTM memory stores multiple bits per cell. The basic structure and operation of the cell does not
change, except that the StrataFlashTM cell exploits the analog nature of charge storage to enable multiple VT levels, thus storing multiple bits. For example,
by using four VT voltage levels, each cell can store two bits of information. The advantage is increased memory density and lower cost per bit.
Aside: The Memory Hierarchy of a PC
closer to processor
r
internal to the microprocessor, made from basic logic
we
gates (flip-flops), contains data the processor is
ive
slo registers
currently using (e.g. operands for a calculation)
ns
er,
pe cache
ap
SRAM, internal to the microprocessor, contains

ex
he
L0 data/instructions the processor thinks it will

ore
,c
L1 need again soon

ser
,m
L2
en
ter
,d
DRAM, external to the processor but on the motherboard,

fas
ity
Main Memory contains data/instructions for operating system and

y,
ac
programs that are running

cit
ap
pa
c
not semiconductor memory (magnetic storage), not

ca
er
volatile, external to the motherboard, permanently

g
Hard Drive
er
lar
stores the operating system, programs, files, etc.

all
sm
not semiconductor memory (magnetic or

External Memory optical storage), not volatile, portable,
(Tape, Floppy Disk, Diskette, CD, etc.) external to the PC
farther from processor
This is a good place to look at the memory hierarchy of a personal computer (PC). As we ascend the hierarchy, we encounter smaller, faster, more expensive memories that are closer to the
microprocessor, aka. central processing unit (CPU). As we descend the hierarchy, the memories become bigger (greater storage capacity), denser (more storage cells per unit area), cheaper (per
byte), and slower (longer access time/latency).
Registers are the smallest and fastest form of memory. They are inside the microprocessor, and store data the processor is currently using (e.g. operands for a calculation). Typically, there are a
handful of general-purpose registers (as well as some dedicated registers not accessible to the programmer) inside a microprocessor.
A cache memory is a small SRAM inside the microprocessor (though L2 or L3 cache may be found outside the processor on the host bus in some systems). Cache stores instructions/data the
processor thinks it will need again soon (how this is determined depends on the cache architecture). As discussed previously, SRAM is very fast memory, but expensive (in terms of silicon real
estate). An L0 cache is smaller, faster, and closer to the processor than L1 cache. L1 is smaller, faster, and closer than L2. And so on. If the processor needs an instruction or some data, it will first
search L0 and then L1 and then L2 and so on. If it can not find the instruction/data in cache, it will then access the Main Memory, discussed next. The number of cache levels is determined by the
processor architecture, based on tradeoffs involving performance (speed) and cost (silicon real state and hardware complexity). Remember that cache is fast, but very small – for example, the
Pentium® III (Coppermine) processor uses a 256 kb (kilobit) on-die L2 cache.
The Main Memory is DRAM, and is contained in SIMM’s (Single In-Line Memory Modules) or DIMM’s (Dual In-Line Memory Modules) on the PC motherboard. Because DRAM is very dense
and cheap, the Main Memory has a much higher storage capacity than cache – for example, modern PC’s have 128 – 256 MB (megabytes) of Main Memory. The trade-off is that it is slower to
access. If the requested instruction/data is found in the cache (called a “cache hit”), it can typically be retrieved in one clock cycle, whereas it might take many more cycles to retrieve it from Main
Memory (on a “ cache miss”). This is why cache is used: if the processor can keep the most often used data in the nearby cache, it will spend less time accessing Main Memory, and the overall
performance of the system will be much better. It should also be noted that advancements continue to be made in DRAM architecture to combat the Main Memory bottleneck, such as DDR-DRAM
(Double Data Rate DRAM) and Rambus RDRAM – these technologies are focused on reducing memory access latency (the overhead delay in accessing data) and/or increasing memory bandwidth
(bytes or words per second).
The Hard Drive is external to the motherboard but inside the PC. It is not semiconductor memory, but rather magnetic storage (and hence non-volatile). The hard drive has far greater storage
capacity than the Main Memory – 30 GB (gigabytes) or more is common in modern PC’s. But again the trade-off is speed: if the processor has to access data on the Hard Drive and load it into Main
Memory, this can take hundreds or thousands of clock cycles. The bottom of the hierarchy is External Memory such as diskettes and CD’s, which are portable memory devices that are not a
permanent part of the PC. These devices are not semiconductor memory, but rather magnetic (tape or disk) or optical (CD) storage. These devices are convenient and have large storage capacity,
but it takes the CPU a very long time to access data on them.
Why the hierarchy? The ideal memory would have enormous storage capacity, very fast data retrieval (low latency and high bandwidth), and low cost (small silicon real estate). The question
arises: why not just build huge register banks, and do away with the rest of the hierarchy? The answer: not only would this be prohibitively large in silicon area (i.e. expensive, unmanufacturable),
but it wouldn’t work – the more hardware (gates and wire) we add to a register bank (and the accompanying access circuitry such as the decoder, etc.), the slower it becomes. A similar argument
holds for cache vs. Main Memory: it is not practical to make an SRAM the size of a DRAM Main Memory – not only is it prohibitively expensive, but the memory would be slowed down too much
by its sheer size. Hence, the memory hierarchy is devised to present the processor with as close to an ideal memory as possible: large storage capacity (provided by the Main Memory) and fast
access (because of the high cache hit rate) at a reasonable cost. Obviously, the cache architecture (number of cache levels, cache sizes, cache storage/retrieval algorithms, etc.) has a pronounced
influence on the performance of the PC – the goal is to maximize cache capacity, hit rate, and bandwidth while minimizing cache latency. Minimizing the latency and maximizing the bandwidth of
Main Memory is also very important, hence the development of DDR-DRAM, Rambus RDRAM, and other technologies.
* Flash memory is also used in the PC, though it doesn’t really fit into the context of the memory hierarchy discussed above. A Flash chip (card) is often used to store the BIOS (Basic Input/Output
System) and other primitive data that the PC needs in order to boot-up. When the PC is turned on, it begins booting-up from the ROM BIOS, until it reaches a point where it can activate the hard
drive and load the operating system followed by other programs (applications). Thus, the Flash ROM holds the seed information the PC needs at start-up. It is ideal for this application because (1)
it is non-volatile memory (i.e. retains its data even when the power is turned off), and (2) the contents of the ROM are set at the time the PC is manufactured and are rarely changed (i.e. do not often
write/reprogram the ROM, sometimes referred to as “firmware” for this reason). Also, as mentioned previously, Flash ROM finds widespread use in portable electronic devices such as mobile
phones and PDAs.
Transistor Scaling
&
Technology Trends
We have discussed how MOSFETs can be used to build logic and memory circuits, and some of the important circuit performance
characteristics and trade-offs involved. We have also taken a big-picture view of how a large and complex circuit like a
microprocessor is made. With this knowledge in hand, we now turn our attention to the topic of transistor scaling (methodologies
for making smaller transistors and denser circuits) and a discussion of the technology trends in the semiconductor industry. It is
important to understand the methods, challenges, and trade-offs involved in advancing the state of semiconductor technology.
Optional Topic: Transistor / IC Scaling
same
different
Attribute Symbol Full Comments: Constant Comments:

or (Constant Strategy: Scale all physical device Voltage Strategy: Scale all physical device
Feature Field) dimensions (L, Z, tOX, xj, etc.) AND all Scaling dimensions (L, Z, tOX, xj, etc.) by 1/s but do
voltages (VDD, VDS, VGS, VT) uniformly by NOT scale the voltages (VDD, VDS, VGS,
Scaling 1/s to produce a smaller transistor with the
factor
VT), e.g. in order to maintain compatibility
factor same large-channel behavior. (s > 1) with industry standard voltage specs or
(s > 1) existing products and applications.
Channel length L 1/s Scale down all physical device dimensions 1/s Scale down all physical device dimensions
by 1/s. by 1/s.
Channel width Z 1/s Scale down all physical device dimensions 1/s Scale down all physical device dimensions
by 1/s. by 1/s.
Device area 1/s2 Area = ZL, scales down by 1/s2. 1/s2 Area = ZL, scales down by 1/s2.
Packing density (devices s2 Die size reduced – improves yield and s2 Die size reduced – improves yield and
per u. area) number of die on the wafer. number of die on the wafer.
S/D junction depth xj 1/s Scale down all physical device dimensions 1/s Scale down all physical device dimensions
by 1/s. Junctions must be made shallower by 1/s. Junctions must be made shallower
to preserve subgate electrostatics. to preserve subgate electrostatics.
(Increases source/drain series resistance.) (Increases source/drain series resistance.)
Gate oxide thickness tOX 1/s Scale down all physical device dimensions 1/s Scale down all physical device dimensions
by 1/s. by 1/s. (Note: May scale by less if this
results in an unacceptably large vertical gate
field. Large field increases susceptibility to
oxide wearout, hot carrier effects, vertical
field mobility degradation, gate leakage,
and dielectric breakdown.)
Gate oxide capacitance COX 1/s Gate area (ZL) reduced by 1/s2 and tOX 1/s Gate area (ZL) reduced by 1/s2 and tOX
reduced by 1/s, so COX (=εOXZL/tOX) reduced by 1/s, so COX (=εOXZL/tOX)
reduced by 1/s. reduced by 1/s.
Gate oxide capacitance C’OX s tOX reduced by 1/s (and gate area ignored), s tOX reduced by 1/s (and gate area ignored),
per unit area so C’OX (=εOX/tOX) increases by s. so C’OX (=εOX/tOX) increases by s
(chart continued ….)
The semiconductor industry is continually shrinking transistor dimensions from one generation of CMOS process technology to the next, thus increasing device density (number of transistors per
unit area). This density increase results in:
• Lower manufacturing cost. Increased transistor density means that the same functionality can be packed into a smaller chip (die) area. Smaller chips are less expensive to manufacture because
more chips fit on each wafer, improving fab volume and throughput. (Note that most of the manufacturing cost is per wafer, not per chip.) The yield (percentage of functional chips) also improves
dramatically as chip size is reduced.
• Improved chip performance. The performance improvement is realized at both the transistor level and the architecture/design level. Transistor speed (intrinsic switching speed and drive
current) improves, increasing the maximum clock frequency of the circuitry. And architects and designers have a larger transistor budget with which to make “smarter” chips (more functionality)
and faster chips (in terms of how fast the chip executes instructions or performs tasks).
Note the industry trend that microprocessor chip size (area) often increases from one generation to the next, even though transistor density is improving. This is driven by the desire to pack ever
more functionality onto the chip, making it more powerful and faster in terms of instruction execution. The performance vs. yield trade-off must be managed when defining the chip size.
For these reasons, chips generally become denser, faster, smarter, and cheaper to manufacture (per bit or per unit performance) from one generation to the next. This continuous improvement in
transistor density is described quantitatively by Moore’s Law, which is illustrated later in this module.
Therefore, it is worthwhile to address the topic of transistor scaling, i.e. methodologies for making transistors smaller. The goal of transistor scaling is to start with a MOSFET having reasonably
good large-geometry behavior, and uniformly miniaturize it such that this behavior is preserved; i.e. the subgate electrostatics can still be treated as quasi-one-dimensional, and small geometry
behavior such as hot electron effects, DIBL, etc., are avoided even though the transistor is smaller. This is easier said than done. We will discuss two approaches to transistor scaling: full scaling
(aka. constant field scaling), and constant voltage scaling. Scaling in a real manufacturing environment actually employs elements of both of these methodologies, with a healthy dose of other,
more pragmatic scaling techniques as well. By studying these two fundamental methodologies, we’ll get a better picture of what’s involved in transistor scaling.
Using the chart provided here, we can compare and contrast the full (constant field) scaling and the constant voltage scaling methodologies. Line items that are the same between the two have a gray
background. An explanation accompanies each item, to help you understand how things scale.
Full Scaling (Constant Field Scaling): The approach here is to scale all transistor physical dimensions by 1/s, where s is the desired scale factor (s > 1, e.g. s = 2 results in a 1/2 or 50% shrink).
This includes reducing the gate dimensions (Z and L), making the gate oxide thinner (tOX), making the source and drain junctions shallower (xj), making the source/drain and isolation areas smaller,
and scaling down the depletion region depths (W) inside the device (i.e. the source/drain-to-well and channel-to-well depletion region widths, which are scaled down by scaling up the well doping
concentration). Thus every physical dimension and feature of the transistor, whether “vertical” or “horizontal”, is reduced in size by 1/s, yielding a uniform three-dimensional miniaturization of the
MOSFET structure. The voltages are also scaled by 1/s, including the supply voltage which we will call VDD (which we assume supplies VDS and VGS) and the threshold voltage VT. By scaling all
physical dimensions and all voltages by 1/s, the subgate electric field (shape and intensity) is maintained, and hence all subgate electrostatics are the same, so that the post-shrink MOSFET has the
same long-channel behavior in principle as the original MOSFET, and can be described using the same models.
Constant Voltage Scaling: The approach here is to scale all transistor physical dimensions by 1/s, as above, but not to scale the voltages. The reason for keeping the voltages the same is usually
one of necessity, e.g. to adhere to an industry standard voltage spec, or to maintain voltage compatibility with existing products or applications. Because of this, constant voltage scaling (or elements
thereof) is generally of more widespread use than full scaling. Of course, by changing the physical dimensions and not the applied voltages, the subgate electric field will change (intensity and
shape) as will all subgate electrostatics, and thus the behavior of the transistor will deviate from its pre-shrink model (e.g. two- and three-dimensional effects become more pronounced in the
treatment of subgate electrostatics, and small geometry behavior such as hot electron effects, DIBL, etc., play a larger role).
Transistor / IC Scaling (cont.)
same
different
factor
Supply voltage VDD 1/s VDD is scaled down by 1/s to preserve 1 VDD not scaled, e.g. to maintain
subgate electric field (intensity and compatibility with industry standard
shape) and subgate electrostatics. (Note: voltage specs or existing products and
VDD is assumed to supply the transistor applications. (Note: VDD is assumed to
voltages VDS and VGS.) supply the transistor voltages VDS and VGS.)
Electric field intensity
ε 1 Field remains constant (shape and
intensity) b/c all dimensions (L, Z, tOX, xj,
s Field strength increases by factor of s
because physical dimensions (L, Z, tOX, xj,
W, etc.) and voltages (VGS, VDS, VT) etc.) scaled down by 1/s but voltages (VGS,
scaled down by 1/s. Post-shrink subgate VDS, VT) are not scaled. Post-shrink
electrostatics approx. the same as pre- subgate electrostatics are now different
shrink, hence large-channel MOSFET from pre-shrink, and device behavior
characteristics preserved. changes.
Substrate/well doping NA s Scale depletion region depth W (S/D-to- s Scale depletion region depth W (S/D-to-
concentration well and channel-to-well) down by 1/s, to well and channel-to-well) down by 1/s, to
preserve subgate electrostatics. Since W ~ preserve subgate electrostatics. Since W ~
√(V/NA), can do this by scaling NA up by s √(V/NA), can do this by scaling NA up by s
and VDD down by 1/s. and VDD down by 1/s.
Threshold voltage VT ~1/s Because all device dimensions/features and ~1 VDS and VGS (assumed equal to VDD) are not
voltages scale by 1/s, it follows that VT also scaled, and neither is VT.
scales by ~1/s.
(VT adjust implant can be used to achieve (VT adjust implant can be used to achieve
desired VT value.) desired VT value.)
Body factor coefficient γ 1/√s γ ~ (√NA)/C’OX . NA and C’OX are both 1/√s γ ~ (√NA)/C’OX . NA and C’OX are both
scaled up by s, so γ is reduced by 1/√s. scaled up by s, so γ is reduced by 1/√s.
Drain current ID ~1/s ID ~ (Z/L)µeffC’OX[(VGS-VT)VDS] (square s ID ~ (Z/L)µeffC’OX[(VGS-VT)VDS] (square
law theory, linear regime). Since both law theory, linear regime). Since the
terms in the bracket scale down as 1/s, and voltage terms do not scale, and C’OX scales
C’OX scales up by s (and the 1/s scaling of Z up by s (and the 1/s scaling of Z and L
and L cancels out in Z/L), it follows that ID cancels out in Z/L), it follows that ID scales
scales down as 1/s. up by s.

We see that all the physical dimensions are scaled down by 1/s in both methodologies, hence all items depending purely on device dimensions are shown in gray on the chart.
Shrinking the dimensions of lithographically-defined features, such as the gate length L, present ever-increasing challenges for photolithography and etch technologies. Of
particular concern is the optical phenomenon of diffraction, whereby light “spreads out” as it passes through a small (relative to the wavelength) opening, such as a feature on
the photomask. This makes it harder to resolve small features, and ultimately limits the feature size and transistor density. Because feature dimensions shrink faster than the
wavelength of UV light used for photolithography, diffraction becomes an increasing limiter. Improvements in UV light sources and optics (e.g. laser sources, lens
improvements, etc.), photoresist and developer chemistry (e.g. chemically-amplified photoresists, etc.), and photomask technology (e.g. optical proximity correction, phase-
shift masks, etc.) help to combat the effects of diffraction. Future exposure sources having smaller wavelengths than UV - such as x-ray, electron, and ion sources - are under
consideration, but this requires fundamental changes in the optics, photomasks, and photoresists as well. Advances in etch technology also improve feature resolution, by
enabling high-aspect-ratio etching and vertical sidewall profiles. Because smaller and denser features can be destroyed by smaller particles, continuous improvements in
cleanroom technology, defect metrology, and process equipment are also required.
Also of interest is the scaling of the source and drain junction depths -- this is necessary in order to maintain the one-dimensional treatment of the channel field/charge. If the
junction depths were not scaled, the relative increase in source and drain sidewall area adjacent to the channel region would make the subgate field/charge profile deviate
toward a two-dimensional model. In order to preserve good MOSFET characteristics, the source and drain junctions must be scaled along with the rest of the dimensions.
From a manufacturing standpoint, it is not easy to make shallow junctions. Dopant channeling can be minimized by performing angled implants (to avoid channeling paths in
the silicon crystal lattice) and/or using pre-amorphization implants (implanting Si or Ge into the silicon substrate surface, rendering it amorphous and thus destroying any
crystalline channeling paths; a subsequent anneal will heal the surface damage and return it to single-crystal structure). Another common technique is the use of heavier
dopant atoms which have a shallower implant depth and diffuse less rapidly (e.g. using In or BF2 instead of B for shallow P-type implants). And care must be taken not to
silicide through the shallow junction, as silicon is consumed in the silicidation reaction -- hence the advantage of having a heavily-doped tip to preserved good channel
characteristics, adjacent to a deeper “bulk” source/drain region which lowers the source/drain resistance and can be silicided safely.
Another line item of particular interest is the scaling of the gate oxide. It is challenging to grow an ultra-thin, high-quality gate oxide uniformly over the wafer surface.
Thinner oxides are more susceptible to defects/pinholes, gate oxide wearout, ESD (electrostatic discharge) damage, dielectric breakdown, and gate leakage (tunnel) current.
Remember: the gate oxide is the heart of the transistor, and must be of the highest quality and uniformity.
Other courses discuss in greater detail the challenges associated with fabricating smaller device features.
Of course, any line item that depends on voltage will be different between the two methodologies (non-gray background on chart), because constant voltage scaling does not
scale the applied voltages. Observe from the chart that the electric field strength is not scaled in the full (constant field) methodology, but increases by s in the constant voltage
methodology (because the physical dimensions have shrunk but the applied voltages have not, resulting in a larger field). This non-scaled field will cause the device to deviate
from its pre-shrink behavior, by exacerbating two-dimensional channel effects and small-geometry effects (hot electron, DIBL, etc.).
Notice also that the threshold voltage VT is scaled in the full scaling methodology, but is not scaled in the constant voltage methodology. The drain current ID scales down as
1/s for full scaling, but increases as s for the constant voltage scaling (due to the larger fields presented by both VGS and VDS, which are assumed to be supplied by VDD). This
would appear to be an advantage, as higher drive current implies higher circuit speed. However, it comes at the price of increased two-dimensional channel behavior,
exaggerated small-geometry effects, increased power consumption, and increased reliability risk. Therefore, while increased drive current is desirable, the trade-offs must be
carefully managed. Also note that the subthreshold swing voltage, S, does not scale, i.e. the ID-VGS curve in weak and moderate inversion remains the same. At the same time,
the supply voltage is reduced (for constant field scaling), meaning that the gate voltage reduction required to turn the transistor off is a larger fraction of the total bias voltage
range, hence noise margins are reduced.
Transistor / IC Scaling (cont.) same
different
factor
DC power consumption PDC ~1/s2 PDC = IDVDD. VDD and ID decrease by 1/s, ~s PDC = IDVDD. VDD not scaled and ID
hence PDC decreases by 1/s2. increases by s, hence so does PDC.
DC power consumption 1 PDC decreases by 1/s2 and area decreases by ~s3 PDC increases by s and area decreases by
per unit chip area 1/s2, so PDC/A ≈ 1. 1/s2, so PDC/A increases by s3.
Transistor switching time ~1/s ID is reduced by 1/s but so is COX, i.e. there ~1/s2 ID increases by s while COX decreases by 1/s
is less current to charge proportionally less (i.e. there is more current available to
capacitance, so these effects cancel. But the charge less capacitance), hence the
capacitances only need to be charged to a transistor switching time decreases by 1/s2.
VDD which has been scaled down by 1/s, (Note that VDD is not scaled, so the
hence the 1/s reduction in transistor capacitances must still be charged to the
switching time. original VDD value.)
Gate delay ~1/s Tracks transistor switching time. ~1/s2 Tracks transistor switching time.
Transistor power-delay 1/s3 Power decreases as 1/s2 and delay decreases ~1/s Power increases as s and delay decreases as
product as 1/s, so power-delay product decreases as 1/s2, so power-delay product decreases as
1/s3. 1/s.
Metal line width 1/s Note: If scale the transistors but not the 1/s Note: If scale the transistors but not the
interconnects, can not realize die size interconnects, can not realize die size
reduction! reduction!
Metal line thickness 1/s Height reduction often required by fab 1/s Height reduction often required by fab
process to maintain metal line aspect ratio process to maintain metal line aspect ratio
(otherwise they become too tall and narrow (otherwise they become too tall and narrow
to fabricate reliably). (Though scaling is to fabricate reliably). (Though scaling is
typically less than 1/s in practice.) typically less than 1/s in practice.)
Metal line cross- 1/s2 Width and thickness both reduced by 1/s. 1/s2 Width and thickness both reduced by 1/s.
sectional area
Metal line resistance R ~s R = ρL/A. Assuming line/trace lengths also ~s R = ρL/A. Assuming line/trace lengths also
reduced by ~1/s, line resistance increases by reduced by ~1/s, line resistance increases by
~s. ~s.

The DC power consumption of the transistor is reduced for full scaling (because the current and voltage are both scaled down), but the power consumption
per unit silicon area does not scale (because the device power scales down as 1/s2 but so does the area). For the case of constant voltage scaling, the power
consumption scales up (because the current scales up and the supply voltage remains constant), and the power per unit area scales up strongly (because the
device power scales up while the area scales down). This discussion refers to DC power consumption (i.e. a current ID flowing across a source-to-drain
voltage drop of VDD when the transistor is held in the “on” state). Dynamic (AC) power consumption tends to increase from one generation to the next, due
mostly to the increased clock frequency.
On the subject of power, note that supply voltages trend downward over time, as necessitated by smaller transistors and thinner gate oxides for reliability
reasons, and the desire to maintain constant fields or at least minimize/control increases in field strength. At the same time, the device density trends
upward. The upshot is more devices drawing AC power from a smaller supply, which leads to more power supply variation (noise) and makes the task of
distributing stable power to the IC doubly more difficult. (Many devices switching simultaneously places large AC current demands on the supply to provide
the required charge, and can cause the supply voltage to “droop” as it struggles to supply enough current and then “overshoot” later if the demand suddenly
drops -- this variation in the supply voltage is called supply noise. Design techniques exist for minimizing and/or tolerating supply noise, but it becomes
more challenging as the semiconductor technology advances.)
The transistor switching time and gate delay are reduced by scaling (with a stronger reduction for constant voltage scaling -- see the chart for details). This
results in a speed improvement for the circuit -- assuming it is not RC limited, which brings us to a discussion of scaling the interconnects ….
If the transistors are scaled down but the interconnect circuitry is not, no reduction in die size is realized. Hence, it is necessary to scale down the
interconnects as well as the transistors. A reduction in metal line width usually necessitates some reduction in metal thickness as well, to preserve a
manufacturable aspect ratio (otherwise the metal lines become too tall and narrow to manufacture reliably). Scaling down the metal line width and thickness
reduces the cross-sectional area and increases the resistance. The current density increases, as shown on the chart, resulting in more resistive heating and
greater susceptibility to electromigration (a phenomenon that forms voids in the metal lines over time, hence posing a reliability risk).
same
different
factor
Metal line current s Current (ID) decreases by 1/s but cross- s3 Current (ID) increases by s and cross-
density sectional area decreases by 1/s2. Hence sectional area decreases by 1/s2. Hence
current density increases by s. current density increases by s3.
Susceptibility to electromigration and Susceptibility to electromigration and
resistive heating increases. resistive heating increases.
Voltage drop on metal ~1 Resistance increases by s and current s2 Resistance increases by s and current
line through the line decreases by 1/s, hence through the line increases by s, hence
voltage drop on metal line does not scale (V voltage drop on metal line increases by s2
= IR). Percentage-wise, this means more (V = IR). Percentage-wise, this means more
“wasted” voltage (dropped on metal line), “wasted” voltage (dropped on metal line),
less doing actual work (dropped across less doing actual work (dropped across
transistor). transistor).
Metal line parasitic C 1/s Width of metal line reduced by 1/s 1/s Width of metal line reduced by 1/s
capacitance decreases surface area by 1/s, which reduces decreases surface area by 1/s, which reduces
parasitic metal-to-metal overlap capacitance parasitic metal-to-metal overlap capacitance
by 1/s. Thickness of metal line reduced by by 1/s. Thickness of metal line reduced by
1/s reduces metal sidewall-to-sidewall 1/s reduces metal sidewall-to-sidewall
capacitance by 1/s also. capacitance by 1/s also.
Metal line RC time RC ~1 Resistance is increased by s but capacitance ~1 Resistance is increased by s but capacitance
constant is decreased by 1/s, hence RC time constant is decreased by 1/s, hence RC time constant
roughly the same. This is bad for long roughly the same. This is bad for long
lines: it can prevent us from taking lines: it can prevent us from taking
advantage of the improved transistor advantage of the improved transistor
switching speed (i.e. the circuit speed is switching speed (i.e. the circuit speed is
becoming RC limited). becoming RC limited).
The interconnect capacitances tend to be reduced, because the metal-to-metal overlap area and metal sidewall area are reduced. Because the resistance
scales up by about the same amount as the capacitance scales down, the RC product in principle remains about the same*. This implies that ICs will
become progressively more RC limited from one generation to the next -- i.e. the transistor switching speed is improving while the interconnect RC delay
remains roughly the same. As discussed previously, this has resulted in the industry’s migration to copper interconnects (lower resistance) and low-k
interlayer dielectrics (lower capacitance) to reduce RC delay and take full advantage of the transistor performance improvements.
* For global wires (long wires that run across all or most of the chip), the RC delay tends to become worse from one microprocessor generation to the next
because the chip size tends to increase as discussed previously, making global lines longer.
same
different
factor
Contact/via area 1/s2 Reduction of each side of contact/via 1/s2 Reduction of each side of contact/via
“window” opening by 1/s results in a “window” opening by 1/s results in a
reduction in area of 1/s2. reduction in area of 1/s2.
Contact/via current s The current (ID) scales as 1/s and the contact s3 The current (ID) scales as s and the contact
density area scales as 1/s2, therefore the current area scales as 1/s2, therefore the current
density scales as s (J = I/A). density scales as s3 (J = I/A).
Contact/via resistance s2 Contact/via “window” opening reduced by s2 Reduced contact/via “window” opening
1/s2 results in resistance increase as s2. (neglecting any change in via/contact
(neglecting any change in via/contact height/depth that may result from changes
height/depth that may result from changes in ILD thickness).
in ILD thickness).
Contact/via voltage drop s The current (ID) scales as 1/s but the s3 The current (ID) scales as s and the
contact/via resistance scales as s2, hence the contact/via resistance scales as s2, hence the
voltage drop across the contact/via scales by voltage drop across the contact/via scales as
s (V = IR) – opposite the direction of the s3 (V = IR). Larger voltage drop across
voltage (VDD) scaling! Larger voltage drop smaller contacts leads to reliability
across smaller contacts leads to reliability concerns.
concerns.
The contact/via resistance also scales up, due to the reduction of the contact/via cross-sectional area. Therefore, the industry is moving toward copper-filled
vias, which have a lower resistance than traditional tungsten vias. Using copper vias in combination with copper metal lines results in a large reduction in
overall interconnect resistance.
For a broader and more indepth summary of IC scaling trends and challenges, the interested reader is referred to chapter 1 of the text: Digital Systems
Engineering, by W.J. Dally and J.W. Poulton, Cambridge U. Press, 1998. Also, chapter 5 of the text: Operation and Modeling of the MOS Transistor, by
Y.P. Tsividis, McGraw-Hill, 1987.
Pulling It All Together: Intel® Microprocessors
4004
386
Pentium® II
Pentium® 4
(note: not to scale wrt. one another)
A microprocessor is a good example of a very large and complex digital circuit that contains a lot of logic and memory. This is a good place to pull the concepts from all five
modules together for a final, big-picture review and summary.
• The silicon chip contains a millions of transistors (MOSFETs) which act like microscopic switches. By understanding the electronic properties of silicon itself, PN
junctions, and the MOS Capacitor, we can understand how a MOSFET works. This is the primary goal of this course.
• These transistors can be connected together to form various logic gates. A logic gate is a small group of transistors that performs some elementary logic operation. We
studied five logic gates: inverter, AND, NAND, OR, NOR. Larger circuits (e.g. our burglar alarm control circuit, our decoder, or parts of a microprocessor) can then be
constructed from logic gates. By understanding how transistors work, we can understand how these logic gates work.
• Transistors can also be connected to make memory cells. A memory cell is a small collection of transistors that stores a bit (0 or 1). Large memories can be constructed
using an array of memory cells. There are different types of memory cells, employing different techniques for storing a bit. We studied three memory cells: DRAM, SRAM,
and Flash EEPROM. Again, by understanding how transistors work, we can understand how these memory cells work.
• Finally, we took a big-picture view of how a complex integrated circuit or “chip” is born. A circuit is created by design engineers and its functionality is verified through
simulation. The circuit is then laid out for silicon. There are many computer-based design tools involved in the design process, and it is necessary to divide large, complex
chips into a collection of smaller blocks and sub-blocks that can be designed by an individual or small team. The transistor-level layout is “fractured” into layers (e.g. poly,
metal-1, etc.), and this fractured database is used to make the photomask set. The fab uses these photomasks to manufacture the chips on silicon wafers using a layer-by-layer
fabrication process (other courses describe this process in detail). The chips are then assembled (packaged). The chips are electrically tested at various stages of the
manufacturing process.
A Brief History of Intel® Microprocessors:
A few Intel® microprocessors are shown for example (the pictures are not to scale wrt. one another). The 4004 was the world’s first microprocessor. It was introduced in
1971, and used primarily in calculators by a company called Busicom. It consisted of 2,300 transistors manufactured on a 10-micron process, and ran at 108 kHz.
The Intel® 8086 was introduced in 1978, having 29,000 transistors on a 3.0-micron process, and running at 5 – 10 MHz. It was selected by IBM to be the microprocessor in
the first personal computer. The 80186 was introduced in 1982 and was used mostly in microcontroller applications. The Intel® 286 (80286) was introduced in 1982 as a
general-purpose microprocessor for personal computers. It contained 132,000 transistors fabricated on a 1.5-micron process, and ran at 6 – 15 MHz.
The Intel® 386 (80386) was introduced in 1985. The introductory version contained 275,000 transistors fabricated using a 1.5-micron process, and later 1.0-micron. It was
introduced at 16 MHz, and reached speeds as high as 33 MHz in its lifetime. The Intel® 486 was introduced in 1989 with 1.2 million transistors on a 1.0-micron process, later
0.8-micron. It had clock speeds up to 66 MHz in its lifetime.
The Pentium® processor was introduced in 1993 with 3+ million transistors on a 0.5-micron process, later 0.35-micron. Pentium® with MMXTM was introduced in 1997 with
4.5 million transistors on a 0.35-micron process, later 0.25-micron. The various versions of Pentium®/MMXTM reached clock speeds around 300 MHz. The Pentium® II
processor was introduced in 1997. It had 7.5 million transistors and was fabricated on a 0.35-micron process (Klamath), and later 0.25-micron (Deschutes). It had clock
speeds ranging from 233 to 450 MHz in its lifetime. The Pentium® III processor was introduced in 1999 with 9.5 million transistors on a 0.25-micron process (Katmai) and
speeds up to 600 MHz, and later that year with 28 million transistors and on-die L2 cache on a 0.18-micron process (Coppermine) and speeds in excess of 1 GHz. Pentium® 4
(Willamette) was introduced at the end of 2000 with a whopping 40+ million transistors on a 0.18-micron process, at initial speeds of 1.4 and 1.5 GHz.
Intel® Microprocessors & Moore’s Law
P2
10,000,000
PPro
PMMx
every 2 yrs P1
double every year every 1.5 yrs 80486 every 2.5 yrs
80486 80486
1,000,000
80386
Number of Transistors
80186
80286
100,000
8088
8086
10,000
8085
8008 8080
4004
1,000
Jan-70 Jan-72 Jan-74 Jan-76 Jan-78 Jan-80 Jan-82 Jan-84 Jan-86 Jan-88 Jan-90 Jan-92 Jan-94 Jan-96 Jan-98
Intro Date
Moore's Law was first published by Intel® co-founder Gordon Moore in 1965. Originally suggesting that processor complexity
(transistor density) doubles every year, the law was revised in 1975 to suggest a doubling every 1.5 - 2 years.
This graph shows the number of transistors for each Intel® microprocessor (up through Pentium® II) vs. the date on which it was
introduced. The solid lines depict the rate of doubling every year, 1.5 years, 2 years, and 2.5 years, for reference. Note that early
on, it looked like a doubling every 1 - 1.5 years. In more recent times, it appears to double about every 1.5 – 2 years.
Moore’s law has important implications for the microelectronics industry. It predicts the continuation of smaller transistors and
denser chips - which translates either into smaller chips or smarter chips, depending on whether the density gain is used to reduce
die size or to increase the transistor budget (or typically, a little of both). Making the chips smaller has big advantages in terms of
volume and yield, which amounts to lower manufacturing cost. Shrinking the transistors has advantages in terms of performance
(faster circuitry and, typically, a larger transistor budget for the architects and designers). No other industry in history has seen this
rate of performance gain and simultaneous cost reduction (per unit performance). For example, if the history of the automotive
industry followed Moore’s law, your car would get 10,000 miles to the gallon, and it would be cheaper to throw it away than to
park it.
* Note that these transistor counts are not normalized to their effective (core) die sizes, and hence do not represent transistor
density per se. Also note that this is one family of microprocessors from one company; chips from other manufacturers, and other
types of chips such as DRAMs, DSPs, etc., could also be plotted to get a more accurate picture of the industry as a whole.

SemiconductorDevicePhysics - 4pt3 (Sze)

Загружено:

Сведения о документе

Исходное описание:

Оригинальное название

Авторское право

Доступные форматы

Поделиться этим документом

Поделиться или встроить документ

Параметры публикации

Этот документ был вам полезен?

Это неприемлемый материал?

Авторское право:

Доступные форматы

SemiconductorDevicePhysics - 4pt3 (Sze)

Загружено:

Авторское право:

Доступные форматы

Introduction to

Semiconductor Device Physics

Rev. 4.3, November 2001

The objectives of this module are:

valence electrons (4) n=1 Atomic Mass [amu]

Schematic Diagram of Covalent Bonding in Silicon

Bonding Diagram Energy Band Diagram

At absolute zero* all of the electrons are in the valence band.

Bonding Diagram Energy Band Diagram

Bonding Diagram Energy Band Diagram

Bonding Diagram Energy Band Diagram

f(E) 0 < T1 < T2 T=0K

g(E) = number of available g(E) = number of seats in

f(E) = probability of finding an EC f(E) = probability of

f(E)*g(E) = number of electrons EG f(E)*g(E) = number of

³ f(E)*g(E) dE = total number

And similarly for the home section.

source: Pierret & Neudeck (editors), Modular Series on Solid

Ei = + kBT ln¨ ¸ kBT = thermal energy = 0.260 eV at 300 K

source: Pierret & Neudeck (editors), Modular Series on Solid

Conduction in Intrinsic Si Conduction in Intrinsic Si

source: Pierret & Neudeck (editors), Modular Series on Solid

Bonding Diagram Energy Band Diagram

Some useful semiconductor properties

Ge 0.66 2.33x1013 0.55 0.36 3900 1900 43 16 936

All values in table are for T = 300 K (room temperature).

source: S.M. Sze, Physics of Semiconductor

(room temperature) Band Gap is too

Small or No Band Gap Moderate Band Gap Large Band Gap

nucleus (15 protons

valence electrons (5) n=1

Column-5 elements like phosphorous have 5 valence electrons.

Bonding Diagram: Silicon Doped with Phosphorous (N-Type)

“Extra” (5th) valence

Energy Band Diagram: N-Type Si (Absolute Zero)

source: Pierret & Neudeck (editors), Modular Series on Solid

Energy Band Diagram: N-Type Si Energy Band Diagram: N-Type Si

Bonding Diagram: N-Type Si Energy Band Diagram: N-Type Si

This is the onset of the extrinsic temperature range.

Bonding Diagram: N-Type Si Energy Band Diagram: N-Type Si

Bonding Diagram: N-Type Si Energy Band Diagram: N-Type Si

source: Pierret & Neudeck (editors), Modular Series on Solid

source: Pierret & Neudeck (editors), Modular Series on Solid

source: Pierret & Neudeck (editors), Modular Series on Solid

+ ND ND+ = conc. of ionized donor atoms (cm-3)

Extrinsic & Intrinsic Temperature Regions

extrinsic temperature region: n ≈ ND

intrinsic temperature region: n = p = ni

V = applied voltage (volts)

Note that the current is dominated by electrons, the majority carriers.

source: Pierret & Neudeck (editors), Modular Series on Solid

source: S.M. Sze, Physics of Semiconductor low temperature high temperature

valence electrons (3) n=2

Bonding Diagram: Silicon Doped with Boron (P-Type)

Energy Band Diagram: P-Type Si (Absolute Zero)

Energy Band Diagram: P-Type Si

This is the Freeze Out temperature region.

Energy Band Diagram: P-Type Si Energy Band Diagram: P-Type Si

Recall that we will treat holes as independent, positive charge carriers.

This is the extrinsic temperature region.

Energy Band Diagram: P-Type Si Energy Band Diagram: P-Type Si

Energy Band Diagram: P-Type Si Energy Band Diagram: P-Type Si

f(E)g(E) = number of electrons EG f(E)g(E) = number of