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Horatio Quinones / Alec Babiarz / Alan Lewis


2762 Loker Avenue West

Carlsbad, Ca. USA


The use of flip chip technology by the electronic industry dates back to the early sixties.
The concept of interconnection arrays, in contrast to the peripheral, offers a very
attractive packaging technology from numerous aspects, including thermal, electrical
and mechanical performance and size reduction. Although a very reliable technology,
(more than a billion controlled collapse chip connections, C4, have been shipped to the
field successfully), larger packages combined with more demanding field environments
like temperature excursion and temperature cycles, posed an adverse impact to the
interconnection fatigue resistance (Coffin-Manson low cycle fatigue model). The
introduction of underfill materials, originally used as interconnection coatings in flip chip
arrays, yielded a thirty-to sixty-fold improvement in fatigue life, thus extending the
undefiled flip chip application space that surpasses numerous other interconnection
technologies. The selection of underfill material and dispensing method becomes a
crucial step in the manufacturing process of flip chip packages. This paper addresses:
(a) underfill challenges in flip chip packages, (b) quantitative reliability performance of
encapsulated vs. no-underfill packages, (c) a proposed formulation to evaluate flip chip
encapsulated technologies performance, and (d) mechanisms present in undefiled


In the 1960’s, International Business Machines (IBM) introduced a new die termination
and interconnection scheme as part of the Solid Logic Technology (SLT). The concept of
holes etched in the glass exposing underlying AlSi device termination pads allowed the
communication of the solid state devices with the "outside world." However, chips
collapsed as a result of molten solder running down the lands. Potential shorts at the
die edges needed to be avoided and hence, the chip collapse had to be controlled. A
solution to this problem led to the invention and development of what is known today
as Controlled Collapse Chip Connection, C4 technology, or more generically, The Flip
Chip Interconnection Technology. The C4 concept was a natural choice when
termination arrays were designed for Bipolar and CMOS technologies.

Properties such as self-centering, planarity requirements, electrical and thermal

properties, high I/O count, design flexibility and manufacturing yields, soon made the
C4 interconnect the logical choice. The reliability of this array technology has proven to
be very robust over the last three decades with over a billion C4 interconnections in
operation today. However, this robustness rapidly decreases as the size of the die
increases, and/or the size of the interconnect decreases. In addition to this geometric
effect on C4 reliability, the field environment can also negatively affect the robustness,
(i.e., larger temperature excursions, green cycles, longer operational time, etc.) of C4

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technology in today’s form factors for electronic packages. In the early eighties, coating
materials for C4 connections were thought to provide environmental protection, and
were found to improve the fatigue life of "this new undefiled array of C4" by a factor of
two to three. The die underfill became a subject of considerable interest [1], different
underfill Where g is plastic strain range.

schemes and materials were dispensed, the underfill dispensing showed to be a key
factor in the improvement of

interconnection technology [2].

Where g is plastic strain range.

Flip Chip Underfill

The subject of C4 reliability forecasts, although an old one, is still going through many
developments phases [3]. Strain range [4] approaches to evaluate fatigue life of ductile
materials (Equation 1), such as that taught by Coffin-Manson [5], have been the most
widely used expressions by the electronic packaging industry. To account for dwell
times and frequency, another term was introduced to the above expression [6], namely,

This equation is known as the Modified Coffin-Manson Equation (MCME), where T is the
absolute temperature, f is frequency, D H is the grain boundary diffusion activation
energy, and k is the Boltzman constant. This term, although first introduced based on
empirical results, has possible physical basis, in particular if diffusion mechanisms are
sighted. The Modified Coffin-Manson Equation becomes:

This expression, although there is no rigorous proof of its being correct in its linear
independence (i.e., no synergistic effects allowed), works quite well for many solder
type interconnection technologies in a large range of electronic applications. The
presence of the properly dispensed underfill can improve the life of the package
substantially. Factors ranging from thirty to sixty have been reported [7]. This
remarkable improvement expanded the field application space, and at the same time
allowed for larger packages and smaller interconnections. Numerous techniques are
used today. Automated underfill material dispensing present unique challenges which
can create reliability problems if not properly addressed. To overcome these challenges,
it is important to understand the character of the fluids and their effect on automation
and reliability.

Most underfill fluids are pre-mixed two-part epoxies. The reason that fluid formulators
pre-mix the fluid is that the quality control of the mixing process is critical to the quality
of the fluid. The mixing process requires equipment for mixing and monitoring that are
beyond the capability of most production facilities. The pre-mixed fluids are frozen at -
40 ° C (-40 ° F) for shipment and storage. Freezing the fluid greatly retards epoxy
cross-linking because these materials are heat-cure epoxies. At this temperature, the
shelf life of these materials usually ranges from several months to a year. If the

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material is not stored properly, partial cross-linking can take place. This can have an
adverse effect on product reliability in two ways: (1) the resultant increase in viscosity
can cause voids or incomplete underfilling, (2) the cure temperature affects the length
of the polymer chains. If partial cure occurs at low temperatures, the cured
characteristics of the material can change. Once thawed, these materials have a limited
pot life for the reasons listed above.

Pot life can vary from several hours to several days. Underfill material that has been
improperly handled will behave differently during the dispensing process. Dramatic
changes in dispensing flow rates, stringing, and changes in underfill rates can all be an
indication of improperly handled material. The following things can be done to mitigate
these problems:

l Set up proper handling procedures for receiving and storing these materials.
Temperature recording devices or special cubes that melt if exposed to high
temperature can be shipped with the material as added assurance of proper

l Dispensing system automated logging of syringe changes can ensure that once
the material is thawed, it is not used past its specified pot life.

l Dispensing equipment with calibration systems are available that will reject fluid
that is thick enough to cause a significant change in flow rate.

l Cooling the fluid syringe while mounted on the dispenser can increase the
material pot life.

l Viscosity sensitivity to temperature.

Most underfill fluids are extremely viscosity sensitive to temperature. Some fluids
change viscosity by an order of magnitude for a 20 ° C temperature change. In
addition, the contact angle of the fluid (a measure of the capillary force for underfilling)
decreases with temperature. There is a relationship between contact angle, viscosity,
and underfill speed [8]. These three effects decrease the time required for the fluid to
underfill. The temperature of the substrate and die must be controlled to properly
underfill the part. However, if the parts are too hot, the material will start to cure
prematurely, causing voids and incomplete underfilling. To account for this sensitivity,
some of the following things can be done:

l Use a pump or valve that is insensitive to viscosity changes, such as servo piston
pump. Pump or valve accuracy can affect the fillet size [9].

l Integrate the temperature control of the substrate and die with the dispenser.

l Control the temperature of the needle tip to increase dispense flow rate, reduce
back pressure, and achieve better fluid-to-needle break-off.

Filler Particles Are Abrasive

Most underfill materials contain about 70% of filler particles that are silica (often times

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spherical) ranging in size from approximately 10 to 50 microns, depending on the

application. These particles are extremely abrasive and somewhat brittle. Their shape is
important because the ratio of volume to surface area affects settling, separation during
flow, viscosity, and particle packing. Particle size distribution is important because it
can affect the maximum filler ratio. Because of these factors, the following must be

l Wetted parts must either be abrasion-resistant, or easily and inexpensively


l The pump must not damage the particles. Hardened pumps or valves with pinch
points can grind filler particles. In some cases this is not critical, but in high
reliability large die applications it can be a factor.

Underfill Materials use Capillary Action to Underfill

As mentioned above in reference to temperature sensitivity, underfill materials use

capillary action to underfill. To use capillary action to its complete advantage in order to
get the best reliability from the final package, it is important to also consider the

l The topography of the space between the die and the substrate can cause the
underfill material to flow at different rates. In the case of perimeter-bumped die,
an L-shaped pattern may cause air to be trapped at the opposite corner.

l The dispensing pattern must be chosen for quick, void-free underfill. Note that
new dispensing patterns are being developed as the fluids and packages evolve.
l Flux cleaning is advisable because a flux contaminant at or near a bump may
cause a void and subsequently a space for the solder bump to flow.
l Air entrapments (i.e., voids) located away from interconnection bumps will not
adversely affect reliability. The St. Venant's principle applies (i.e., stress
concentration is not altered in the bump).

l Any contamination from flux residue or the cleaning process can impede underfill

l High-flow materials have high surface tension and have a tendency to trap air
bubbles once formed. The material should be packaged air-free and the dispenser
should not be sensitive to this characteristic.

l High surface tension can cause the fluid to cling to dispensing tips. Plastic tips or
beveled tips to prevent wetting on the needle can be helpful. Needle heaters can
also be useful.

Flip Chip Strain Factor

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Different rates of expansion of the various structures connected by the solder bumps
induce relative displacements among them during temperature cycling: strains and
stresses are generated in the solder bumps, energy is dissipated, i.e., work is done by
these bumps.

The average shear strain, see Figure 1, of a connection located at location i is

Where ri is the distance from centroid, D Ti is the temperature excursion for member i
and H is interconnection height. In addition to the shear strain, there is also an axial
displacement present, as depicted in Figure 1. This induced axial strain is often
neglected, mainly because its magnitude for fully populated arrays can be significantly
smaller than the shear for some packages, and also because it is used as a "figure of
merit" in the reliability projection. When the expected value, or mean life, is used to
represent the life of the interconnect, we write the life prediction in the field as:

The subscripts F and L are used for the field and lab environment respectively. The axial

component of the strain could indeed become very important. For instance, depopulated
arrays without the dispensed underfill could go through large deflections along the axis
of the interconnection.

Figure 1. Interconnection strain during temperature expansion

These deflections induce large axial strain. In many instances, the axial component can
be much larger than the shear strain component itself. A similar situation is
experienced when some packages are subjected to power cycles. Thermal gradients
induce warping and axial deflections of the various components (i.e., die and die
carrier), resulting in cases where inner interconnections may experience larger total
strains than those placed at edges and corners. Fatigue failures can occur on inner
interconnections earlier than outer interconnections. This is a clear sign of other than
shear strain presence in the package. The presence of underfill serves multiple
purposes: (a) Elastic effect. It prevents the structure from reaching full relative x-y
displacement by constraining the "almost complete" free expansion possible. See Figure

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2. However, such an effect is relatively small, ten- to twenty-percent decrease in shear

strain, or twenty- to forty-percent increase in fatigue life.

Figure 2. Underfilled Flip Chip

This fact does not account for the improvement observed during load cycling, which can
be as much as sixty times.

(b) Structural support. There must be other mechanisms involved for properly
underfilled packages:


Die Size Temp. Frequency Cycles to Die Carrier Mean Life

Mm Degrees C CPD First fail KCycles

13 0 to 100 72 6,200 50mm white 203


13 0 to 100 72 11,000 50mm white 258


13 0 to 100 72 >2,500 50mm dark -


19.2 -65 to 150 144 >500 32mm white 10.4


19.2 -55 to 125 27 >500 32mm white 18.4


Table 1. Encapsulated Flip Chip Reliability Performance: mean life numbers are normalized to a common constant. (Data published by IBM-
Microelectronics [7] )

a passivated surface will tend to delay the time of crack initiation by smoothing the
surface and lowering slipping. Mechanical structural support contributes to lower
loading that causes solder creep. The smooth and continuous structure created by the
dispensed underfill decreases potential sites of stress concentration.

Once the package is encapsulated, the fatigue endurance becomes a function not only
of the solder interconnection, but also of the underfill material. As long as properly

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dispensed underfill material with desired physical properties is used, package life
improvement will be realized. The variation in fatigue performance among
interconnections is diminished because the continuity and smoothness of the underfilled
array overshadows local geometric differences that may exist among interconnections.
A pseudo hydrostatic compressive state of stress is imposed on the interconnections in
the presence of the underfill after polymer curing. This state tends to minimize deviator
displacements and allows some volumetric changes. This loading state is an optimum
configuration to prevent and/or delay energy dissipation of the interconnection by
means of rupture or material fracturing.

(c) Finally the presence of the underfill changes the boundary conditions of the two
structures joined by the interconnections without the dispensed underfill. In other
words, the underfilled system may be treated as a quasi multi-layer system, and
stresses and displacements may be calculated accordingly. Table 1 summarizes
reliability performance results for C4 flip chip interconnections underfilled when
subjected to accelerated thermal cycling (ATC). Similar packages without the dispensed
encapsulation will only last a few hundred cycles of 0 to 100 ° C temperature
excursions. The number of cycles to first fail is somewhat consistent with the Coffin-
Manson strain range model. The encapsulated data tends to have standard deviations
higher than those of the unencapsulated packages. This fact may reflect the kinetics of
the process, i.e., the slow process of failing and the large difference in the number of
cycles to fail for different interconnections, and large variations in the underfill
characteristic (the data reflects process variations for a period of time of about five
years). There seems to be a correlation between the failures and the distance from the
neutral point (DNP). Larger DNP interconnections tend to fail earlier as expected from
shear strain mechanisms. Cracks are observed in the underfill near sites where solder
fractures occur. It has also been reported in some cases that no cracks in the underfill
were noticed, but solder fractures were observed [10].

Figure 3 depicts a typical crack initiation site for a flip chip underfill. The underfill
material must have good adhesion characteristics to both surfaces, die and die carrier,
as well as to the solder connections. Some materials may have good adhesion strength
to the silicon die and ceramic, but not to the FR4 carrier. In these cases, delamination
may occur in ATC stressing that may lead to early solder interconnection failures. The
underfill also provides a mechanical support by stiffening the package. This reliability
improvement is observed during package preconditioning where high dynamic loads are
applied to the package.

Figure 3. Drawing of a crack initiation site for an encapsulated flip chip after some ATC

This acceleration, coupled with the corresponding inertia masses, may cause solder
fractures unless dispensed underfill is in place. It has been observed that
unencapsulated flip chip interconnections deform significantly during ATC, contrary to
underfilled flip chips where very small deformation is experienced by the

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interconnections during ATC even if a fatigue fracture occurs (as depicted in the
drawing of Figure 4). There, it appears as if the cracks are propagating along the grain
boundaries throughout the entire interconnection.

Figure 4. Drawing of encapsulated C4 flip chip fatigue fractures during ATC showing
little bump deformation.

Cyclic creep deformation is a mechanism that results from an alternate load

superimposed to a non-modulated base load, i.e., shear forces from relative
displacements plus an external axial load (tensile or compressive). This cyclic creep can
be orders of magnitude larger than static creep [11]. Dispensed underfill in flip chip
arrays largely diminishes the cyclic creep effect and in many cases prevents it from
happening altogether. Experimental data has shown that many underfill materials used
by the industry have very high creep resistance properties; they "practically do not
creep" under the loads experienced by most electronic packages in the industry today
and are a fundamental improvement in packaging reliability.

Flip Chip Reliability Formulation

Reliability assessment of electronic packages encompasses four major steps: a basic

physical understanding of the failure mechanism, laboratory data generation,
acceleration models, and derived or adopted probability distribution functions consistent
with the statistical nature of the failure mode in question. In the case of flip chip
technology, there are some reliability concerns that need to be evaluated: (a)
environmental, i.e., temperature, humidity and direct current biased, (b) dynamic
loading, i.e., mechanical shock and vibration, and (c) cyclic loading, i.e., thermal and or
power cycling. The formulation presented here will only address the cycling loading
wearout, also known as solder low cycle fatigue. Other mechanisms that impact
interconnection reliability (T&H, DC bias, etc.), are not addressed here [12].

Low Cycle Interconnection Fatigue

Physical Mechanisms

Solder systems fatigue has been the subject of numerous analytical and experimental
studies that date back to the first part of the century. However, the mid-sixties studies
of high frequency cyclic stress of metals, lead to the development of perhaps the most
frequently used equation for electronic reliability, the Coffin-Manson fatigue model. As
already mentioned, this expression relates failure time to plastic strain range. The
overriding mechanism is that of work performed by the material as energy is fed into it.
Recall that the strain energy is:

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Where { e } is the strain vector and { e } T is its transpose, [K] is the stiffness tensor,
dW is the volume element. From this expression, it follows that the exponent for the
Coffin-Manson equation should be two. The strain factor to the second degree appears
in the energy of the system, any non-linearity is accounted for in the [K] factor and
should not be reflected in the value of the exponent, two. The fatigue of solder under
alternate loading consists of crack development followed by a crack propagation in the
solder that eventually may lead to electrical and/or functionality package failure. Plastic
deformations take place at every step of the cycle; such as a non-Markovian stochastic
process, which lead to surface ruptures after other forms of energy storage saturation
occur in the material.

Lab data generation

Accelerated stress tests are a practical absolute necessity for the evaluation of reliability
and quality of electronic packaging technologies. Ideally, no accelerated testing would
be best. Complex material geometries, etc., make the process of performance
forecasting very difficult by pure analytical methods. This discipline is still an art that
mandates the existence of a database from which one may use ad hoc acceleration
models that are not necessarily rigorously proven, to project field performance.
Urrhenius models, linear models (i.e., BET model for voltage acceleration), and more
complex models are used to bridge accelerated tests. For the case of low cycle solder
fatigue, as pointed out above, the Modified Coffin-Manson equation is the most widely
accepted acceleration model. For solder material used in the electronic industry, room
temperature is already above half the melting point. Hence, for all practical purposes,
the solder materials are operating at relatively high temperatures, material non-
linearities are present, and the risk of having mechanisms that may be predominant at
some temperature ranges only, pose a question about the validity of the lab data. Lab
data should be generated to cover as wide a range of environments as possible. Such
data interpolation gives some degree of confidence for the use of acceleration models to
extrapolate for untested environments, i.e., field conditions. Table 1 shows results from
various accelerated conditions, and with that data, acceleration parameters may be
verified resulting in the validation of the exponents for both the strain and the time
term of the MCME.

Reliability Formulation

There are mainly three modes of failure for underfilled flip chips under cyclic loading:
delamination at the die carrier underfill interface, delamination at the die underfill
substrate, and fracture in the bulk of the underfill. These modes of failure dictate, to a
large extent, the dynamics of the crack kinetics of the interconnections that may
eventually lead to functionality failures. In choosing the underfill material, it is
recommended that mechanical testing such as die shear, underfill delamination and
angle of wetness be assessed. Underfill materials may have good adhesion
characteristics for first level components and not for second level surfaces and vice
versa. The stiffness of the underfill plays an important role in determining die
mechanical integrity, a more compliant material applies less loading on die. Finally, the
thermal coefficient of linear expansion (CTE) must be such that tensile loading on the
interconnections is avoided as much as possible. A CTE that matches that of the solder

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or interconnection material is likely to be an excellent choice. The time-to-failure of one

interconnection traditionally has been assumed to fit statistical distributions such as
Weibull and Lognormal [13]. The authors do not embrace their use for fatigue-like
situations. A distribution based on the physics of the crack initiation and propagation
was first introduced by H.Quinones et al, SCRIP [14]. However, this paper uses the
Lognormal distribution strictly for illustration purposes.

An underfill package will be considered to have failed if any of the interconnections

fails, i.e., a competing risk formulation is needed. Let N be the time/cycles to failure of
a given interconnection located at position i, we define its reliability as qi(N;No,s ),
where N is the number of cycles, No is the mean of the Lognormal distribution, and s 2

is its variance. The failure probability for a single interconnection, i, can be written as:

Assuming Lognormal for the failure distribution of one interconnection, we can then

The competing risk can be modeled as the weakest link in a chain, therefore the
probability of success of the array of underfilled interconnections is the product of the
individual reliabilities, and linear independence is assumed.

For flip chip underfill, the time-to-failure for different interconnections is related by the
relative position with respect to the centroid. For a case of symmetric arrays with full
encapsulation, the centroid coincides with the geometric center. This center is known in
packaging reliability as the neutral point. Using the Coffin-Manson equation to
normalize the time-to-fail of any interconnections to a single position, i.e., a given
single distance from the neutral point (DNP) say, r*, we obtain the normalization value
(Figure 4):


It is customary to assume that the standard deviation remains constant for different
interconnections as well as for different environments, although it is not a proven factor
nor are there plausible arguments to justify such an assumption. (Authors have proven
a dependence on the variance on the environment.) For cases where this invariance is
assumed, and only the mean of the distribution is accelerated (MCME), the reliability
calculation of the underfill package becomes just the product of factors that involve only
one parameter, N0, and a geometry factor, a ij. Figure 5 illustrates reliability contours as

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function of cyclic loading for array interconnections.



Figure 5. Illustration of reliability maps (fraction failed per package), as a function of

cycles and temperature. Lognormal assumed for individual joint. (Published by IBM-


l Underfilled flip chip technology offers several advantageous features to the

electronic packaging technology: (a) Area arrays technology allows for the
placement of active I/O under the active area of the die. (b) Denser and smaller
packages are possible by the use of fully populated area arrays.
l The dispensing process can adversely affect the reliability of the final package if
proper attention is not paid to the following characteristics: temperature
sensitivity, pot life, filler fluid characteristics and capillary flow behavior.
l The use of Modified Coffin-Manson equation (MCME) as a figure of merit for
reliability projections seems to be adequate for most flip chip packaging electronic
applications, although not rigorously shown to be exact.
l The magnitude of the strain on underfill interconnects varies directly with joint
distance from the neutral point.
l Matching the CTE of the encapsulant to that of the solder provides the maximum
leverage to enhance C4 fatigue life.
l C4 time-to-failure is inversely proportional to the square of the joint plastic strain.
Use of this factor as a figure of merit is recommended for predicting reliability of
the underfilled interconnections.
l Properly underfilling flip chips will result in a very robust and reliable electronic
l Models that include energy per cycle or stress-strain hysteresis widths may offer
an alternative figure of merit to for bridging various environments.
l The competing risk approach to system reliability of underfilled flip chip offers a
simple natural method to forecast reliability.
l Cracks in the interconnections are present after ATC even without underfilled

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l Fatigue fractures occur in the interconnection without causing large joint
l It is imperative to generate data bases from which one can extrapolate to field
conditions. Theoretical models that attempt to bypass this step have not been
proven. Fatigue is to a large extent a statistical process, hence stochastic models
need to be contemplated.


The authors are indebted to Dr. M.Shatzkes for his pioneer work in the field of
electronic package reliability, to Mr. J.Carbin for technical discussions on underfills, to
Mr. B.Ciardella for the sponsorship, and numerous other people at Asymtek who
contributed to this paper.


[1] K.Beckman, A.Kolman, K.Puttlitz et al, "Solder Interconnection Structure for

Joining Semiconductor Devices to Substrates That Have Improved Fatigue Life,
and Process for Making," U.S. Patent 4,604,644 (Aug. 1986).

[2] H.M.Tong, L.Mok, K.Grebe and H.Yeh, "Parylene Encapsulation of Ceramic

Packages for Liquid Nitrogen Application," Proc. 40th Elec. Comp. Technol. Conf., 1
(May 1990), pp. 345-350.

[3] H.Quinones, "Flip Chip-BGA Packaging Workshop Proc.," Center for

Management Technology, Singapore, July 1996.

[4] M.C.Shine , L.C.Fox, and J.W.Sofia. "Strain-Range Partitioning Procedure for

Solder Fatigue," Proc. IEPS, pp. 346-359, 1984.

[5] S.S.Manson,"Thermal Stress and Low Cycle Fatigue," McGraw-Hill, NewYork,


[6] K.C.Norris, A.H.Lanzberg, "Reliability of Controlled Collapse Interconnections,"

IBM J.Res. Dev. 13(3), May 1969, pp. 226-238.

[7] H.Quinones, "3rd International Conference on Flip-Chip Technology, C4

Encapsulation Fatigue," Center for Management Technology, April 1997.

[8] Schwiebert, K.Matthew and W.L.Leong, "Underfill Flow as a Viscous Flow

Between Parallel Plates Driven by Capillary Action," Hewlett-Packard Company,
Electronic Assembly Development Center, Palo Alto, CA.

[9] A.R.Lewis, "Fine-tuning the Dispensing Process," Advanced Packaging,

May/June 1997.

[10] H.Quinones, K.Puttlitz, "Flip Chip Solder Interconnections: A Reliability

Perspective," Packaging Conference, Orlando Fl, 1996.

[11] H.Quinones, "Solder Cyclic Creep," Packaging IBM-ITL, 1987.

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[12] R.Tummala, Raimaszewski, "Microelectronics Packaging Handbook," Van

Nostrand Reinhold, New York, 1989, pp. 629-634.

[13] P.A.Tobias, D.Trindale, "Applied Reliability," Van Nostrand Reinfold, New

York, 1986, pp. 96-101.

[14] H.Quinones, M.Shatzkes, "Statistics of Crack Initiation and Propagation

SCRIP," MRS Proc., Spring 1994.

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