3.

“ A DevelopmentalIntrinsic-Barrier
Transistor”
W. C. HITTINGER
and R. M. WARNER,JR.
Bell Telephone Laboratories
The intrinsic-barrier design extends transistor frequency
range
withoutsacrificing
power-handlingcapacity. A
review of the design principles is presented, together with
adescription of a moderate-powerdevelopmental model,
the M1830. Aset of 156 M1830 unitswasrecentlymade
in the laboratory; 53 of these possessed measurable VHF
characteristics,anddiagramsarepresentedhereshowing
parameterdistributions for theseunits.Outputpower
determinationsweremade for 15 units(notnecessarily
thebestones of the group). Nine units gave morethan
20 milliwatts of sustainedusefuloutputat 200 mega-
cycles per second. The bestunitstudied indetailthus
far displayed an alpha of 0.88 at 100 cycles persecond,
ohmic base resistance of 106 ohms at 250 megacycles per
second, collector
capacitance of 0.2 micromicrofarads,
groundedbase cutoff frequency of 238 megacycles per
second,andoutput power of 30 milliwatts at 200 mega-
cycles per second.

p. “Recent Advances in Power Junction

Transistors”
B. N. SLADE
RCA Laboratories, Princeton
This paper will discuss experimental P-N-P and N-P-N
power transistors having low collectorleakage,
high
breakdownvoltageandhighcurrent gain. P-N-Ptransis-
tors have been made with d.c. current amplification factors
ashighas 140 at 1 ampere, collector leakage current on
the order of 20 microamperes and collector breakdown as
highas 200 volts. Thesecharacteristicsareattributedin
parttotheuse of specialjunctionalloysconsisting of
indiumandgalliumoraluminum.
N-P-N transistors having leakage and voltage breakdown
characteristics similar to the P-N-P transistors have been
madewith d.c. currentamplificationfactorsashigh as
200 at 1 ampere.An alloy of arsenic in lead is used for
boththeemitterandcollectorjunctions.
Other considerations in the design of power transistors
suchas baseleadresistance, emitter tocollectorpunch
through,andthermaldropwillbe discussed. Typical
characteristics of transistorsdesignedforClass B ampli-
fier useaswellashighvoltageswitchingapplications
willbepresented.

5. “Yacuum-Baking Encapsulation Techniques

and Improved Reliability of NPN Alloy
Transistors”
N. P. BURCHAM
and P. MILLER
Bell Telephone Laboratories
Otherinvestigators*havereported that improvedre-
liabilityfor NPN alloytransistorscanbeexpectedwith
vacuumbakingandvacuumencapsulation of the device.
Our pilotshopexperiencewithrelativelylargenumbers
13
of NPN alloytransistorshasdemonstratedthat vacuum
encapsulation does offer definitegains in reliability over
earliermethodsforencapsulation.Anextension of this
encapsulationtechnique involving employing a gettering
agentresultsinfurtherimprovementinthestability of
the device characteristicswith time.
Feasibility of use of theseencapsulationprocedures in
high level productionhasbeenachievedthroughdesign
of the high-vacuum station and the procedures associated
withitsoperation.
Details of theequipmentandprocessandplots of
transistor parameters versus time will be presented.

"A. J. Wahl and J. J. Kleimack, Bell Telephone Labora-

tories, atthe A.1.E.E.-I.R.E. transistorconference, Uni-
versity of Pennsylvania, 1955.

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