9 – Digital Logic Binary Counters, BCD Decoder for Display

-Static BCD to Seven Segment Display Decoder

-Binary Synchronous Counter: 8-bit
-HCMOS to LSTTL logic gate interface
-Open Collector outputs, tri-state outputs
-Driving non-logic output devices

Prototyping Breadboard
Dual channel Oscilloscope, with 10X probe
Function generator with TTL or CMOS output
DC adjustable power supply
74HC590 8-bit synchronous counter, with output latch
74LS47 BCD-to-seven-segment-display decoder
Seven-segment Light-emitting-diode digit display, common anode
1.8K resistors
Yellow Light-emitting-diodes
0.1uf or 0.33uf capacitor

Exercise a binary counter, driven from an external clock source. Exercise its
internal latch function, and its tri-state output function. Drive a 74LS47 BCD-to-seven-
segment decoder, that in turn drives a seven-segment LED display.

Review the 74HC590 counter data sheet. This is an eight-bit binary counter with extra
functionality added, so that it may be applied to a wide variety of counting applications with a
minimum of extra “glue” logic gates. The extra functions (such as output latches) should be
disabled, to see dynamic counting. From the data sheet on page 2, the BLOCK DIAGRAM shows
that the basic counting function involves:
• Eight D-type flip-flops
• Clock input CCK, increment counter on positive-going edge transitions
• NOT_CCLR Active-low reset that forces all flip-flops to the “0” state on their Q outputs
• NOT_CCKEN Active-low enable – when low, allows CCK to increment the counter.

The extra latch and tri-state functions involve the two pins:
• RCK On positive-going edge, transfer current flip-flop count value to output pins
• NOT_G Active-low tristate. When low, drive output pin. When high, output pin is high-
impedance.
NOT_RCO Ripple-carry counter output. Used to cascade counter chips for larger count values
that require more than eight flip-flops.

Set a D.C. power supply to give 5.0 volts output. Turn the current set point down so that
even with a short circuit, less than 40 mA current will flow. Setting the current limit this way may
protect circuitry from destruction should you make a wiring mistake. Although the 74HC590 will
accept supply voltages between 2.0 and 6.0 volts, the LSTTL decoder requires Vcc=5.0v within
10%.
Connect the counter as shown below. You may drive as many display light-emitting-
diodes at the “Q” outputs as you like. Four should be sufficient to show the count sequence. Set
the function generator’s TTL output (or CMOS output) to a frequency below 10 Hz. Note that in
order to see counter outputs, the input pin NOT_G must be tied low. Determine whether
NOT_CCLR should be tied low or high, for the counter flip-flops to count up from zero.
 LED

1.8K +5.0v

QA QB QC QD QE QF QG QH
CCK Vdd
TTL ? RCK
or G CCLR CCKEN Vss
CMOS

?
Counter flip-flop Q outputs are not available to probe directly, they must propagate through the
output latch flip-flops (and then through the tri-state driver) to their respective output pins.
If you tie RCK low, the output state will not change. If RCK is tied high, output state
will not change. Only when RCK changes from low-to-high will the counter state propagate to
the output pins. Where should RCK be tied to dynamically see the counter flip-flops count?

Satisfy yourself that this is a binary counter. Counting should agree with the following sequence:
Binary Hexadecimal Decimal
0000 00 00
0001 01 01
0010 02 02
0011 03 03
0100 04 04
0101 05 05
0110 06 06
0111 07 07
1000 08 08
1001 09 09
1010 0A 10
1011 0B 11
1100 0C 12
1101 0D 13
1110 0E 14
1111 0F 15
Which of the eight “Q” outputs of the counter corresponds to the most significant bit of the table
above (the leftmost binary digit), under the Binary heading ________?
In the free space above, show the Binary output state of QA, QB, QC, QD, QE, QF, QG,
QH for Hexadecimal counts from 0F to 22.

Connect an oscilloscope probe to the QH output (pin 7). Turn the function generator clock
frequency to fin=100KHz. You should see a square wave: find its frequency f=__________Hz.
Calculate the ratio 100000 / f. To which power-of-2 is this closest (2x)? x=_______.
Which better describes QH output: the ratio 100000 /f, or 100000 / (2x)?

Find the power-of-two for each of the other seven Q outputs of this counter
QA:______, QB:______, QC:______, QD:_______, QE:_______, QF:______, QG:_______.

You can “clock” this counter by hand. Add a pull-up resistor from CCK to Vdd. Any resistor
value will be acceptable. Momentarily ground the CCK pin to Vss with a wire. As you release the
grounding wire, CCK input pin should see a rising clock edge to advance the counter by one
count. Does the counter follow the same binary sequence as it did with the function generator?
Experiment a few times, and explain the count sequence that you see.

LED

1.8K +5.0v

QA QB QC QD QE QF QG QH
CCK Vdd
? RCK
G CCLR CCKEN Vss

Seven Segment Decoder

The 74LS47 chip accepts four BCD-encoded TTL-compatible inputs and delivers seven
outputs meant to drive a display showing any one of ten decimal digits (0.1.2.3.4.5.6.7.8.9). Note
that the seven outputs are not strictly TTL-compatible. Outputs are designed to sink much more
current to ground (up to 24mA) than standard TTL, but outputs are not designed to source
current. Output voltages may be allowed to rise far above Vcc (5.0v) – as high as 15 volts. This
output driver is sometimes called open-collector, rather than TTL.
The decoding logic assumes that when an output sinks current to ground, its display
segment will light, as indicated by an “on” or “low” state. No current will leave a segment un-lit,
as indicated by an “off” or “high” state. This “off” or “high” of seven-segment outputs should not
be equated to a TTL logic “high” state.
Why is this chip is called a “decoder” rather than an “encoder”?

Seven-Segment LED Display

This device is NOT an integrated circuit. It contains seven discrete LEDs (light-emitting-
diodes) on a small printed circuit board. Like any LEDs, light output is proportional to forward
current. All LED anodes are tied together (common anode). Each LED cathode comes out to an
individual package pin. With about 1 mA. current flowing through an LED, a voltage drop of
about 2.0 v will be measured from anode to cathode. One milliamp DC current is sufficient to
give discernable light output.
A series-connected resistor is needed to limit LED current flowing from Vcc (5.0v),
through LED, to 74LS47 output (assuming the output is “on”). From the 74LS47 data sheet,
estimate the “on”state output voltage, with 1 mA. current flowing Vo=_____________v

Calculate what series resistance is required Rs=__________ohms

Find in the lab seven resistors having a value closest to Rs. Connect each LED cathode through a
series resistors to its appropriate output pin of the 74LS47 decoder. NOT_LT and NOT_RBI
inputs of the 74LS47 should be tied high.
Test the decoder by running through ten states of the four BCD input pins. Observe that
the seven-segment display shows an appropriate number for each BCD input state.

Now connect the four BCD inputs to consecutive outputs of the 74HC590 binary counter. Clock
the 74HC590 with a function generator, at a frequency of about 1 Hz. Verify that the display
shows the consecutive count sequence found in the 74LS47 data sheet. (0 –15)
1 +5.0v a
Seven
f b
Segment
LED display g
e c
10 9 8 5 4 2 3 7
d
Rs x 7

a b c d e f g Vcc LT
74LS47 RBI
A B C D GND

QA QB QC QD QE QF QG QH
CCK 74HC590 Vdd
TTL ? RCK
or G CCLR CCKEN Vss
CMOS

?
Increase the generator frequency up to 100KHz. What display do you see? Why?

Note that this circuit mixes two logic families: HCMOS, and LSTTL. Observe the logic levels at
one of the four counter outputs (or decoder inputs). Measure the high state and low state voltages.
Do these comply with the acceptable high and low input logic levels on the 74LS47 data sheet?
Vhigh (measured) __________v Minimum high voltage (data sheet) _______________v
Vlow (measured) ___________v Maximum low voltage (data sheet) _______________v

Calculate noise immunity voltage for these two states

Noise immunity, high state __________v
Noise immunity, low state __________v
Use standard LSTTL input high and low voltage range, compared to output high and low voltage
range as a benchmark guide for “acceptable” noise immunity. Would you say that driving LSTTL
inputs from HCMOS outputs this way, is acceptable engineering practice?

Tri-state
Counter latches are connected to “Q” output pins through tri-state drivers. You can think
of these gates as buffers: the logic output state is the same as the logic input state. But the output
can also be disconnected from its input, depending on the state of the NOT_G pin.
When NOT_G is pulled high, the eight 74HC590 output pins are left floating, meaning
that no current flows into or out of the pin. This third state is sometimes called high-impedance
state or high-Z state.
When NOT_G is pulled low, the Q output pin is connected to the latch Q output. The
output pin is driven high or low, depending on the logic state of its latch. All eight tri-states are
driven from the same NOT_G pin – all eight outputs are high-Z (when NOT_G is high) or all
eight outputs are connected to their respective latch Q (when NOT_G is low).

Many tri-stated chips may be wired together, with all their outputs on a common bus.
Only one of these chips should have its NOT_G pin tied low – should two or more chips have
their bus-enabling pins active at the same time, you’d have a bus fight, where the output pin of
one chip may be trying to pull high, while the other output pin tries to pull low at the same time.

For all the procedures above, NOT_G was active (tied low). Pull NOT_G high and observe the
seven-segment display. Which of the fifteen output states does the 74LS47 go to? ____ Why?