INTEL UNIVERSITY VLSI BOOTCAMP 2021

SMART CAR SYSTEM

1 High Level Overview

The objective is to design a SoC (System on Chip) for vehicle monitoring system that provides
various indications to the driver to aid vehicle maintenance, as well as enabling real-time driver-
assistance system.

2 Design Requirements
The Smart Car System SoC must include at least the following features in Section 2.1 (but not
limited to) that would be able to perform start-up condition check before allowing engine to
ignite, decide any follow-up actions required and allow driver to activate at least one driver
assistance feature in Section 2.2 (but not limited to) while driving. Designer is free to add in
any inputs or outputs that are required for your design.

2.1 Perform start-up condition check before allowing engine ignites

2.1.1 Buttons
• START/OFF button to ignite and power off engine.

2.1.2 Fuel Level

• System is able to detect fuel level.

2.1.3 Engine Oil Level

• System is able to detect engine oil level.

2.1.4 Tyre Pressure

• System is able to detect tyre pressure.

2.1.5 Battery Voltage

• System is able to detect battery voltage.

2.1.6 Driver Alert (LED / alarm / etc.)

• System is able to warn / display to driver if any conditions / acceptable limits are not met.

2.1.7 Memory
• Store data obtained from the inputs and read the data for any condition checking or
features enabling.
2.2 Driver-assistance systems while driving
The system should at least include one driver-assistance feature during driving. Designer is free
to create any features out of the list. Few examples are as below:

• Safety belt warning

• Blind spot obstacle detection and warning
• Pedestrian detection and alert
• Driver drowsiness alert
• Handsfree auto parking
• Fuel efficiency calculation
• Line following assist

3 Challenge
This challenge would require each person to know the flow of the system from the system being
switched on until the vehicle is in motion and the driver-assistance function is activated. The
subsections in the challenge section are parts that would form the whole picture of the system
/ SoC including the details on the implementations. Complete all 7 challenge subsections (3.1
– 3.7).

3.1 Block Diagram

The block diagram below is an example without any internal blocks. Define all the possible I/O’s
(if the I/O depicted in the diagram below is possibly complete then it is not needed to add any),
insert the internal IP design blocks and show how each of them are related to the inputs,
internal blocks, and outputs.

reset
Ignite_engine

Fuel Level

Alarm
Tire Pressure
LED Indicator
Engine Oil Level

2
3.2 Subsystem / IP Design Blocks
Identify the necessary IP designs and describe their functions. Two subsystems are defined
below. Complete the rest of the subsystems and their description below.

Subsystem/Module Description
Main Controller Controller for the smart car system.
Fuel Adapter to obtain the fuel level from sensor.

3
3.3 Interface Signals List
Define the I/O signal interfaces of the SoC. Several signal interfaces are listed below. Complete
by adding more signal interfaces and their description below.

Signal Direction Description

reset Input Reset the SoC during powerup.
0: not reset, 1: reset
ignite_engine Input User input to ignite car’s engine.
1: ignite trigger, 0: N/A
fuel_level Input 8 bits indicating from empty to full
8’h0: empty, 8’hff: full

4
3.4 Control Registers List
Define all the control registers to be used to control the states of the SoC. One of the control
registers is described as follows. Complete by adding more registers and their description.

1. FUEL_STATUS
Field Name Bit Type Reset Value Description
SENSOR_RDY 8 RO 0 Indicates sensor ready.
LEVEL 7:0 RO 0 8 bits indicating from empty to full.
8’h0: empty, 8’hff: full

5
3.5 Controller Implementation
The controller description is described in section 3.4. Draw a Finite State Machine (FSM) of the
controller implementation.

6
3.6 System Validation Test Plan
List down 3 directed and 3 random test conditions that should be added to the test plan.
Example is numbered zero.

0. Smart Car System IP timeout testing: de-assert reset and check if timeout occurs if 1 IP isn’t
ready by 1ms.

Directed Test

1.

2.

3.

Random Test

1.

2.

3.

7
3.7 DFx Implementation
1. Based on your design, list the DFT features required to be implemented in your design?
The features added must be able to allow defect screening for ALL the elements of the
design.
2. Apart from DFT features, are there any DFD features that can be added into your design to
ease the debugging process?
3. Based on your answer(s) in Question 1 & 2, are there any additional I/O interfaces needed
in your design to enable the aforementioned DFx features?
4. Based on your answer(s) in Question 1 & 2, briefly explain each of the DFT & DFD features.
You may use tables or diagrams to illustrate the feature implementations.
5. In your opinion, what are the possible ways that can help to improve the speed of testing
of a design?

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Challenges in life are doorways for improvements.