Detection of Wiring Interconnect Faults

using Boundary Scan Architecture

Pankaj Kumar1, Abhishek Singhal2, R. K. Sharma3 and Vikesh Kumar4,
1,2,4
Department of Electronics and Communication Engineering, Vidya College of Engineering, Meerut
3
Department of Electronics and Communication Engineering, National Institute of Technology, Kurukshetra
(E-mail: pankaj.kumarnkr@gmail.com; abhishek.vce.in@gmail.com, mail2drrks@gmail.com; vikeshmca@gmail.com
bkk23fec@iitr.ernet.in)

Abstract- Miniturization trends in Integrated Circuits caused
many testing problems in PCB Board. This limits the use of
traditional in-circuit test techniques for testing of such boards.
This paper proposes a new approach to test PCB Board level
wiring Interconnects using Boundary Scan architecture. This
work implements BIST using Boundary Scan technique. The
Proposed Algorithm is developed to diagnose dominant-1
(WOR), dominant-0 (WAND) and stuck-at faults . This algorithm
is also compared with the existing algorithms viz modified
counting, walking one’s algorithm and others. Our results are
found to be better than the existing algorithms.
Keywords- Boundary scan, BIST, TPG, PCB, Faults.
I. INTRODUCTION
which Inputs/Outputs (I/Os) of the device under test are easily
controllable and observable [7,8,9]. The Boundary Scan
architecture is shown in Fig.1 [1].
The Boundary Scan Cells are inserted into the logic core
and I/Os as in Fig. 1 [10]. The major components of Boundary
Scan Architecture are Boundary scan cells, Instruction
register, Test Access Port (TAP), Bypass register, Data
register, Test Data in (TDI) and Test Data out (TDO). TDI is
an input pin through which the test data is passed to the first
boundary scan cell. TDO is an output pin of the last
bidirectional boundary scan cell through which test data is sent
out from the circuitry. Bypass register is a one bit register
which is used to bypass the test data.

Testing of PCB is essential to test the interconnections and

components mounted on it [1, 2]. In 1960, testing was done BS Cell BS Cell
manually. But with the development of the integrated circuit
I/O I/O
(IC) the complexity of the circuit reaches to its peak level
which further increase the testing time of manual process. So BS Cell ASIC BS Cell
it will become very difficult to test the integrated circuit
manually. At that time, the essential requirement is to test the
IC’s quickly [3]. So for reducing the testing time and to make BS Cell BS Cell
the testing labor free, Testing at circuit level is done using
ATE (Automatic Test Equipment) which is also known as an Data Register
external tester [4]. But with these advantages ATE have some TDI TDO
limitations too. First limitation is that as the integration level is Bypass Register
changed from SSI to LSI the cost of testing with ATE became M
U
X
extremely high. Second limitation is that it is unable to
Instruction Register
provide the pointer as to where the problem lay. Third
limitation is that at LSI level ATE increase test application
time also. Control Signals

In the mid of 1970’s, the testing of boards were carried

TCK
out with in-circuit testing. Testing is done with fixture
containing the bed of nails. SMT (surface mount technology) TMS
and DIP (dual in package) create further difficulty to test
TRST

interconnects on board [5].
In order to remove the problem of testing, a group of 200
scientists came together to form the Joint Test Action Group
(JTAG) in mid 1980. In 1990, JTAG recommends Boundary
Scan based DFT (Design for Test) Technique which is known
TAP
Fig. 1. Boundary Scan Architecture
TAP controller is a 16-state finite state machine. It
controls all the operations done by the boundary scan

Controll
as IEEE 1149.1 standard [6]. Boundary Scan cell is the basic architecture. TAP controller takes the decision which
building block of boundary scan test architecture through instruction should be the current instruction [11]. More than
 one chip under test can be tested in parallel using boundary testing which is widely used in industry as it is more
scan, where all chips have a single TDI, TDO, TCK and TMS Controllable and Observable but serial access mechanism of
[12]. the flip-flop increases the test application time [25] and the
Scan flip-flops also take more power during the process of
Boundary scan cells play no role in normal
scan shifting which is the main limitation of this technique
mode of operation because data is bypassed from scan cells
[26]. This paper is divided into seven sections. In section II,
whereas in case of testing mode, serial test data is passed
different types of faults are discussed. In section III, existing
through the scan cells. When boundary scan cells are
test algorithms are covered. In section IV, we have discussed
connected in a chain, it forms boundary scan register [1].
our proposed algorithm to test board level interconnect faults.
Standard Boundary Scan Cell is shown in Fig. 2 [7]. Boundary
Implementation of algorithm is taken up in section V,
scan cell works in four modes. In capture mode, test data is
comparison of our algorithm with existing algorithms is done
captured by the boundary scan cell. In Shift DR test, data is
in section VI and conclusion is given in section VII.
shifted through the cell. In Update mode, new test data is
applied to the boundary scan cell [13]. In normal mode, data is II. FAULTS
bypassed from scan cells. All the modes of boundary scan cell
are dependent on the clock. Clock and TRST (Test-Reset)
In circuit testing, fault is a major topic of interest.
signals are applied in parallel to the individual PCBs [14].
Interconnect faults may be introduced due to etching, shorting
Boundary scan takes less time for testing depending upon the
between two wires and an open within wire. Faults can also be
complexity of the circuit. Furthermore, some circuit nodes
introduced if any one of component is missing from the
connecting two or more BGA (Ball Grid Array) pins may
complete PCB. The faults are classified as Multi-net faults and
never have surface to test so it makes boundary scan the only
Single-net faults.
way of quality testing [15]. So now a day, Industry used IEEE
1149.1 Boundary Scan standard mostly to test the heavily A. Multi-net Faults
loaded printed circuit board as this method is cost-effective
and have no need of physical probing [16-20]. Multi-net faults are those faults which occur in multiple
wires when a short takes place between any two wires. These
Parallel Data In faults are also known as bridging faults.
To illustrate the modeling of bridging faults or multi-net
faults, consider two wires denoted as A and B at signal source
0 end and A´ and B´ at signal destination end with a resistive
0 short between the two wires as shown in Fig. 3.
1
1 ’
Data A A
SDI 1
Out
SDO Resistive short

B ’
B
Fig. 3. Bridging fault
D Q D Q
There are two bridging fault models that are frequently
Mode_Control
Shift_DR used in practice i.e. the wired-AND and wired-OR bridging
fault models.
Capture_DR Update_D
R The wired-AND model (also denoted as WAND) is
Fig. 2. Boundary Scan Cell sometimes referred as a dominant-0 bridging fault since a ‘0’
on either wire results logic ‘0’ at output of both the wires [8]
as shown in Fig. 4.
Boundary scan itself can not do quality testing of the
complete PCB. For enhancing the PCB level testing, other
testing methods such as ICT (In-Circuit Test), FT (Functional A ’
A
Test), MDA (Manufacturing Defect Analyzer) are used [21]. A dom B
Some other techniques used are IDDQ and Scan based [22].
IDDQ technique is an effective testing scheme for detecting the B ’
B
bridging faults [23]. In IDDQ testing, there is no requirement of
passing the effect of fault to the output, the only requirement is Fig. 4. Dominant-0 fault
to trigger the fault. But one limitation of IDDQ is that it takes
more time to test [24]. Another testing technique is Scan based

Wired-OR (also denoted as WOR) is sometimes referred
as a dominant-1 bridging fault. In this type of fault, any wire A
or B which have logic ‘1’ will dominate the logic value of
other wire as shown in the Fig. 5.
A A
’
A A
B dom
’ shorted then the response of these nodes is same as
B B
Fig. 5. Dominant-1 fault
B . Single-net Faults
Counting sequence algorithm is developed by Kautz as shown
in Table 1.1 [28]. It consists of [log (n)] parallel test vectors
sufficient for a network consisting of N connected terminals.
However this method of testing interconnects faults has
the following drawbacks.
1) Aliasing Syndromes: This type of problem occurs if
two nodes, when shorted together produce the same
response as the response of any other node. As an
illustration in Table 1.1 [8], if node N2 and N3 are
the response of N4 node. Thus, it is impossible to say
when a short occurs, whether N2, N3 and N4 are
shorted together or whether only N2 and N3 are
shorted in case of dominant-1 type of faults.

Single-net faults are those faults which occur in single
wire. These faults are also known as stuck-at faults.
Stuck-at fault model allows the wire inputs and outputs to
be either stuck-at-0 or stuck-at-1. But, it is not necessary that
to have a hard wired connection between a wire and reference
voltage in case of stuck-at-1 fault. Similarly, it is not
necessary in case of stuck-at-0 fault to have a short between a
wire and ground [27].
In suck-on fault, the input or output of the faulty wire is
stuck-at-1 or stuck-at- 0. The stuck at logic value will not
change by changing the nets input.
When stuck-off fault occurs, the output end of the net
remains at logic ‘0’ / logic ‘1’ depending upon parasitic
capacitance because the logic values applied at input net
cannot passed to the output net due to the break with in a wire.
Stuck-off fault is detected by applying 1-0 (0-1) at the input
end and analyzing the output response of the wire [8].
III. EXISTING TEST ALGORITHMS
2) Confounding Syndromes: This occurs if two nodes,
when shorted together produce response equal to the
response of any other two nodes when shorted
together. For example, N2 and N3 when shorted,
produce the pattern “0011”, which is same pattern,
received when N1 and N4 are shorted. Thus, when
this pattern occurs, it is impossible to judge whether
all four are shorted together, or whether only one of
the pairs is shorted together
3) 3) The main drawback of this algorithm is that it
can not test stuck-at-1 and stuck-at-0 type of faults as
the test vectors proposed in this algorithm at Nodes
N1 and N8 contains all 0’s and all 1’s [29].
B. Modified Counting Sequence Algorithm
Table 1.2: Sample Test set created by Modified Counting Sequence Algorithm
Parallel Test Vectors Sequential Test
Vectors
Nodes T1 T2 T3 T4

N1 0 0 0 1 V1
In this section, we have discussed briefly five existing
N2 0 0 1 0 V2
algorithms by which we can detect stuck-at, wired-OR and
wired-AND types of faults. N3 0 0 1 1 V3

N4 0 1 0 0 V4
A. Counting Sequence Algorithm
N5 0 1 0 1 V5
Table 1.1: Sample Test set created by Counting Sequence Algorithm
N6 0 1 1 0 V6
NODES TEST VECTORS N7 0 1 1 1 V7
T1 T2 T3
N1 0 0 0
N2 0 0 1 The problem of testing stuck-at faults is no more in
N3 0 1 0 Modified Counting Sequence algorithm. As the every test
vector in this algorithm contains at least one ‘0’ and one ‘1’.
N4 0 1 1
Modified Counting Sequence Algorithm allows Stuck-at type
N5 1 0 0 fault testing This algorithm was proposed by Goel et. al. [30]
N6 1 0 1 as shown in Table 1.2. They have modified Counting
Sequence algorithm by extending sequence test vector (STVs)
N7 1 1 0
to [log (N+2)] parallel test vectors (PTVs). Modified Counting
N8 1 1 1
sequence algorithm [8, 31] is used for testing the interconnect However this method of testing interconnects faults
faults. has the following drawbacks.

However this algorithm has the following drawbacks. 1) This algorithm have the problem of Confounding
syndromes as discussed above which can be seen analyzing
1) Aliasing Syndrome: This type of problem occurs if two the nodes N6, N8 and N4, N10.
nodes, when shorted together produce the same response as 2) The number of test vectors used by this algorithm is
the response of any other node. As an illustration, in Table 2.1 more. So this algorithm takes more time for testing the PCB
[8], if nodes N1 and N2 are shorted together, then the response level interconnects.
of these nodes is same as the response of N3 node. Thus, it is
impossible to say when a short occurs, whether N1, N2 and D. Walking One’s Sequence Algorithm
N3 are shorted together or whether only N1 and N2 are
shorted. The problem of confounding syndrome presented in the
True/Compliment test and diagnose algorithm is overcome by
2) Confounding Syndrome: This occurs if two nodes, when using Walking One’s Sequence algorithm [8] because the
shorted together produce response equal to the response of any pattern are designed in such a way that any short between
other two nodes when shorted together. For example, N3 and nodes results in an output pattern precisely identified which
N4 when shorted, produce the pattern ‘0111’ which is same nodes are shorted together. As an example, in Table.1.4, if
pattern received when N5 and N6 are shorted. Thus, when this Node N5 and N7 are shorted together the output pattern is
pattern occurs, it is impossible to judge whether all four are “0000101” which have ‘1’ at 5th and 7th position and shows
shorted together, or whether only one of the pairs is shorted that wires of nodes N5 and N7 are shorted together. Thus in a
together. fault free case, the output response of the given test vector
consists of a single one whereas in faulty case, the output
C. True/Complement Test and Diagnose Algorithm response of the given test vector consists of multiple one’s
This algorithm is developed by P.T. Wagner [32] to Table 1.4: Sample Test set created by Walking One’s Sequence Algorithm
remove the problem of aliasing syndrome which is present in Test Vectors
previously discussed algorithms. The total number of test Nodes
T1 T2 T3 T4 T5 T6 T7
vectors used by this algorithm is 2[log (N+2)] which is double N1 1 0 0 0 0 0 0
of test vectors used by the previous algorithm as shown in
N2 0 1 0 0 0 0 0
Table 1.3. The additional [log (N+2)] test vectors are obtained
by complimenting the first set of test vectors. This algorithm is N3 0 0 1 0 0 0 0
capable to diagnose all types of shorts rather than the shorts N4 0 0 0 1 0 0 0
which have the problem of confounding syndrome.
N5 0 0 0 0 1 0 0
Table 1.3: Sample Test set created by True/Complement Test and Diagnosis N6 0 0 0 0 0 1 0
Algorithm
N7 0 0 0 0 0 0 1
Nodes True Vectors Complement Vectors
N1 0 0 0 1 1 1 1 0
This algorithm is used for testing dominant-1 (WOR) and
N2 0 0 1 0 1 1 0 1
stuck-at faults in interconnects.
N3 0 0 1 1 1 1 0 0
N4 0 1 0 0 1 0 1 1 However, inspite of having advantages of no syndromes,
N5 0 1 0 1 1 0 1 0
this algorithm has its limitations that it requires more test
vectors to test the interconnect faults. Therefore, this algorithm
N6 0 1 1 0 1 0 0 1
takes more time to test interconnects.
N7 0 1 1 1 1 0 0 0
N8 1 0 0 0 0 1 1 1 E. W-Test Adaptive Algorithm
N9 1 0 0 1 0 1 1 0
W-Test Adaptive Algorithm is proposed by Goel and
N10 1 0 1 0 0 1 0 1
McMohan to reduces the walking one’s Algorithm. It is a two
step algorithm with a combination of Modified sequence
As an illustration, as shown in Table 4.3, in the true Algorithm and Walking one’s sequence Algorithm. In the first
test set, if nodes N3 and N4 are shorted, the response of these step of W-test algorithm Modified counting algorithm with
nodes are same as the response of Node N7. But in case of [log (N+2)] test vectors as discussed above is applied to the
complement test set, the response of the shorted nodes N3 and nets for interconnects testing. After analyzing the output
N4 is completely different from the response of node N7. response of the Modified counting algorithm we identifies the
Therefore, this algorithm completely removes the problem of nodes which have same output response it is due to the
aliasing syndromes [32]. shorting, aliasing syndromes and Confounding syndromes. So
in the second step of the algorithm to detect the actual faults
we apply the walking one’s sequence algorithm to these faulty
nodes. So W-test adaptive algorithm limits the walking one’s
algorithm up to the faulty nodes. Finally the total number of
test vectors used by W-test algorithm are W+[log(N+2)] V. IMPLEMENTATION OF ALGORITHM
Parallel test vectors. Where W is the number of the faulty nets
and N is the number of total nets. So with this algorithm a We have used Verilog on Active-HDL to implement our
quality diagnosis of the shorts takes place very easily [30, 34]. proposed algorithm and to generate test vectors as shown in
Fig.8. The result shows that the proposed algorithm is simpler
and has no problem of Aliasing Syndromes and Confounding
Syndrome as the previously discussed algorithms have these
IV. PROPOSED ALGORITHM
problems.
In this paper, we have developed an algorithm which is
used for testing dominant-1, dominant-0 and stuck-at faults
between interconnects of two nodes. The proposed algorithm
can easily diagnose which two wires are shorted. We can
easily determine the actual position of the dominant-1,
dominant-0 and stuck-at faults on the basis of the output
response available at output Boundary scan cells. The output
response of each shorting between different wires of different
node is different which forms the basis of fault detection.
The developed test vectors of the proposed algorithm are
shown in Table 1.5, which are generated by the TPG. Test Fig.8 Test pattern Generator
vectors of the proposed algorithm are unique and it gives
quality diagnosis of dominant-1, dominant-0 and stuck-at For testing dominant-1 type of fault, we apply unique test
faults when it is applied as an input to the different nodes of vectors to each node at the time of testing. If any type of the
the wires. The output response of the applied test vectorare syndromes occurs for testing the any pair of nodes then it will
completely free from the problem of the syndromes. become very difficult which pair of nodes became short. To
remove this problem complement Test vectors are used instead
Table 1.5: Sample Test set created by the Proposed Algorithm
of True test vectors. The output response of these test vectors
Nodes True Vectors Complement Vectors
will be completely free from any type of the syndromes,
N1 0 1 1 1 1 0 0 0
N2 1 0 1 1 0 1 0 0 VI. COMPARISON WITH EXISTING ALGORITHMS
N3 0 1 0 1 1 0 1 0
N4 0 1 1 0 1 0 0 1 The first advantage is the absence of syndromes at the
output of the shorted nets which is the drawback of Counting
N5 1 1 1 0 0 0 0 1
Sequence, Modified Counting sequence and True/Complement
N6 0 0 1 1 1 1 0 1 Test and Diagnose algorithms.
N7 1 0 0 0 0 1 1 1
The second advantage is that the test vectors are generated
internally, so BIST is implemented using boundary scan.
This technique requires 2[log(N+2)] test patterns. The The third advantage of our proposed algorithm is that it is
additional log(N+2) test vectors are obtained by also used for testing stuck-at faults which is not possible in
complimenting the first set of test vectors. case of Counting sequence algorithm.
The fourth advantage of our proposed algorithm is that it is
for example In case of true test vectors, if nodes N3 & N4
single step algorithm whereas W-test adaptive algorithm is
becomes short then the output response of these nodes
two step algorithm which takes more time in testing.
becomes equal to ‘0111’ which is same as the output response
of Node N1 . So we can not detect wether N1N3, N3N4 or One limitation of our algorithm is that the faults on any six
N1N4 are shorted.To identify this we use complement Test nodes can be tested simultaneously to avoid aliasing. So we
vector for the node pair N3, N4 and N1. The ouput response of can make the groups of total nodes in a multiple of six.
these nodes in case of complement test vector is completely
different and free from the problem of Aliasing syndrome and
Confounding syndrome.

VII. CONCLUSION
The problems and the complexities of board level interconnect
testing are addressed in this paper. With the increasing
component density in IC’s and the increasing number of IC’s
on printed circuit boards, the number of interconnects on the
boards have increased tremendously. Apparently,
interconnects are simple electrical wires running in parallel to
each other. But in reality, the problems in interconnect testing
are no simpler than the problems of testing the circuitry inside
IC components. It is shown that one of the main problems in
board level interconnect testing is that of test point
accessibility. Boundary scan architecture proposed by Joint
Test Action Group (JTAG) is an efficient framework to
provide electronic access to interconnect test points. This
dissertation addresses the interconnect testing problem in the
context of boundary scan architecture. Several schemes are
proposed in the literature for testing different types of
interconnect faults. These schemes have advantages and
disadvantages. The problems of existing testing algorithm are
removed in our proposed algorithm.
The board level faults have been tested by our developed
algorithm using Boundary Scan technique and it is shown that
the results are better than the existing algorithms. The
dominant-1, dominant-0 and stuck-at faults can be tested by
our algorithm. The demerits of existing algorithms are no
longer present in our proposed algorithm. One limitation of
our algorithm is that the faults on any six nodes can only be
tested at a time to avoid aliasing.
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