Core architecture doubles
mem data rate
By Todd Farrell
Sr. Technical Member
Micron Technology Inc.
Double data rate, high-speed
CMOS SDRAM products are
evolving. By the end of 2007,
DDR3 SDRAM will be intro-
duced into PC desktop and
notebook products. By 2009,
DDR3 SDRAM is expected to be
the PC industry’s mainstream
memory device.
The initial performance tar-
get for DDR3 eclipses the data
rate of DDR2 SDRAM. At 800-
1,067Mbps, DDR3 will give
twice the performance of its
predecessor. By 2009, the gains
will be even greater: DDR3 will
be capable of reaching a data
rate of 1,333-1,600Mbps. To
achieve twice the data-rate
performance of DDR2 while
maintaining a reasonable cost
structure, DDR3 has been
enhanced with new signaling
features.
To achieve increased data
rates over DDR2 SDRAM, the
DDR3 SDRAM core architec-
ture doubles the internal data
prefetch from 4n-bit wide trans-
fers to 8n-bit-wide transfers. A
single read/write access consists
of a single 8n-bit-wide, one-
clock-cycle data transfer at the
internal DRAM core and eight
corresponding n-bit-wide, one-
half-clock-cycle data transfers
at the I/O pins. In DDR3-800
SDRAM, the core array only
needs to operate at half the
data-rate frequency. However,
increasing the prefetch to 8n
increases the die size because
the internal I/O paths are
doubled. With half the data rate
frequency, but twice the I/O
paths, a DDR3-800 SDRAM
has the same core frequency as
a DDR2-400 device.
In addition to core frequen-
cy, DDR2 and DDR3 SDRAM
will share a similar migra-
tion path. DDR2 SDRAM was
defined with 256Mb 4-bank
devices at its inception, had
Figure 1: Multiple 240Ω structures enable pull-up and pull-down drivers.
512Mb 4-bank and 1Gb 8-bank
devices added for mainstream
production, and was eventually
developed with 2Gb 8-bank de-
vices for high-capacity memory
systems. DDR3 SDRAM is ex-
pected to be introduced with a
1Gb density, have 2Gb devices
added during production, and
end with a 4Gb density.
Like DDR2 SDRAM 1Gb and
2Gb devices, DDR3 SDRAM
uses eight banks and has a re-
duced page size of 1KB for the
x4 and x8 configurations (2KB
for the x16 configuration).
Since the x4 and x8 configura-
tions are common in larger sys-
tems containing many devices,
the reduced page size helps
minimize activation current
when banks are opened for
read/write access. Although
the larger page size of the x16
devices uses more activation
current, most applications that
use this device configuration
typically have fewer devices in
the system.
The supply voltage for DDR3
SDRAM has been reduced to
1.5V—a 16.5 percent reduc-
tion over the 1.8V of DDR2
SDRAM. Although the volt-
age-reduction percentage is not
as large as it was in the transi-
tion from DDR to DDR2, a 28
percent reduction, the 1.5V
operation will have power-
saving advantages. In lower-
data-rate applications such as
mobile computing, power is
valued over performance and a
16.5 percent reduction is sig-
nificant. To minimize system
power-supply costs, the supply
tolerance requirements have
been reduced slightly from ±5.5
percent in DDR2 SDRAM to ±5
percent for DDR3 SDRAM.
Signaling overview
DDR3 SDRAM I/O signaling
is based on a 1.5V stub-series
terminated logic (SSTL) inter-
face and uses a center-tapped
termination (CTT) bus struc-
ture, similar to DDR2 SDRAM.
DDR3 SDRAM input receiver
characteristics are enhanced
by reducing the input voltage
threshold levels required to al-
low DDR3 SDRAM devices to
operate at lower voltage swings.
Input voltage levels are refer-
enced to a midlevel V DDQ/2
voltage (Vref) for logic-high and
logic-low conditions, similar to
DDR2 SDRAM’s single-ended
signals. Data capture is also
similar, using a bidirectional,
source-synchronous data strobe
for each byte lane. However, the
DDR3 SDRAM data strobe is a
differential pair (DQS, DQS#)
and does not support a single-
ended version.
Table 1 compares DDR2
and DDR3 SDRAM supply and
signaling levels.
Merged driver
DDR3 SDRAM drivers have
been enhanced with a capaci-
 a common impedance ratio
between the 18Ω output driver
and the termination values of
150-, 75- and 50Ω, which were
optimal for DDR2 SDRAM
systems.
Decreasing the capacitance
is a key bandwidth enabler for
DDR3 SDRAM systems. The
DDR2 SDRAM capacitance
(max) specification is 3.5pF
for DDR2-667 and DDR2-800
devices. The DDR3 SDRAM
merged driver is capable of
achieving 2.5pF for the DDR3-
1333 device, which is a 40
percent reduction. A typical
DDR3 SDRAM desktop with an
achievable memory footprint
and performance target has two
dual-rank UDIMM modules per
memory channel at a data rate
of up to 1333Mbps.
Turning on the pull-up and
pull-down legs in parallel en-
ables termination values. When
pull-up and pull-down legs are
enabled, a Thevenin equivalent
termination value is created,
which is optimal for the CTT
bus structure. Figure 2 pro-
vides an example of using the
merged-driver structure to cre-
ate an equivalent Rtt termina-
tion value of 40Ω to a midpoint
voltage VDDQ/2. Multiple ter-
mination values are available,
depending on how many of the
pull-up and pull-down legs are
enabled (Table 2).
Figure 2: Merged-driver structure creates an equivalent Rtt termination value of 40Ω to a midpoint voltage VDDQ/2.

tance reduction, dynamic on-die structures enable multiple ter- tance. It reuses portions of the Dynamic ODT
termination (ODT) and a new mination values, using combi- output driver structure for the A new dynamic ODT feature
calibration scheme. To reduce nations of the same pull-up and termination values because gives DDR3 SDRAM systems
the input capacitance of a com- pull-down driver legs. The full- they are a common divider ratio the flexibility to optimize termi-
bination output driver/termi- strength driver has an output of the existing 240Ω legs. This nation values for different load-
nation driver, DDR3 SDRAM impedance of 34Ω, represented is a key distinction from DDR2 ing conditions. It also provides
implements a “merged” driver. by enabling seven 240Ω pull-up SDRAM, which uses separate a way to manage the termina-
This concept uses multiple or pull-down legs (Figure 1). structures for the output driver tion power consumption. For
240Ω structures to enable pull- A merged driver’s advantage and termination driver imped- example, in a typical dual-slot
up and pull-down drivers. These is its ability to reduce capaci- ance. DDR3 SDRAM lacks DDR3 SDRAM desktop system,
the memory module that is not
DDR2 SDRAM 667-800 DDR3 SDRAM 800-1600 accessed during a read or write
Parameter/condition Min. Nom. Max. Min. Nom. Max. Units command wants to terminate
Supply voltage (VDD) 1.7 1.8 1.9 1.425 1.5 1.575 V the data bus with a low-imped-
I/O voltage (VDDQ) 1.7 1.8 1.9 1.425 1.5 1.575 V
ance value, such as 30Ω or 40Ω.
I/O reference voltage 0.49 x 0.5 x 0.51 x 0.49 x 0.5 x 0.51 x V
(VREF) VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ The optimal termination for the
Input AC logic high VREF + Vref + V memory module that is being ac-
level (VIHAC) 0.200 0.175 cessed during a write command
Input AC logic low VREF – VREF – V is a high-impedance value of
level (VILAC) 0.200 0.175
Input DC logic high VREF + VREF + V about 60Ω or 120Ω.
level (VIHDC) 0.125 0.100 Dynamic ODT allows a
Input DC logic low VREF – VREF – V DDR3 SDRAM device to change
level (VILDC) 0.125 0.100 termination values seamlessly
Table 1: DDR2 SDRAM vs. DDR3 SDRAM supply and input voltage levels. between write commands is-

Figure 3: Dynamic ODT decreases jitter considerably at the memory module being accessed.
Figure 4: Pull-down leg uses a large polyresistor with n-channel devices for tuning it to the desired 240Ω value.
Equivalent termination value
RTT (Ω) to VDDQ/2
120
60
40
30
Table 2: DDR3 SDRAM termination driver values (Rtt).
sued to different modules.
This feature is not available in
DDR2 SDRAM systems, which
require a bus idle time when
changing termination values
on the same device. By enabling
dynamic ODT, signal integrity
is improved. Dynamic ODT de-
creases jitter at the memory
module being accessed, and it
reduces the amount of ringback
created by reflections off the
second idle memory module.
Although the open data-
eye voltage margin decreases
slightly with dynamic ODT en-
abled, the increase in aperture
width, improved input receiver
sensitivity and decreased input
voltage levels provide enough
margin to compensate for this
effect. The result is a more pre-
dictable and constant open data
eye with good signal integrity.
Rtt ratio to external RZQ
resistor
RZQ / 2
RZQ / 4
RZQ / 6
RZQ / 8
Driver calibration
DDR3 SDRAM introduces a
calibration scheme that is used
for the output driver and for ter-
mination. The ZQ ball of each
DDR3 SDRAM is connected
to an external 240Ω, 1 percent
precision resistor (RZQ), which
is then connected to ground.
The calibration control block
consists of an ADC, compara-
tors, a majority filter, an inter-
nal reference voltage generator
and an approximation register.
The 240Ω legs in the calibration
block are identical to one of the
several pull-up leg combina-
tions used in the output driver
and termination options.
The pull-up leg uses a large
polyresistor that is slightly
larger than 240Ω. It has several
p-channel devices to reduce
the resistance of the legs that
Number of 240Ω legs
enabled
1 pull-up, 1 pull-down
2 pull-up, 2 pull-down
3 pull-up, 3 pull-down
4 pull-up, 4 pull-down
tune the polyresistor to 240Ω.
This resistor is used to archive
a more linear pull-up and pull-
down curve for improved signal
integrity at the system level.
The pull-down leg is similar
to the pull-up leg. It uses a
large polyresistor with multiple
n-channel devices for tuning
the polyresistor to the desired
240Ω value. A block diagram
of the ZQ calibration circuit is
shown in Figure 4.
Once a calibration command
is given, the pull-up line is driven
low, which in turn pulls the pull-
up leg to VDD Q. The voltage
pull-up (Vpull-up) line is used to
compare the voltage at the Xres
point to an internally generated
reference voltage, VDDQ/2, us-
ing the comparator located in-
side the DQ calibration control
block. The p-channel tuning
devices are individually tuned
using the Vohsignals until the
voltage at Xres equals VDDQ/2.
The Voh codes generated by the
PIC are stored in the internal
approximation register and
sent to each of the pull-up legs
of the output drivers and ter-
minations. Once the pull-up
devices have been calibrated
to the external RZQ resistor,
the comparator is used again
to compare the voltage on the
pull-down line (V pull-down ) to
the reference voltage set at
V DD Q/2. This generates the
Vol codes and updates the pull-
down devices at the appropriate
time, completing the calibra-
tion process.
DDR3 SDRAM introduces
two new command decodes
to generate calibration com-
mands: ZQ calibration long
(ZQCL) and ZQ calibration
short (ZQCS). The ZQCL com-
mand funnels out manufac-
turing process variations and
calibrates the memory device’s
initial temperature and volt-
age setting. This command is
issued during initial system
power-up or when the device is
in the reset condition. Full cali-
bration takes 512 clock cycles
to complete. The memory data
bus must be completely idle and
quiet during this time.
The ZQCS command tracks
continuous changes in voltage
and temperature during normal
operation. This allows DDR3
SDRAM to maintain a linear
output driver and termination
impedance over the full voltage
and temperature range. The
ZQCS command takes either 64
or 256 clocks to complete. The
memory data bus must be idle
and quiet during this time.
The 64-clock ZQCS require-
ment assumes that the supply
voltage and temperature range
are less than or equal to 10mVdc
and 0.25°C, respectively, over
a given 128ms period, starting
from the previous ZQCS com-
mand. If the temperature and
voltage variations are larger
than this, the ZQCS command
must wait a full 256 clock cycles
to reset the calibration circuit
to the new voltage and tempera-
ture setting. At this point, the
system may resume 64-clock
cycle ZQCS commands every
128ms, as long as the voltage
and temperature do not drift
10mVdc and 0.25°C from the
previous ZQCS command.
The ZQ calibration scheme
enables the output driver and
termination impedance to
make linear improvement over
the full range of voltage and
temperature specifications.
Because the memory control-
ler issues the calibration com-
mands ZQCL and ZQCS, more
than one DDR3 SDRAM device
can share a single RZQ resistor.
However, each device’s idle
and quiet time during calibra-
tion cannot overlap or occur at
the same time.
The DDR3 ZQ calibration
scheme offers advantages over
the previous DDR2 scheme.
DDR3 SDRAM has improved
signaling through voltage re-
duction and reduced I/O capac-
itance. DDR3 SDRAM’s memo-
ry bandwidth performance will
double the performance of to-
day’s DDR2 SDRAM products
and will increase total system
memory capacity. With these
innovations, DDR3 SDRAM
systems will achieve data rates
of 1,600Mbps by 2009 and
maintain lower cost and power
consumption. Given this prog-
ress, DDR3 SDRAM will soon
become the PC industry’s stan-
dard memory.