MANIPAL CENTER FOR INFORMATION SCIENCE

( A Constituent College of Manipal Academy of Higher

Education, Manipal )

Mini project
Implementation of BIST Capability using LFSR
Techniques in Synchronous RAM

Wilson k (101002036)

Ramesh K S (101002042)

Muddurangan L (101002049)

Group ID- IVC13

Course: MS VLSI - CAD

Guided by: - Mr. Sunderasan.C

 CONTENTS
Abstract .................................................................................................................................................. 3

1. INTRODUCTION .................................................................................................................................. 4

2. General Description ........................................................................................................................... 4

2.1 BIST................................................................................................................................................... 4

2.2 LFSR DESIGN ..................................................................................................................................... 7

2.3 Some polynomials for maximal LFSRs .............................................................................................. 9

2.4 BIST IMPLEMENTATION ON Synchronous RAM ............................................................................. 10

2.5 Synchronous RAM .......................................................................................................................... 10

2.6 Multiplexer ..................................................................................................................................... 11

3. Specific Requirements...................................................................................................................... 13

4. Project Code ..................................................................................................................................... 14

4. References........................................................................................................................................ 20

4.1 Webliography ................................................................................................................................. 20

Abstract
The increasing growth of sub-micron technology has resulted in the difficulty of VLSI
testing. Test and design for testability are recognized today as critical to a successful design.
Built-in-Self-Test (BIST) is becoming an alternative solution to the rising costs of external
electrical testing and increasing complexity of devices Small increase in the cost of system
reduces large testing cost. BIST is a design technique that allows a circuit to test itself Test
pattern generator (TPG) using Linear Feedback Shift Resister (LFSR) is proposed which is
more suitable for BIST architecture. We are implementing Synchronous Random Access
Memory (SRAM) with BIST capability using LFSR techniques.
1. INTRODUCTION
Testing of integrated circuits (ICs) is important to ensure a high level of quality in product
functionality in both commercially and privately produced products. In the modern System-
on-a-Chip (SoC) design, many cores are integrated into a single chip. Some of them are
embedded, and cannot be accessed directly from the outside of the chip. Such SoC designs
make the test of these embedded cores become a great challenge. The Built-In-Self-Test
(BIST) is one of most popular test solutions to test the embedded cores. Built-in self-test
refers to techniques and circuit configurations that enable a chip to test itself. In this
methodology, test patterns are generated and test responses are analyzed on-chip.

INPUT Primary IP
TPG MUX (Test)

BIST
Synchronous
Output
RAM

BIST
COMPARATOR
PASS / FAIL

Figure 1: Basic Block Diagram

Abbreviation:
TPG: Test Pattern Generator
BIST: Built In Self Test
RAM: Random Access Memory

2. General Description
2.1 BIST
Built-in Self Test or BIST, is the technique of designing additional hardware and software
features into integrated circuits to allow them to perform self-testing, i.e., testing of their own
operation (functionally, parametrically, or both) using their own circuits, thereby reducing
dependence on an external automated test equipment (ATE).
BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a
chip easier, faster, more efficient, and less costly. The concept of BIST is applicable to just
about any kind of circuit, so its implementation can vary as widely as the product diversity
that it caters to. As an example, a common BIST approach for DRAM's includes the
incorporation onto the chip of additional circuits for pattern generation, timing, mode
selection, and go-/ no-go diagnostic tests.

The main drivers for the widespread development of BIST techniques are the fast-rising costs
of ATE testing and the growing complexity of integrated circuits. It is now common to see
complex devices that have functionally diverse blocks built on different technologies inside
them. Such complex devices require high-end mixed-signal testers that possess special digital
and analog testing capabilities. BIST can be used to perform these special tests with
additional on-chip test circuits, eliminating the need to acquire such high-end testers.

BIST is also the solution to the testing of critical circuits that have no direct connections to
external pins, such as embedded memories used internally by the devices. In the near future,
even the most advanced tester may no longer be adequate for the fastest chip, a situation
wherein self-testing may be the best solution for.

Advantages of implementing BIST include: 1) lower cost of test, since the need for external
electrical testing using an ATE will be reduced, if not eliminated; 2) better fault coverage,
since special test structures can be incorporated onto the chips; 3) shorter test times if the
BIST can be designed to test more structures in parallel; 4) easier customer support; and 5)
capability to perform tests outside the production electrical testing environment. The last
advantage mentioned can actually allow the consumers themselves to test the chips prior to
mounting or even after these are in the application boards.

Disadvantages of implementing BIST include:

1) Additional silicon area and fab processing requirements for the BIST circuits
2) Reduced access times
3) Additional pin (and possibly bigger package size) requirements, since the BIST circuitry
need a way to interface with the outside world to be effective
4) Possible issues with the correctness of BIST results, since the on-chip testing hardware
itself can fail.
Issues that need to be considered when implementing BIST are: 1) faults to be covered by the
BIST and how these will be tested for; 2) how much chip area will be occupied by the BIST
circuits; 3) external supply and excitation requirements of the BIST; 4) test time and
effectiveness of the BIST; 5) flexibility and changeability of the BIST (i.e., can the BIST be
reprogrammed through an on-chip ROM?); 6) how the BIST will impact the production
electrical test processes that are already in place.

BIST techniques are classified in a number of ways, but two common classification of BIST
are the Logic BIST (LBIST) and the Memory BIST (MBIST). LBIST, which is designed for
testing random logic, typically employs a pseudo-random pattern generator (PRPG) to
generate input patterns that are applied to the device's internal scan chain, and a multiple
input signature register (MISR) for obtaining the response of the device to these test input
patterns. An incorrect MISR output indicates a defect in the device.

MBIST, as its name implies, is used specifically for testing memories. It typically consists of
test circuits that apply, read, and compare test patterns designed to expose defects in the
memory device. There now exists a variety of industry-standard MBIST algorithms, such as
the "March" algorithm, the checkerboard algorithm, and the varied pattern background
algorithm.

One may also encounter the acronym "ABIST", which stands for two totally different BIST
techniques: the Array BIST, which is a form of MBIST used for embedded memories, and
the Analog BIST, which is a BIST approach for analog circuits. BIST is fast becoming an
alternative solution to the rising costs of external electrical testing and increasing complexity
of devices. This approach will find greater deployment in a wider variety of circumstances
as more and better BIST techniques are developed. This does not mean, however, that BIST
will eventually replace external electrical testing altogether. Still, BIST proponents are
optimistic that BIST will someday be the preferred mode of testing, instead of being merely
an alternative to external ATE testing as it is today.

Circuit Under Test (CUT): It is the portion of the circuit tested in BIST mode. It can be
sequential, combinational or a memory. It is delimited by their Primary Input (PI) and
Primary Output (PO).
Test Pattern Generator (TPG): It generates the test patterns for the CUT. It is a dedicated
circuit or a microprocessor. The patterns may be generated in pseudorandom or
deterministically.
Test Response Analysis (TRA): It analyses the value sequence on PO and compares it with
the expected output
BIST Controller Unit (BCU): It controls the test execution; it manages the TPG, TRA and
reconfigures the CUT and the multiplexer. It is activated by the Normal/Test signal and
generates a Go / No go.
2.2 LFSR DESIGN
A linear feedback shift register (LFSR) is a shift register whose input bit is a linear
function of its previous state. The only linear function of single bits is xor, thus it is a shift
register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift
register value.

The initial value of the LFSR is called the seed, and because the operation of the register is
deterministic, the stream of values produced by the register is completely determined by its
current (or previous) state. Likewise, because the register has a finite number of possible
states, it must eventually enter a repeating cycle. However, an LFSR with a well-chosen
feedback function can produce a sequence of bits which appears random and which has a
very long cycle.

Applications of LFSRs include generating pseudo-random numbers, pseudo-noise sequences,

fast digital counters, and whitening sequences. Both hardware and software implementations
of LFSRs are common.

Linear feedback shift registers (LFSRs) are often used to generate test patterns. The outputs
from the first and fourth flip-flops are XORed together and fed back into the D input of the
first flip-flop. The general form of a LFSR is a shift register with two or more flip-flop
outputs XORed together and fed back into the first flip-flop. The name linear comes from the
fact that exclusive OR is equivalent to modulo-2 addition, and addition is a linear operation.
By proper choice of the outputs that are fed back through the exclusive OR gate, it is possible
to generate 2"- 1 different bit patterns using an n-bit shift register. All possible patterns can
be generated except for a11 0s. The patterns generated by the LFSR of Figure are:

1000, 1100, 1110, 1111, 0111, 1011, 0101, 1010, 1101, 0110, 0011, 1001, 0100, 0010,
0001, 1000.

These patterns have no obvious order, and they have certain randomness properties. Such a
LFSR is often referred to as a pseudo-random pattern generator, or PRPG. PRPGs are
obviously very useful for BIST, since they can generate a large number of test patterns with a
small amount of logic circuitry. Table 10-4 gives one feedback combination that will generate
all 2n - 1 bit patterns for some LFSRs with lengths in the range n = 4 to 32.

If the all-Os test pattern is required, an n-bit LFSR can be modified by adding an AND gate
with n - 1 inputs, as shown in Figure 10-24 for n = 4. When in state 0001, the next state is
0000; when in state 0000, the next state is 1000; otherwise, the sequence is the same.
2.3 Some polynomials for maximal LFSRs
The following table lists maximal-length polynomials for shift-register lengths up to 19. Note
that more than one maximal-length polynomial may exist for any given shift-register length.

Bits Feedback polynomial Period

n 2n − 1
2 x2 + x + 1 3
3 x3 + x2 + 1 7
4 x4 + x3 + 1 15
5 x5 + x3 + 1 31
6 x6 + x5 + 1 63
7 x7 + x6 + 1 127
8 x8 + x6 + x5 + x4 + 1 255
9 x9 + x5 + 1 511
10 x10 + x7 + 1 1023
11 x11 + x9 + 1 2047
12 x12 + x11 + x10 + x4 + 1 4095
13 x13 + x12 + x11 + x8 + 1 8191
14 x14 + x13 + x12 + x2 + 1 16383
15 x15 + x14 + 1 32767
16 x16 + x14 + x13 + x11 + 1 65535
17 x17 + x14 + 1 131071
18 x18 + x11 + 1 262143
19 x19 + x18 + x17 + x14 + 1 524287
Output-stream properties

• Ones and zeroes occur in 'runs'. The output stream 0110100, for example consists of
five runs of lengths 1,2,1,1,2, in order. In one period of a maximal LFSR, 2n − 1 runs
occur (for example, a six bit LFSR will have 32 runs). Exactly 1/2 of these runs will
be one bit long, 1/4 will be two bits long, up to a single run of zeroes n − 1 bits long,
and a single run of ones n bits long. This distribution almost equals the statistical
expectation value for a truly random sequence. However, the probability of finding
exactly this distribution in a sample of a truly random sequence is rather low.
• LFSR output streams are deterministic. If you know the present state, you can predict
the next state. This is not possible with truly random events.
• The output stream is reversible; an LFSR with mirrored taps will cycle through the
output sequence in reverse order.
2.4 BIST IMPLEMENTATION ON Synchronous RAM
In implementation part, the BIST techniques with 8-bit LFSR based test pattern generation is
incorporated into the Synchronous RAM design before the overall design is synthesized by
means of recognizing the exiting design to match built in test requirements as we discussed
Test pattern generator is the very important part, which have different possible circuits.

2.5 Synchronous RAM

Single Clock Synchronous RAM Port Listing

Port Name Type Description
data[7:0] Input 8-bit data input
read_addr[5:0] Input 6-bit read address input
write_addr[5:0] Input 6-bit write address input
we Input Write enable input
clk Input Clock input
q[7:0] Output 8-bit data output
2.6 Multiplexer

A multiplexer or mux is a device that performs multiplexing; it selects one of many analog
or digital input signals and forwards the selected input into a single line. A multiplexer of 2n
inputs has n select lines, which are used to select which input line to send to the output.

An electronic multiplexer makes it possible for several signals to share one device or
resource, for example one A/D converter or one communication line, instead of having one
device per input signal.
An electronic multiplexer can be considered as a multiple-input, single-output switch, and a
demultiplexer as a single-input, multiple-output switch. The schematic symbol for a
multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins
and the short parallel side containing the output pin. The schematic on the right shows a 2-to-
1 multiplexer on the left and an equivalent switch on the right. The sel wire connects the
desired input to the output.

In telecommunications, a multiplexer is a device that combines several input information

signals into one output signal, which carries several communication channels, by means of
some multiplex technique. A demultiplexer is in this context a device taking a single input
signal that carries many channels and separates those over multiple output signals

In telecommunications and signal processing, an analog time division multiplexer (TDM)

may take several samples of separate analogue signals and combine them into one pulse
amplitude modulated (PAM) wide-band analogue signal. Alternatively, a digital TDM
multiplexer may combine a limited number of constant bit rate digital data streams into one
data stream of a higher data rate, by forming data frames consisting of one timeslot per
channel.

In telecommunications, computer networks and digital video, a statistical multiplexer may

combine several variable bit rate data streams into one constant bandwidth signal, for
example by means of packet mode communication. An inverse multiplexer may utilize
several communication channels for transferring one signal.
3. Specific Requirements

Software

• Linux (Operating System)

• VCS simulation
• Model Sim
4. Project Code
//BIST Test Bench
module bist_tb;
//parameter datain=8'b10101110;

reg sel,clk,rst,we,cs,oe;
reg [7:0] datain;
reg [5:0] read_addr,write_addr;
//reg [7:0] data;
wire [7:0] dataout;
wire bst;
integer i;

bist
b1(.sel(sel),.datain(datain),.clk(clk),.rst(rst),.dataout(dataout),.read_addr(read_addr),.write_ad
dr(write_addr),.we(we),.cs(cs),.oe(oe),.bst(bst));

initial
begin
clk<=1'b0;
rst<=1'b1;
we<=1'b1;
cs<=1'b1;
oe<=1'b1;
#55 rst<=1'b0;
end
always
#5 clk=~clk;
always
#400 rst=~rst;

initial
begin

#5 sel=1'b0;
#5 we=1'b0;cs=1'b0;
#5 datain=8'b10101010;
#5 write_addr=6'b010101;
//#10 cs=1'b1; we=1'b1;
#5 cs=1'b0; oe=1'b0; we=1'b0;
#5 read_addr=6'b010101;

#5 we=1'b1;cs=1'b1; oe=1'b1;
 #20 sel=1'b1;
#5 we=1'b0;cs=1'b0;
#5 write_addr<=6'b0;read_addr<=6'b0;
for(i=0;i<=63;i=i+1)
begin
#1 write_addr<=write_addr+i;
#1 read_addr<=read_addr+i;
end
//#200 cs=1'b1; we=1'b1;
#5 cs=1'b0; oe=1'b0;
//#5 read_addr<=6'b0;
/*for(i=0;i<=63;i=i+1)
begin
#1 read_addr<=read_addr+i;
end*/
/*#5 read_addr=6'b000000;
#5 read_addr=6'b000001;
#5 read_addr=6'b000010;
#5 read_addr=6'b000011;
#5 read_addr=6'b000100;*/
//#300 $finish;
end
initial
$monitor($time,"clk=%b,rst=%b,sel=%b,we=%b,cs=%b,oe=%b,datain=%b,write_addr=%b,r
ead_addr=%b,dataout=%b,bst=%b",clk,rst,sel,we,cs,oe,datain,write_addr,read_addr,dataout,
bst);
endmodule

//Bist Code

module bist(sel,datain,clk,rst,dataout,read_addr,write_addr,we,cs,oe,bst);

input sel,clk,rst,we,cs,oe;
input [7:0] datain;
input [5:0] read_addr,write_addr;
output [7:0] dataout;
output bst;
wire [7:0] dataout;
wire [7:0] qout,q;
wire [5:0] read_addr,write_addr;
wire we;
wire[7:0] data;
wire bst;

lfsr l1(.qout(qout),.clk(clk),.rst(rst),.qbarout());
mux2x1 m1(.datain(datain),.qout(qout),.sel(sel),.data(data));
ram_infer
r1(.data(data),.read_addr(read_addr),.write_addr(write_addr),.we(we),.clk(clk),.q(q),.cs(cs),.o
e(oe));
outreg o1(.q(q),.qout(qout),.dataout(dataout),.bst(bst));

endmodule

//LFSR Code
module lfsr(qout,qbarout,clk,rst);
parameter n=8;
output [n-1:0] qout,qbarout;
input clk,rst;
wire [n-1:0] q,qbar;
wire a,g;
reg [n-1:0]qout,qbarout;

dff d1(q[0],qbar[0],g,clk,rst);
dff d2(q[1],qbar[1],q[0],clk,rst);
dff d3(q[2],qbar[2],q[1],clk,rst);
dff d4(q[3],qbar[3],q[2],clk,rst);
dff d5(q[4],qbar[4],q[3],clk,rst);
dff d6(q[5],qbar[5],q[4],clk,rst);
dff d7(q[6],qbar[6],q[5],clk,rst);
dff d8(q[7],qbar[7],q[6],clk,rst);

assign a=qbar[0]&qbar[1]&qbar[2]&qbar[3]&qbar[4]&qbar[5]&qbar[6]&qbar[7];
assign g=(a^q[1]^q[2]^q[3]^q[7]);

always @(posedge clk)

begin
qout<=q;
end
endmodule

//D-Flip Flop Code

module dff(q,qbar,d,clk,rst);
input d, clk,rst;
output q,qbar;
reg q,qbar;
always @(posedge clk)
begin
if(rst)
begin
q<=1'b0;
qbar<=~q;
end
else
begin
q<=d;
qbar<=~q;
end
end
endmodule

//MUX Code
module mux2x1(datain,qout,sel,data);
input [7:0]datain,qout;
input sel;
output [7:0]data;
reg [7:0]data;

always @(sel or datain or qout)

begin
case (sel)
1'b0 : data= datain;
1'b1 : data= qout;
default : data =8'bxxxxxxxx;
endcase
end
endmodule

//RAM Interface
module ram_infer(data,read_addr,write_addr,we,clk,q,cs,oe);
input [7:0] data;
input [5:0] read_addr, write_addr;
input we, clk,cs,oe;
output [7:0] q;
reg [7:0] q;
reg [7:0] ram[63:0];
integer i;

always @ (posedge clk)

 begin
if (!we && !cs)
begin
ram[write_addr]<=data;
end
else
begin
q<=8'b00000000;
end
end
always @(posedge clk)
begin
if(!cs && !we && !oe)
begin
q<=ram[read_addr];
end
else
begin
q<=8'b00000000;
end
end

endmodule

//Output Register
module outreg(q,qout,dataout,bst);
input [7:0]q,qout;
output [7:0]dataout;
reg [7:0]dataout;
output bst;
reg bst_i;

assign bst=bst_i;
always @ (q or qout)
begin
if(q==qout)
begin
dataout<=q;
bst_i<=1'b1;
end
else
begin
dataout<=q;
bst_i<=1'b0;
 end
end
endmodule
4. References
4.1 Webliography
http://www.ui.savba.sk/diag/tools/testability.html