PAPER PRESENTATION

ON
VLSI DESIGN
[ DESIGN OF ALL DIGITAL PHASE LOCKED LOOP (ADPLL)
FOR RF TRANSMITTER]

at
SRI VENKATESWARA UNIVERSITY

by

UMA MAHESWARA RAO D., SUDARSAN K.R.,

II B.E. ECE, II B.E. ECE,
Email:sreeganesh52@yahoo.com , Email:matrixneo9@gmail.com ,
Contact no : 0877-2261032
Mobile : 9440419783 Mobile : 9885936124

SIDDHARTH INSTITUTE OF ENGINEERING AND TECHNOLOGY

PUTTUR
 DESIGN OF ADPLL FOR RF TRANSMITTER AT 2.4 GHz FREQUENCY

Abstract:-

We present the RF transmitter architecture based on All Dig ital Phase Locked

Loop (ADPLL) which is built from the ground up using digital techniques and digital

creation flow. In this paper, we described a system on chip that integrates ADSP with a

multi Gega-Hertz digital RF transmitter that meets the blue tooth specifications. A need

has arisen to find digital architectural solutions to the RF functions. The frequency

synthesizer is a key block used for frequency translation of radio signals and has been

traditionally based on a charge -pump phase-locked loop (PLL), which is not easily

amenable to integration. Recently, a digitally -controlled oscillator (DCO), which

deliberately avoids any analog tuning controls, was first presented for RF wireless

applications. This allows for its loop control circuitry to be impl emented in a fully digital

manner as first proposed. Normally VCO forms a major part in conventional analog

PLLs. Due to its entire digital architecture ADPLL consists of a DCO. Here the DCO

functions on the basis of Shifting. This DCO shifting along with FCW comprises the

basic operation of ADPLL. The challenge of the above ADPLL -based transmitter is to

find an architecture that is amenable to low current consumption such that it is

competitive to similar products using the conventional RF techniques.

Index terms:-

Transmitter, system-on-chip, blue tooth, DSP, frequency synthesizer, digital controlled

oscillator.

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HARDWARE IMPLEMENTATION :-

ARCHITECTURE :-

The transmitter is based on an ADPLL with a wideband frequency modulation

capability. The output variable frequency (Fv) is related to the reference frequency(Fr)

by the frequency command word (FCW).

The FCW is time-variant and is allowed to change with every cycle of the frequency

reference (FREF) clock. The variable phase (RVi) is determined by count ing the number

of rising clock transitions of the DCO oscillator clock CKV.

The index i indicates the DCO edge activity. The reference phase RR[k] is

obtained by accumulating FCW with every cycle of the retimed frequency reference

(FREF) clock input operating at fR.

BLOCK DIAGRAM OF ADPLL

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The FREF-sampled variable phase is subtracted from the reference phase in a

synchronous arithmetic phase detector producing phase error samples.

The FREF retiming quantization error is determined by the TDC.

PHASE OPERATION :-

The phase operation of RR [K] and RV [I] could be visualized as two rotating vectors and

the smaller angle between them constituting the phase error. Both RR[K] and RV[I] are

positive numbers .

ROTATING VECTOR INTERPRETITION OF REF. & VAR. PHASES:-

The digital phase error is attenuated by the loop gain factor and then normalized by the

DCO gain [K DCO] in order to correct the DCO phase/frequenc y in a negative feedback

manner.The phase error attenuator factor establishes the PLL loop first -order filtering

characteristic.

Where fbw is a 3-dB cut-off frequency of the closed PLL loop. With Fw=15,the ADPLL

provides fine frequency control with 400 -Hz accuracy, according to

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 ADPLL PHASE DOMAIN SIGNALS

The number of integer bits Wi=8 was chosen to fully cover the Bluetooth frequency

range of Fv= 2400–2480 MHz with the Fr=13 MHz reference frequency. For the

implemented architecture Wi=8 and Wf=15.

VARIABLE PHASE ACCUMULATOR : -

The variable phase accumulator is implemented as an incrementer of RV[i]

followed by a sampler of RV[k] . The 8 -b accumulator implements the DCO clock count

incrementing with a rollover effect, which is naturally handled with the modulo

arithmetic. The CMOS proce ss is fast enough to perform the 8 -b binary incrementer at

2.4-GHz clock in one cycle using a simple carry -ripple structure The carry-ripple binary

incrementer was transformed into two separate smaller incrementers. The first

incrementer operates on the tw o lower order bits and triggers the higher order increment

whenever its count reaches “11.” The second incrementer operates on the same CKV

clock, but the 6-b increment operation is allowed now to take four clock cycles

VARIABLE PHASE INCREMENTER WITH SEPARATE CALCULATION

BETWEEN LOWER AND HIGHER ORDER BITS

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 The fan out of six was taking a disproportional toll on the delay, so a slight

modification was done by retiming that control path. Final implementation version of th e

PV block is shown below. The triggering state is now one count earlier at “10.” The chief

improvement of this solution is that the register output Q INC is now capable of driving

six multiplex select lines.

IMPLEMENTATION OF VARIABLE PHASE INCREMENTER WITH

HIGHER ORDER INCREMENT TIMING

TIME TO DIGITAL CONVERTER:

It measures the fractional delay difference between the FREF clock and the next

rising edge of the DCO clock, CKV. The TDC operates by passing the complementar y

DCO clock through the string of inverters. On each rising edge of FREF, the delayed

clock vector is sampled using an array of registers whose outputs form a pseudo -

thermometer code. The outputs are then converted to binary code and normalized by the

DCO clock period to be used as a fractional error correction. The finite TDC resolution

results in a frequency estimation quantization of

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 STRUCTURE OF TDC

DIGITALLY CONTROLLED OSCILLATORS (DCO): -

ARCHITECTURE OVERVIEW OF DCO :-

Fractional-N frequency synthesizer architecture avoids both of the above

problems and lends itself well to an indirect narrowband frequency modulation which

could be implemented in a more digital manner.

NORMALIZED DCO HARDWARE

ABSTRACTION LAYER

This architecture, however, requir es precise matching between the digital pre -

compensation filter and the analog PLL transfer function . A two-point direct modulation

scheme performs phase compensation of the PLL by digitally integrating the transmit

modulating data bits and using the integ rator output to shift the phase of the reference

clock signal, while the Gaussian filtered data directly modulates the VCO frequency. In

contrast, this paper proposes a DCO gain calibration solution that is digital in nature,

consumes little hardware overh ead, and requires only one component matching, i.e.

DCO, which is done just-in-time in a digital manner with a very fine resolution.

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DCO GAIN NORMALIZATION : -

At a higher level of abstraction, the DCO oscillator, together with the DCO gain

normalization fR=KDCO multiplier, logically comprise the normalized DCO (nDCO), as

illustrated .The DCO gain normalization conveniently decouples the phase and frequency

information throughout the system from the process, voltage and temperature variations

that normally affect the KDCO. The frequency information is normalized to the value of

the external reference frequency fR. The digital input to the nDCO is a fixed -point

normalized tuning word (NTW).The reference frequency is chosen as the normalization

factor because it is the master basis for the frequency synthesis. In addition, the clock rate

and update operation of this discrete -time system are established by the reference

frequency.

CONCLUSION AND FUTURE SCOPE: -

ADPLL systems have many ad vantages over the traditional charge -pump PLLs.

The ability to use DSP to improve the system’s performance is significant and can make

the system much more adaptive.ADPLL has a improved speed, performance, reliability

and programmability when compared to a nalog PLLs. Moreover the testability is easier

when compared to analog PLLs. Also the cost and size are reduced when compared to

analog PLLs. Hence ADPLLs are far more superior when compared to PLLs.

References :-

1.portal.acm.org/citation.cfm

2.www.itcprogramdev.org

3.ieeexplore.ieee.org

4.en.wikipedia.org/wiki/