CMOS Gates and Circuits

Ali El Kateeb
U of M- Dearborn

ECE 514
Overview
„ Static logic gates
„ The Inverter: design and layout
„ NOR and NAND gates
„ Logic Formation
„ Layout of complex logic gates
„ CMOS transmission gates
Static Logic Gates
„ Characateristics
„ When inputs are stable, the output are
well-defined
„ DC power dissipation is very small
„ Series and parallel MOSFET arrays can be
used to construct arbitrary logic functions
Static Logic Gates - Inverter
„ Inverter

„ Inverter operation
Static Logic Gates - Inverter
Voltage Transfer Curve (VTC)
„ The voltage transfer curve (VTC) of the inverter is a
plot of Vout as a function Vin
„ The VTC defines the DC behavior of the circuit, and
neglect all transient switching effects
Static Logic Gates - Inverter
„ To measure VTC, apply a sequence of voltages to the input and
measure the voltage at the output
„ Unity-gain line defined by Vout = Vin
„ The intersection of the transfer curve with the unity gain line is
denoted by VI, which denote the inverter switching voltage
„ Interpretation of VI: it represents the boarder between logic 0
and logic 1 input voltage range (VI called the inverter threshold
voltage)
Static Logic Gates - Inverter
Transient Properties
„ Logic delays originate from the finite

time required to charge and discharge

the output capacitance Cout
Static Logic Gates - Inverter
Transient Properties

„ The switching time intervals are computed by

analyzing the output circuit for high-to-low and low-
to-high transitions
„ High-to-low time: the time required for the output
voltage to change from 0.9 VDD to 0.1 VDD
„ Low-to-high time: the time required for the output
voltage to change from 0.1 VDD to 0.9 VDD
Static Logic Gates - Inverter
Transient Properties
„ The switching time can be used to measure
the speed of the inverter
f max = 1 / (tHL + tLH)
Where tHL + tLH is the minimum time interval
needed for the inverter to make a full
transition from logic 1 to logic 0, and back to
logic 1
Static Logic Gates - Inverter
Transient Properties
„ Propagation delay time tp: average delay through the inverter
gate
tP = (1/2) (tPLH + tPHL)
„ tPLH is the propagation delay for a low-to-high, and tPHL is for

high-to-low
„ These times are defined between 50% points
Static Logic Gates - Inverter
Inverter Design
„ Process transconductance is
k’p = µp C ox
Where µp is the surface hole mobility
C ox is the oxide capacitance per unit area
„ Hole mobility is less than the electron mobility
k’p < k’n
where k’n ≈ 2 k’p
„ Device transconductance
ßp = k’p (W/L)p for p-device
ßn = k’n (W/L)n for n-device
Therefore, ßp < ßn (for equal size pFET and nFET)
Static Logic Gates - Inverter
Inverter Design
„ Inverter design is based on:
„ DC Characteristics
„ Transient characteristics
„ The gate-threshold voltage, Vinv (or VI), is dependent on ßn /
ßp
„ Gate-throshold voltage where Vin = Vout
„ To change ßn / ßp, the channel dimensions must be changed,
i.e., channel length L and channel width W

„ ßn / ßp = 1 is desirable since it allows a capacitive load to

charge and discharge in equal times by providing equal
current-source and –sink capabilities
Static Logic Gates - Inverter
Inverter Design
50/1

5/1

5/1

20/1
Static Logic Gates - Inverter
Inverter Design
ßn = k’n (Wn/Ln)
ßp = k’p (Wp/Lp)

• For equally sized n- and p- transistors, Where

ßn = 2 ßn
• tf = tr/2, i.e., fall time is faster than rise
time due to different carrier mobilities
• To have approximately the same rise and
fall time for an inverter
ßn / ßp = 1 (Implies that the channel width
for the p-device must be increased to
approximately two to three times that of
the n-device)
Layout - Inverter
„ Circuit layout and physical design
revolve around two basic ideas
„ Design the circuit so that it has the proper
electrical characteristics
„ Place the transistors and the interconnect
lines in a manner that results:
„ In a reasonable compact structure
„ Route other interconnections as needed
Layout - Inverter

„ Note: the transistor dimensions W’ and L’ are the drawn values.

„ pFET has been made larger than nFET (W/L)p > (W/L)n
„ The size ratio is less than 2, so ßn > ßp
Layout - Inverter
Different approach
„ MOSFETs are constructed using horizontal ACTIVE regions
„ POLY input and all METAL connections are vertical
„ pFET and nFET transistors are equal in size
NAND2

„ The nFETs provide a path from the output to ground if and only if
both A=1 AND B=1
„ If any one of nFET is OFF, the output has a strong connection path
to the power supply Vdd through one of the pFETs
NOR2

„ When either A=1 OR B=1 (or both), then at least one of the
nFET is conducting and the output voltage is 0v
„ The only time the output is high when both A=0 AND B=0
General CMOS Static Logic Gates
Features of the topology are:
„ Every input variable is connected to both
nFET and pFET

β pMOS only

B
A
α
C nMOS only
General CMOS Static Logic Gates
Features of the topology are:
„ Two logic arrays are used to implement the logic
function
„ One array consists of nFETs with the logic block
connecting the output to ground
„ The other, pFET, build a logic block connected from the
output to VDD
„ When the inputs are stable, only one logic block is
closed, i.e., either pFET or nFET
„ Low DC power dissipation
„ N-input gate requires 2N transistors (one for nFET
and one for pFET)
CMOS Static Logic Gates
„ Static logic gate can implement And-Or-Invert (AOI)
and OAI logic functions easily
„ Correspond to Sum of Products (SOP) and Product
of Sum (POS)
„ The basic rules of logic formation can be summarized
as following:
„ Rules apply to group of nFETs that implement
individual functions:
„ Series-connected nMOSFETs give the NAND operation
„ Parallel-connected nMOSFETs give the NOR operation
„ Rules apply to group of pFETs
„ Series-connected pMOSFETs to implement the NOR
operations
„ Parallel-connected pMOSFETs to implement the NAND
operation
CMOS Static Logic Gates:AOI example
„ The structure of the pFET logic array is the dual of
the nFET connections
„ nFETs is series require that the corresponding

pFETs be in parallel
Example: F = (AB + C)’
CMOS Static Logic Gates:XOR Example
Example: F = A XOR B (i.e., F= A’B + AB’)
Create the AOI form, which leads directly to the gate logic, i.e.,
F = (AB +A’B’)’

-
CMOS Static Logic Gates:XNOR Example
Example: F = AB + A’B’
Layout of complex logic gates
„ Logic formation rules are based on series and parallel
combinations of MOSFETs
„ Layout techniques can be divided into these groups
„ Series-connected MOSFETs
„ Parallel-connected MOSFETs
„ Input and output wiring
„ Wiring to ground and VDD
Layout of complex logic gates
„ Series-connected MOSFETs
„ n+ and p+ regions can be shared between two transistors
„ Since drain and source electrodes are not defined until the
voltage are applied, a common n+ region serves as either a
drain or source as required
„ As the transistor resistance are in series, the RC time
constant of the group can be a limiting factor in the
switching time
Layout of complex logic gates
„ Parallel-connected MOSFETs
„ Parallel connections can be achieved by using n+
and p+ regions in connections with metal
interconnect routing
Layout of NAND2 and NOR2 gates
„ Series-parallel logic is required for
NAND2 and NOR2 layout
„ NAND2: Two nFETs in series and two pFETs in
parallel
„ NOR2: Two nFETS in parallel and two pFETs in
series
Basic Layout Guidelines
„ Do wire planning before cell layout
„ Assign preferred direction to each layer
„ Group p’s and n’s
„ Determine input/output port locations
„ Power, ground must be wide
„ Determine cell pitch
„ Height of tallest cell
„ Number of over-the-cell tracks and wire lengths
„ Use metal for wiring
„ Use poly for intra-cell wiring only
„ Use diffusion for connection to transistors only
„ Do stick diagram first!
Basic Cell Layout Guidelines
„ P-N spacing is large, so keep pMOS
together and nMOS together
„ Vdd and ground distribution must be in
wide metal
„ Vdd runs near pMOS groups
„ Ground runs near nMOS groups
„ Layers in alternate directions
„ M1 and M2 should run in orthogonal
directions.
Transistor Layout

Good bad bad bad

„ Transistors should be at least as wide

as contacts
„ Use as many contacts as possible for
wider transistors
Layout Issues
„ Two types of diffusion
„ ndiff
„ poly crossing ndiff makes nMOS transistor
„ pdiff
„ poly crossing pdiff makes pMOS transistor
„ Cannot directly connect ndiff and pdiff
„ must connect ndiff to metal and metal to pdiff
„ Cannot get ndiff too close to pdiff because of wells
„ large spacing rule between ndiff and pdiff
„ need to group nMOS transistors together and pMOS
transistors together
Stick Diagrams
„ Use stick diagram to reduce the work that
needed to create the layout
„ Alternate representation of the circuit, somewhere
in between a layout drawing and the electronic
schematic
„ Like a layout
„ Basic topology of the circuit
„ Relative positions of objects roughly correct
„ But
„ Wires have no width
„ Size of objects not to scale
Stick Diagram
„ Simplified version of layout
„ Abstract the layout so that wires are just
lines
„ No need to worry about width or spacing
„ Good starting point before the layout
Wiring Layers
„ Wiring layers represented by different colors
„ diff: green/yellow
„ poly: red
„ metal1: blue
„ metal2: orange
„ metal3: purple
„ Wires on the same layer always connect, if
they touch. No way to jump wires without
changing layers
„ Need contacts to connect wires on different
layers
Transistor
„ Formed when poly (red) crosses
diffusion (green or yellow)

No connection

Connection

connected transistor
Basic Layout Planning
„ Need to route power and ground (in metal)
„ Keep nMOS devices near nMOS devices and
pMOS devices near pMOS devices
„ nMOS near ground and pMOS near Vdd
„ Run poly vertically and diffusion horizontally
with m1 horizontally
„ Keep diffusion wires as short as possible
„ just enough to make transistors
„ All long wires in m1 and m2
Typical Cell Layout Plan

„ Inverter
„ pMOSFETs: near VDD
„ nMOSFETs: near GND

Vdd

Gnd

„ Translate a stick diagram to a physical layout

„ Replace each line with a polygon of appropriate size and
shape
CMOS Gates
Example: Draw the circuit and stick diagram
that represent the AOI circuit ( A + B )C

B A B C
Vdd

out out

C
Gnd
A
Switch logic
„Can implement Boolean formulas as
networks of switches.
„Can build switches from MOS transistors—
transmission gates.
„Transmission gates have smaller layouts.
Types of switches
 Behavior of n-type switch
n-type switch has source-drain voltage
drop when conducting:
„ conducts logic 0 perfectly;
„ introduces threshold drop into logic 1.
VDD VDD - Vt

VDD
 n-type switch driving static logic

Switch underdrives static gate, but gate

restores logic levels.

VDD VDD - Vt

VDD
n-type switch driving switch logic

Voltage drop causes next stage to be

turned on weakly.

VDD VDD - Vt

VDD
 Behavior of complementary
switch
„ Complementary switch products full-
supply voltages for both logic 0 and
logic 1:
„ n-type transistor conducts logic 0;
„ p-type transistor conducts logic 1.
Switches
„ How to built switches from MOS transistors?
„ N-type switch
„ Require one transistor and one gate signal
„ Transmit 0 well, but when Vdd is applied to the drain, the
voltage at the source is Vdd-Vtn
„ As Vgs is always equal to Vds, the NMOS transistor is either in
0 saturation or off
„ When switch logic drives gate logic, n-type switches can cause
electrical problems
„ When n-type switch driving a complementary gate cause the gate
to run slower when the switch input = 1
„ Since pulldown current is weaker when a lower gate voltage
is applied
Vdd−Vth „ The complementary gate’s pulldown will not suck current off
the output capacitance as fast as it should be
Switches
„ How to built switches from MOS transistors?
„ P-type switch
„ When Vin = 0 and Vout = Vdd
„ Cload will be discharged through P transistor until Vout = Vtp
„ P-device will stop conducting

„ Logic 0 is somewhat degraded through p-device

Vin Vout

Cload
Review: Voltage Degradation
„ Both nMOS and pMOS have voltage
degradation problems
„ nMOS degrades logic ‘1’
„ pMOS degrades logic ‘0’

Vdd−Vth Vdd

0 |Vth|
CMOS Transmission Gate
„ To solve voltage degradation problem, use
both nMOS and pMOS
„ Need both true and complement of control
„ Bi-directional gate
„ When S=0, both FETs are in cutoff (TG modeled as open
switch)
„ Setting S to 1, turns on both FETs (TG modeled as closed
switch) Other symbols used
S
S
A B A B

S’ S’
CMOS Transmission Gate
„ Electrical model of TG

„ Parasitic resistance and capacitance in the MOSFETs

„ When the TG is used in a circuit, it acts as a passive switch
that intrinsically slows the response due to the parasitic RC
structure
CMOS Transmission Gate
„ TGs act as a voltage-controlled switches
„ Used to implement Boolean switching functions
„ Many logic functions can be placed into canonical SOP form
and implemented using TG-based switching logic networks
Example: 2:1 multiplexer circuit
T= D0S + D1S’
CMOS Transmission Gate
„ Example: XOR and XNOR
F(A,B) = AB’ + A’B (XOR)
F’(A,B) = AB + A’B’ (XNOR)
CMOS Transmission Gate:Layout