3-D TSV Interconnects

Technology & Market Analysis

At the Material / Equipment / Device Levels
Report Sample - August 2008
Infineon

Freescale DuPont
Silex
IMEC

Nokia

© 2008
Copyrights © Yole Développement SARL. All rights reserved.
 Why Stacking chips in 3-D?
• Trend is to move from 3D flexible configurations to 3D stacking and then to 3D
IC with TSV:

Æ Package on Package
Æ Stacked dies with Wire Bonds Æ 3D IC integration with TSV

• There are different motivations for the development of 3D IC solutions:

ƒ Form factor: to increase density (achieving the highest capacity / volume ratio)
ƒ Increased electrical performances: to shorten interconnects length (device speed), to
improve electrical performances (reducing electrical parasitances due to RC delays in
RF and DRAM applications) and to strongly reduce chips power consumption
ƒ Heterogeneous integration: to integrate different functional layers (RF, memory, logic,
sensors, imagers, exotic substrate material, …) based on optimized process nodes
ƒ Cost: at some point, 3D integration will be cheaper than shrinking furthermore 2D-SOC
design rules

© 2008 • 2
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 3D IC market drivers summary
Æ The integration of 3D technologies will enable performances, form factor and cost
requirements of the next generation of electronic devices:
“More than Moore”
Heterogeneous integration
Æ Co-integration of RF, logic, memory,
sensors functional layers in a reduced
space

Electrical performances
Æ Shortened interconnects,
removed repeaters &
3D vs. “More Moore” reduced parasitances (RC
Æ 3D can be cheaper delays…)
than going to the n+2
process node?

Density
Æ Achieving the highest
capacity / volume ratio

© 2008 • 3
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 Vias integration schemes:
“Via First” or “Via Last”?

Æ A “Via-First” approach:

CMOS Vias BEOL Thinning Bonding

Æ A “Via-Last” approach:

CMOS+BEOL Vias Thinning Bonding

© 2008 • 4
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 Emerging 3D-TSV Technology platforms

© 2008 • 5
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 Yole’s 3D-TSV market forecasts model
• Yole’s 3D-TSV market forecasts model is based on the continuous update of the following
data informations:

Std. Product Chip sizes 3D Stack TSV Market

Units forecasts (mm2) requirements penetration %
Sources: iSuppli, IC Insights … Sources: Teardown Analysis Reports Sources: Semiconductor &
Packaging fabs Assumptions: Yole

Equipments
Unit forecasts 3-D Fab Modeling 3D TSV Wafer Manufacturing
Materials with TSV+ Yield per product
forecasts
Volume forecasts
Source: TSV+ Cost modeling tool

DuPont

© 2008 • 6
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 3D-TSV wafer forecasts per Industry

© 2008 • 7
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 3D-TSV Equipments & Materials Market Forecasts

© 2008 • 8
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 Yole’s Advanced Packaging Reports &
Newsletters collection now includes:

Æ Monthly newsletter on 3DIC & WLP 3-D TSV Interconnects

Equipment & Materials - 2008 Report
TSV Packaging technologies
ÆRegister for free on:
DuPont

www.i-micronews.com/3DIC.asp E
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3-D TSV Interconnects

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Devices & Systems - 2008 Report

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TSV + Æ NEW Reports: Released in July 2008

Cost Analysis Tool for
your 3D IC manufacturing

3D IC & TSV
WLP & Embedded Die “Top 50” Players Company Profiles
Technologies & Markets

+ Database

Æ Excel™ tool released April 08

Æ Report released in February 08 Æ Report & Database released in October 07

© 2008 • 9
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 3-D TSV Interconnects
Devices & Systems – 2008 Report
Technology & Market Analysis, July 2008

Infineon

Freescale DuPont
Silex
IMEC

Nokia

© 2008
Copyrights © Yole Développement SARL. All rights reserved.
 Table of Content (Main chapters only)
Introduction ...…………………………....……….... 4 Technical challenges to be tackled for 3D ICs … 230
Advanced Packaging Challenges & Trends for 3D stacking Test technologies to be developed for 3-D …………….. 231
3D-TSV interconnects latest Roadmaps with via characteristic Open / Shorts tests, Functionality tests
evolutions
Inspection & Metrology tools
3D EDA Design and thermal software tools …………… 248
Comparison of Competitive 3D Packaging State of the art of current developments
technology platforms ……………………….. 20 Thermal management solutions for 3-D ………………… 262
Edge interconnects / Fan-Out WLP / PoP / Wire Bond / Flip-chip Thermal copper pillar bumps
face to face Micro-cooling chips (air / liquid) developments

3-D Technology platforms & players …….…… 28 Advanced Packaging infrastructure Readiness
3-D WLP Encapsulation
3-D TSV Stacks & Supply chain evolution ……...………………. 280
3-D Interposer modules (Silicon and Glass based) Which 3-D technology platform for which application?
Mapping of different player’s activity
3D-TSV market forecasts Summary ….……..… 48
Forecasts per industry Conclusions & Perspectives ….…………….…… 292
Forecasts per technology platform
Forecasts per market
Forecasts per wafer size Annexe ………………………………………………. 294
3D-TSV Technology Roadmaps & Forecast
detailed per Player & Industry …………….. 67
- CMOS image sensors ……………................. 68
> Trend for stacked DSP with CIS and BSI architectures
- Wireless-SiP …………………………………... 102
> IPD platforms
- MEMS ……………………………..................... 127
- LEDs ……………………………………………. 147
- Memories (Flash & DRAM) ……................... 156 Silex

- Logic 3D-SOC/SiP …………………………..… 199

> Roadmap for progressive 3-D partitioning of different functions
COST Analysis comparing 3DIC Vs. SOC …. 219
Nokia

© 2008 • 11
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 List of Tables / Figures (2006 to 2015 Market Forecasts)
3-D TSV Market forecast Summary:
• Conservative / Likely / Optimistic Scenarios for 3D-TSV Market Ramp
and adoption into the market place …………………………………..… 51
• 3D-TSV Equipments & Materials Market forecasts (M$) ……………. 54
• Impact of 3-D TSV technologies on Semiconductor business ……. 55
• 3D-TSV wafer forecasts:
• per industry (wspy eq.) ……………………………….… 52
• per Market (wspy) ……………………….……………….. 56
• per wafer size diameter (wspy) ……….……………….. 57
• per Technology Platform (wspy eq.) ….……………… 58
• 3D TSV Market segments: Risk analysis per application …………. 60
• Packaging Technologies: 2007 Market Status ………………………. 62
• 3D-TSV Devices forecast:
• per industry (Munits) …………………………………... 63
• per Market (Munits) ……………………………………... 65
• per Technology Platform (Munits) ……...……………. 66
CMOS image sensors 3-D TSV market forecasts:
• Wafer Scale Optics Forecast: Breakdown per applications ….…. 88
• CMOS image sensor devices forecast:
• Breakdown per architecture platform (Munits) ……... 94
• Breakdown per architecture platform (wspy eq.) …… 95
• 3D-WLP CMOS image sensor forecasts:
• per Application (Munits) ……………………………..… 96
• per Application (8“ & 12"wspy) ……………………….. 97
• Breakdown per Resolution (Munits) …………………. 98
• Breakdown per resolution (wafer eq.) ………………. 99
• Breakdown per wafer diameter (wspy) ……………... 100
MEMS 3-D TSV market forecasts:
• 3D-WLP MEMS devices forecast per application (Munits) ………..… 142
• 3D-WLP MEMS wafer forecasts per application …………….………... 144
LED WL-CSP market forecasts:
• 3D WLP interposer for LED application wafer forecast ……………… 155
Stacked / Embedded memories 3-D market forecasts:
• Memory wafers forecast Discrete Vs. 3D Stacked Breakdown …..… 188
• Memory wafers: Breakdown per Mount technology ………………….. 189
• Focus on NAND Flash ……………………………..……. 190
• Focus on NOR Flash ………………………………….… 191
• Focus on DRAM ……………………………………….… 192
• 3D-TSV Memories wafer forecasts:
• Flash vs. DRAM wafer forecasts (wspy) …………….. 193
• NOR / NAND / DRAM / SDRAM breakdown …………. 194
• Breakdown per Application Product (12" wspy) ….... 195
• Via First vs. Via Last (12" wspy) ……………………...…197
Logic chips 3-D market forecasts:
• 3D-TSV Logic / Analog / IO wafer forecast ………………………………. 228
Silex

Wireless SiP 3-D TSV market forecasts:

• 3D-TSV Wireless-SiP wafer forecasts per application (6" wspy) … 125
Nokia

© 2008 • 12
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 3-D TSV Interconnects
Equipment & Materials – 2008 Report
Technology & Market Analysis, July 2008

DuPont
NEC-Schott
EVG SUSS STS Brewer Science

© 2008
Copyrights © Yole Développement SARL. All rights reserved.
 Table of Content (Main chapters only)
Introduction ...........................................................… 4
Market forecasts Summary ……………………….. 21
3-D Equipment market forecasts …………………………. 29
> Breakdown for Wafer Bonders / Chip Bonders / Etching‐Drilling /
Plating / Lithography / Spray coating / Temporary Bonding /  > Thermal management materials
Grinding‐Thinning / Inspection & Metrology / Test tools
Advanced Materials market forecasts …………………………….. 33
> Breakdown for Photo‐resists / Adhesives / Gas /
Advanced Substrates / Specific Chemistries
3D-TSV Manufacturing Challenges ………………. 36
3DIC Enabling technologies …………………………………………… 37
Via first or Via‐last? ……………………………………………………….. 38
Different via shapes & geometries ………………………………… 52
3‐D TSV emerging Supply chain …………………………………….. 58
Equipment & Advanced Materials Tool-Box for
3-D IC integration …………………………………… 60
Analysis of different technologies / Requirements / Tool Capabilities / 
Scenarios / Forecasts / Suppliers involved in:
Via Etching / drilling ……………………………..……………......…..  62
> DRIE & Laser COO
Via Dielectric isolation ………………………………………………….  87
> PECVD / SACVD / Spin‐on & Sprayed dielectric polymers
Via filling methods ………………………………………………….…… 100
> Barrier / Seed layer related technologies
> Polysilicon / Tungsten / Copper plating / Conductive paste
Grinding / Thinning …………………………………………………...… 130
> Equipments & Materials challenge & requirements
Thin Wafer Handling  …………………………………………………… 146
> Equipments & Materials challenge & requirements
© 2008 • 14
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Lithography related technologies ……………………………………. 175
> Micro bump pads & pillars technologies overview
> Materials challenges & requirements for 3‐D 
> Dry films development for 3D‐WLP applications
> Stepper vs. Mask aligner lithography vs. ECPR
Bonding & Final assembly steps  ………………………………..…… 206
> Thermo compression / Direct oxide / Adhesive 
> C2W vs. W2W Bonding
> Cost analysis
Advanced Substrates for 3‐D Technologies ……………….....… 246
Test / Inspection / Metrology solutions for 3‐D ……………… 252
Cost of Ownership for 3-D TSV manufacturing ….. 265
TSV manufacturing CoO & Capital Tools investment necessary for a:
> MEMS fab
> CMOS image sensor fab
> Memory fab
> Logic 3D‐SOC & Wireless‐ SiP fab
CoO comparison of TSV vs. wire bonding vs. PoP
3‐D TSV cost evolution / learning curve improvement over time
Main conclusions & Perspectives ……….………. 307
DuPont
Amkor
STS
 List of Tables & Figures (2006 to 2015 Market Forecasts)
Market forecast Summary ……………..….……….. 21 • Wafer Bonder Chamber Sales forecast (Units / M$) ………... 242
• Conservative / Likely / Optimistic Scenarios • Chip Bonder Equipment Market Forecasts (Units / M$) …… 244
for 3D-TSV Market Ramp ……………………………….…..... 23 • Test / Metrology / Inspection Tools forecasts (Units / M$) … 262
• 3D-TSV Wafer forecasts breakdown:
• per industry (wspy eq.) ……….………………………..…….. 24 Advanced Materials market forecast for 3-D TSV … 84
• per wafer size diameter (wspy) …………………………… 26 • Bosch DRIE Gas Market (in M$) ……………………………….. 84
• per 3‐D Technology Platform ………………………………. 27 • Photo-Resist Materials Volume Forecasts (in Liters / M$) ….. 202
• 3D-TSV Equipments & Materials Market forecasts (M$) … 29 • Specific Chemistries Market Forecasts (in M$) …………….. 121
>  Detailed breakdown for Wafer Bonders / Chip Bonders / Etching‐ >   Detailed breakdown for CMP slurries & Seed/ Barrier / 
Drilling / Plating / Lithography / Spray coating / Temporary Bonding  Electroplating / Stripper / Remover chemistries
/ Grinding‐Thinning / Inspection & Metrology / Test tools • CMP equipment & Materials: Global Market Share ……….... 143
• 3-D TSV Materials Market forecasts (M$) …………….……... 33 • Temporary Wafer Bonding Materials Forecast (in Liters) …... 159
>   Detailed breakdown for Photo‐resists / Adhesives / Gas / • Dicing Tapes Market Forecast (in m²) …………………………. 160
Advanced Substrates / Specific Chemistries
• 3-D Advanced Substrate Market Forecasts (in wafers eq.) ….. 249
• Silicon vs. Glass 3-D Capping Forecasts (in wspy / M$) …….. 250
Equipment market forecasts for 3-D TSV …….… 83
• Via Etching scenarios developed ………………………… 83
Cost Modeling results for 3D TSV Manufacturing … 299
• DRIE chambers Sales Forecasts (Units / M$) ……………. 85
• Cost Analysis synthesis for a NEW 3-D fab ……………….… 299
• Via isolation scenarios developed ……………………..… 97
• Cost Analysis synthesis for a EXISTING 3-D fab …………… 300
• Spray Coating Equipment forecast (Units / M$) …………. 98
• Via Filling scenarios developed …………………………. 127
• Electroplating tools Market forecast (Units / M$) ……….. 128
• Thinning / Grinding Tool Market forecast (Units / M$) …. 144
• 3D TSV Wafer handling scenarios developed …………. 172
• Temporary Bonding tools Market forecasts ….. …….… 173
• Lithography tools Market Forecast (Units / M$) …. ……. 204
• Bonding scenarios developed ………………………….... 211
STS
• Wafer Bonder Vendors Market shares ………………….. 225 DuPont

• Bonding scheme (W2W / C2W) scenarios developed … 239

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 More information on:

www.yole.fr www.i-micronews.com/3DIC.asp

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