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A 1 A
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Answer sheet:
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#2
#3
#4
#5
A A
Name:__________________________________ EE227 Final last 4 SSID_________
A 2 A
#6
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A A
Name:__________________________________ EE227 Final last 4 SSID_________
A 3 A
2 Find the value of R and C1 in a PLL loop filter (One in series with the resistor) assuming
Kvco=66MHz/V, Ipump=0.1ma. Assume Wn=100Khz, and the Vco divider is 23. Assume
the damping factor is 0.7 (10 points)
3 Design a VM type Schmitt trigger with trip points of 1.2V and 1.3V. Assume all transistor
have L=0.24u. Assume 1st Wni=.48u. Assume all L’s are 0.24u. Show devices on
schematic. (10 points)
4 Given a PLL with 12 bit Y and Z dividers, and a restriction on Z that it can range from 4005
to 4009. Find the best value of Y and Z (Smallest error) to generate a VCO frequency of
14.775MHz when FREF is 6.277MHz. Compute all results to 1Hz resolution. Assume Z is
the VCO divider (10 points)
6 Design a 3 bit R-2R D/A converter. Show schematics. Assume R is 10k ohms. (Transistor
sizes not required) (10 points)
8 Why are guard rings used in I/O design. Draw the latch up devices, and show their origin
on a chip view. (10 points)
9 How are high speed buffers implemented? How is Vcm established? Show example
schematics. (10 points)
10 Design a 3 transistor voltage divider providing Vdd/3 and 3/4Vdd using only N transistors.
Calculate device sizes assuming 100ua flows in the divider. (10 points)
A A
Name:__________________________________ EE227 Final last 4 SSID_________
A 4 A
Exam is closed book, no scratch paper. Handy Equations for the Exam
VT VT 0 2 F VSB 2F
1
R
k (VGS VT )
ID k'
W
2L
2(VGS VT )VDS VDS
2
VIL = VT + 1/(kRL)
k
2
2(VGS VT )VDS VDS
2
CJ area
C BS , D CJSW perim
VGS VT , VBS
1
VDS VGS VT PB
CGS width CGSO
k ' N COX N OX CGD width CGDO
tOX
CGB width CGBO
W
k k'
L KN
V DD VTP VTN
k
I D (VGS VT ) 2 KP
2 VM
KN
k
1
ID (VGS VT ) 2 (1 VDS ) KP
2
VOH dVout/dVin = -1 2VTN 1 1.5V DD 2VTN C L
VOL dVout/dVin = -1 kN ln
V DD VTN
2
V DD VTN 0.5V DD t PHL
VM Vout=Vin
ox 2VPN 1 1.5VDD 2VTP CL
Cox kP ln
tox
DDV VTP 2
VDD VTP 0.5VDD t PLH
A A
Name:__________________________________ EE227 Final last 4 SSID_________
A 5 A
2C L VTN V1 V DD VD
t fall I D I S e T 1
k N V DD VTN
2
CL 2V 2VTN V 2 kT
ln DD T
k N V DD VTN V2 q
C in I D I S e T
j
ln
D p Pno Dn N po
C I S qA
t P ,total A' ln EXT L L
C in ln p n
2
BEST e 2.718 ni
Pno
ND
W W
ni 2
L 2 L1 N po
NA
W W
D Diffusion rate
L3 L4
2 L Length of P / N
W W
L 1 L 2
I bias 2
R k'
VGS VTHN
W q
N ' kT
I D I D0 e
L
H WP S W N
kT
k' 0.26mV @ room _ temp
H N WR S DWR q
k 'P
H S
WR CJ AD
k 'N Cd , bot
D MJ
k 'P Vdb
1
PB
CJSW PD
Cd , side MJSW
Vdb
1
PBSW
A A
Name:__________________________________ EE227 Final last 4 SSID_________
A 6 A
KF I DAF
f COX
'
L2
v12/ f
gm
8kT
2 I d
q
2
vtherm
gm
gm0
gm( f )
1 j Zs Cgb Cgs Cgd
id gm vgs
is vgs j Cgb Cgs Cgd
B 'W Vgs Vt
fT
2LCgs
dI ds
gm Vds C
dVgs
g m (linear ) Vds
g m ( sat ) Vgs Vt 2 I D
I DS const
Gm ids gm 2 I D
vgs VGS const
Ipump
Kpd
2
Kpdi * Kvco
Wn
NC1
Wn
* R * C1
2
A A
This is the only piece of paper you will turn in. Please plan to fit all answers on this page!
Answer sheet:
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
11 Draw schematics for a voltage doubler using NMOS transistors and capacitors. (10 points)
12 Find the value of Ipump and R in a PLL loop filter assuming C1 is 100pf (One in series with
the resistor) assuming Kvco=76MHz/V, Assume Wn=200Khz, and the Vco divider is 5.
Assume the damping factor is 0.7 (10 points)
13 Design a VM type Schmitt trigger with trip points of 1.3V and 1.5V. Assume all transistor
have L=0.24u. Assume 1st N device has Wni=.72u. Assume all L’s are 0.24u. Show
devices on schematic. (10 points)
14 Given a PLL with 12 bit Y and Z dividers, and a restriction on Z that it can range from 4005
to 4009. Find the best value of Y and Z (Smallest error) to generate a VCO frequency of
21.314MHz when FREF is 19.3MHz. Compute all results to 1Hz resolution. Assume Z is the
VCO divider (10 points)
15 Draw the schematics for a source coupled cross coupled oscillator. (10 points)
16 Design a 3 bit flash A/D converter. Draw a block diagram. (Transistor sizes not required)
(10 points)
18 Design a three transistor voltage divider providing Vdd/2 and 3/4Vdd using only P
transistors. Calculate device sizes assuming 70ua flows in the divider. (10 points)
19 Show schematics for a two wire high speed driver. Include the impedance matching
feedback loop. (10 points)
20 How is large cross over current eliminated in IO design? Show a representative schematic
(10 points)
Exam is closed book, no scratch paper. Handy Equations for the Exam
VT VT 0 2 F VSB 2F
1
R
k (VGS VT ) V DS
ID k'
W
2L
2(VGS VT )VDS VDS
2
1
R
k
2(VGS VT )VDS VDS
2
2
k (VGS VT )
VIL = VT + 1/(kRL)
VGS VT ,
VDS VGS VT CJ area
C BS , D CJSW perim
VBS
N OX 1
k ' N COX PB
tOX
CGS width CGSO
W
k k' CGD width CGDO
L
CGB width CGBO
k
ID (VGS VT ) 2
2
KN
k V DD VTP VTN
ID (VGS VT ) 2 (1 VDS ) KP
2 VM
KN
VOH dVout/dVin = -1 1
VOL dVout/dVin = -1 KP
VM Vout=Vin
2VTN 1 1.5V DD 2VTN C L
ox kN ln
Cox
tox V DD VTN
2
V DD VTN 0.5V DD t PHL
QB 2 Si qN A 2 F
K NI
V DD VTN
Q B QOX K NF
VT GC 2 F V ID
C OX C OX K NI
1
Q B 0 QOX Q B Q B 0 K NF
GC 2 F
C OX C OX C OX
K PI
1 V DD VTP
2q Si N A K PF
C OX V I LI
K PI
(300) 1
(T ) K PF
T / 300 a
VOL VDD/(kRL(VDD-VT)+1)
2
WNF VTRIG VTN WNI VD
I D I S e T 1
LNF VDD VTRIG LNI
2
WPF VDD VTP VTRIG WPI kT
T
LPF VTRIG LPI
q
T~26mv at room temperature
2C L VTN V1 V DD
t fall VD
k N V DD VTN I D I S e T
2
CL 2V 2VTN V 2 D p Pno Dn N po
ln DD
k N V DD VTN V2 I S qA
L L
p n
C ni 2
ln EXT Pno
C in ND
j
ln ni 2
N po
C NA
t P ,total A' ln EXT
C in ln D Diffusion rate
BEST e 2.718 L Length of P / N
W W
L 2 L1
VGS VTHN
W W W q
I D I D0 e N ' kT
L3 L4 L
W
2 kT
W 0.26mV @ room _ temp
q
L 1 L 2
I bias
R 2k '
CJ AD
Cd , bot MJ
H WP S W N Vdb
1
PB
k 'N
H WR S DWR CJSW PD
k 'P Cd , side MJSW
Vdb
H S 1
WR PBSW
k 'N
D
k 'P
Vdd=2.5V K’n=138u K’p=51u Vtn=0.52V Vtp=-0.58V L=1u
PROCESS PARAMETERS N+ACTV P+ACTV POLY N+BLK PLY+BLK MTL1 MTL2 UNITS
Sheet Resistance 4.2 3.3 3.8 59.6 184.0 0.07 0.07 ohms/sq
Contact Resistance 5.5 4.8 4.7 2.92 ohms
Gate Oxide Thickness 57
angstrom
gm0
gm( f )
1 j Zs Cgb Cgs Cgd
id gm vgs
is vgs j Cgb Cgs Cgd
B 'W Vgs Vt
fT
2LCgs
dI ds
gm Vds C
dVgs
g m (linear ) Vds
g m ( sat ) Vgs Vt 2 I D
I DS const
Gm ids gm 2 I D
vgs VGS const
Ipump
Kpd
2
Kpdi * Kvco
Wn
NC1
Wn
* R * C1
2
This is the only piece of paper you will turn in. Please plan to fit all answers on this page!
Answer sheet:
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
21 Draw schematics for a circuit who’s delta V output is the square of the input delta V. (10
points)
22 Find the value of R and C1 in a PLL loop filter (One in series with the resistor) assuming
Kvco=96MHz/V, Ipump=0.2ma. Assume Wn=70Khz, and the Vco divider is 12. Assume the
damping factor is 0.8 (10 points)
23 Design a VM type Schmitt trigger with trip points of 1.22V and 1.54V. Assume all transistor
have L=0.24u. Assume 1st Wpi=72u. Assume all L’s are 0.24u. Show devices on
schematic. (10 points)
24 Given a PLL with 12 bit Y and Z dividers, and a restriction on Z that it can range from 4005
to 4009. Find the best value of Y and Z (Smallest error) to generate a VCO frequency of
7.2MHz when FREF is 15.35MHz. Compute all results to 1Hz resolution. Assume Z is the
VCO divider (10 points)
26 Design a 3 bit current mode D/A converter. Show schematics. Transistor sizes not
required. (10 points)
28 What is the algorithm used in an algorithmic A/D converter? Explain how it works. (10
points)
29 Why must high speed busses be terminated in characteristic impedance? (10 points)
30 Design a 3 transistor voltage divider providing Vdd/3 and 3/4Vdd using only N transistors.
Calculate device sizes assuming 100ua flows in the divider. (10 points)
Exam is closed book, no scratch paper. Handy Equations for the Exam
VT VT 0 2 F VSB 2F
1
R
k (VGS VT ) V DS
ID k'
W
2L
2(VGS VT )VDS VDS
2
1
R
k
2(VGS VT )VDS VDS
2
2
k (VGS VT )
VIL = VT + 1/(kRL)
VGS VT ,
VDS VGS VT CJ area
C BS , D CJSW perim
VBS
N OX 1
k ' N COX PB
tOX
CGS width CGSO
W
k k' CGD width CGDO
L
CGB width CGBO
k
ID (VGS VT ) 2
2
KN
k V DD VTP VTN
ID (VGS VT ) 2 (1 VDS ) KP
2 VM
KN
VOH dVout/dVin = -1 1
VOL dVout/dVin = -1 KP
VM Vout=Vin
2VTN 1 1.5V DD 2VTN C L
ox kN ln
Cox
tox V DD VTN
2
V DD VTN 0.5V DD t PHL
QB 2 Si qN A 2 F
K NI
V DD VTN
Q B QOX K NF
VT GC 2 F V ID
C OX C OX K NI
1
Q B 0 QOX Q B Q B 0 K NF
GC 2 F
C OX C OX C OX
K PI
1 V DD VTP
2q Si N A K PF
C OX V I LI
K PI
(300) 1
(T ) K PF
T / 300 a
VOL VDD/(kRL(VDD-VT)+1)
2
WNF VTRIG VTN WNI VD
I D I S e T 1
LNF VDD VTRIG LNI
2
WPF VDD VTP VTRIG WPI kT
T
LPF VTRIG LPI
q
T~26mv at room temperature
2C L VTN V1 V DD
t fall VD
k N V DD VTN I D I S e T
2
CL 2V 2VTN V 2 D p Pno Dn N po
ln DD
k N V DD VTN V2 I S qA
L L
p n
C ni 2
ln EXT Pno
C in ND
j
ln ni 2
N po
C NA
t P ,total A' ln EXT
C in ln D Diffusion rate
BEST e 2.718 L Length of P / N
W W
L 2 L1
VGS VTHN
W W W q
I D I D0 e N ' kT
L3 L4 L
W
2 kT
W 0.26mV @ room _ temp
q
L 1 L 2
I bias
R 2k '
CJ AD
Cd , bot MJ
H WP S W N Vdb
1
PB
k 'N
H WR S DWR CJSW PD
k 'P Cd , side MJSW
Vdb
H S 1
WR PBSW
k 'N
D
k 'P
Vdd=2.5V K’n=138u K’p=51u Vtn=0.52V Vtp=-0.58V L=1u
PROCESS PARAMETERS N+ACTV P+ACTV POLY N+BLK PLY+BLK MTL1 MTL2 UNITS
Sheet Resistance 4.2 3.3 3.8 59.6 184.0 0.07 0.07 ohms/sq
Contact Resistance 5.5 4.8 4.7 2.92 ohms
Gate Oxide Thickness 57
angstrom
gm0
gm( f )
1 j Zs Cgb Cgs Cgd
id gm vgs
is vgs j Cgb Cgs Cgd
B 'W Vgs Vt
fT
2LCgs
dI ds
gm Vds C
dVgs
g m (linear ) Vds
g m ( sat ) Vgs Vt 2 I D
I DS const
Gm ids gm 2 I D
vgs VGS const
Ipump
Kpd
2
Kpdi * Kvco
Wn
NC1
Wn
* R * C1
2
This is the only piece of paper you will turn in. Please plan to fit all answers on this page!
Answer sheet:
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
31 Draw schematics for a Schmitt trigger relaxation oscillator. (10 points)
32 Find the value of R and C1 in a PLL loop filter (One in series with the resistor) assuming
Kvco=96MHz/V, Ipump=0.2ma. Assume Wn=100Khz, and the Vco divider is 3. Assume the
damping factor is 0.8 (10 points)
33 Design a VM type Schmitt trigger with trip points of 1.4V and 1.5V. Assume all transistor
have L=0.24u. Assume device is symmetrical, and Wn=4u. Assume all L’s are 0.24u.
Show devices on schematic. (10 points)
34 Given a PLL with 12 bit Y and Z dividers, and a restriction on Z that it can range from 4005
to 4009. Find the best value of Y and Z (Smallest error) to generate a VCO frequency of
14.571MHz when FREF is 17.150MHz. Compute all results to 1Hz resolution. Assume Z is
the VCO divider (10 points)
35 Draw the schematics for a current 7 stage starved oscillator with start/stop control. (10
points)
36 Design a 3 bit resistor string DAC. Draw schematics. Do not show transistor sizes. (10
points)
37 What is the algorithm used in an algorithmic D/A converter? Explain how it works. (10
points)
38 How is large cross over current eliminated in I/O design? (10 points)
39 Draw the schematics for a 2 wire high speed transmitter. Include the Vcm feedback loop.
(10 points)
40 Design a 3 transistor voltage divider providing Vdd/2 and 3/4Vdd using only P transistors.
Calculate device sizes assuming 80ua flows in the divider. (10 points)
Exam is closed book, no scratch paper. Handy Equations for the Exam
VT VT 0 2 F VSB 2F
1
R
k (VGS VT ) V DS
ID k'
W
2L
2(VGS VT )VDS VDS
2
1
R
k
2(VGS VT )VDS VDS
2
2
k (VGS VT )
VIL = VT + 1/(kRL)
VGS VT ,
VDS VGS VT CJ area
C BS , D CJSW perim
VBS
N OX 1
k ' N COX PB
tOX
CGS width CGSO
W
k k' CGD width CGDO
L
CGB width CGBO
k
ID (VGS VT ) 2
2
KN
k V DD VTP VTN
ID (VGS VT ) 2 (1 VDS ) KP
2 VM
KN
VOH dVout/dVin = -1 1
VOL dVout/dVin = -1 KP
VM Vout=Vin
2VTN 1 1.5V DD 2VTN C L
ox kN ln
Cox
tox V DD VTN
2
V DD VTN 0.5V DD t PHL
QB 2 Si qN A 2 F
K NI
V DD VTN
Q B QOX K NF
VT GC 2 F V ID
C OX C OX K NI
1
Q B 0 QOX Q B Q B 0 K NF
GC 2 F
C OX C OX C OX
K PI
1 V DD VTP
2q Si N A K PF
C OX V I LI
K PI
(300) 1
(T ) K PF
T / 300 a
VOL VDD/(kRL(VDD-VT)+1)
2
WNF VTRIG VTN WNI VD
I D I S e T 1
LNF VDD VTRIG LNI
2
WPF VDD VTP VTRIG WPI kT
T
LPF VTRIG LPI
q
T~26mv at room temperature
2C L VTN V1 V DD
t fall VD
k N V DD VTN I D I S e T
2
CL 2V 2VTN V 2 D p Pno Dn N po
ln DD
k N V DD VTN V2 I S qA
L L
p n
C ni 2
ln EXT Pno
C in ND
j
ln ni 2
N po
C NA
t P ,total A' ln EXT
C in ln D Diffusion rate
BEST e 2.718 L Length of P / N
W W
L 2 L1
VGS VTHN
W W W q
I D I D0 e N ' kT
L3 L4 L
W
2 kT
W 0.26mV @ room _ temp
q
L 1 L 2
I bias
R 2k '
CJ AD
Cd , bot MJ
H WP S W N Vdb
1
PB
k 'N
H WR S DWR CJSW PD
k 'P Cd , side MJSW
Vdb
H S 1
WR PBSW
k 'N
D
k 'P
Vdd=2.5V K’n=138u K’p=51u Vtn=0.52V Vtp=-0.58V L=1u
PROCESS PARAMETERS N+ACTV P+ACTV POLY N+BLK PLY+BLK MTL1 MTL2 UNITS
Sheet Resistance 4.2 3.3 3.8 59.6 184.0 0.07 0.07 ohms/sq
Contact Resistance 5.5 4.8 4.7 2.92 ohms
Gate Oxide Thickness 57
angstrom