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Chap. 11 in
“Verilog HDL– A Guide to Digital Design and Synthesis”
by Samir Palnitkar
Learning Objectives
Describe basic MOS switches nmos, pmos, and cmos
1
Switch-Level Modeling
Switch-Modeling Elements
MOS switches
CMOS switches
Bidirectional Switches
Power and Ground
Resistive Switches
Delay specification on switches
Examples
CMOS inverter
CMOS nor gate
2-to-1 multiplexer
simple CMOS flip-flop
MOS Switches
two types of MOS switches can be defined with the
keywords, nmos and pmos nmos n1(out,data,control);
pmos p1(out,data,control);
control control
NMOS PMOS
control control
nmos pmos
0 1 x z 0 1 x z
0 z 0 L L 0 0 z L L
data
data
1 z 1 H H 1 1 z H H
L: 0 or z x z x x x x x z x x
H: 1 or z z z z z z z z z z z
Switch-Level Modeling Dept. of CSIE, DYU 4
2
CMOS Switches
CMOS switches are declared with the keyword
cmos
the ncontrol and pcontrol are
normally complements of each other
when ncontrol signal is 1 pcontrol
and pcontrol signal is 0
the switch conducts
data out
when ncontrol signal is 0
and pcontrol signal is 1
the output of the switch is z
ncontrol
cmos c1(out,data,ncontrol,pcontrol);
CMOS
nmos (out,data,ncontrol);
pmos (out,data,pcontrol);
Bidirectional Switches
three keywords are used to define bidirectional
switches
tran: acts as a buffer between inout1 and inout2
tranif0: connects inout1 and inout2 only if control
signal is 0
tranif1: connects inout1 and inout2 only if control
signal is 1 control
inout1 inout2 inout1 inout2
tran tranif0
control
tran t1(inout1,inout2);
tranif0 (inout1,inout2,control); inout1 inout2
tranif1 (inout1,inout2,control); tranif1
3
Power and Ground
the power (Vdd, logic 1) and
ground (Vss, logic 0) sources
needed when transistor-level circuits are designed
defined with keywords supply1 and supply0
place logical 1 and 0 continuously on nets
supply1 vdd;
supply0 vss;
Resistive Switches
4
Delay specification on switches
MOS and CMOS switches
delays are optional and appear immediately after the
keyword for the switch
rise, fall, and turn-off delays
zero, one, two, or three delays
Specify blocks
pin-to-pin delays and timing checks can also be specified
5
Switch-Level Modeling
Switch-Modeling Elements
MOS switches
CMOS switches
Bidirectional Switches
Power and Ground
Resistive Switches
Delay specification on switches
Examples
CMOS inverter
CMOS nor gate
2-to-1 multiplexer
simple CMOS flip-flop
Examples
CMOS Inverter in out
Vdd
module my_inv(out,in);
output out;
input in;
in out
supply1 pwr;
supply0 gnd;
pmos p1(out,pwr,in);
nmos n1(out,gnd,in);
gnd
endmodule
6
Examples (Cont’d)
CMOS Nor Gate
// Define nor gate a out Vdd
module my_nor(out,a,b);
b pwr
output out;
input a,b; module stimulus;
wire c; wire OUT; c
reg A,B;
supply1 pwr; wire c;
supply0 gnd;
my_nor nor1(OUT,A,B); out
pmos pb(c,pwr,b);
pmos pa(out,c,a); initial
nmos na(out,gnd,a); begin a b
nmos nb(out,gnd,b); A=1’b0; B=1’b0;
#5 A=1’b0; B=1’b1;
endmodule #5 A=1’b1; B=1’b0; gnd
#5 A=1’b1; B=1’b1;
end
endmodule
Examples (Cont’d)
a 2-to-1 multiplexer using CMOS Switches
i0 2-to-1 Mux
2-to-1 out
i1 Mux
i0
S
//2-to-1 mux using switches sbar out
module mux_2to1(out,s,i0,i1);
output out; i1
input s,i0,i1;
wire sbar;
my_inv not1(sbar,s);
cmos c1(out,i0,sbar,s);
cmos c2(out,i1,s,sbar);
endmodule S
7
Exercise 4-to-1 MUX
Switch-level multiplexer
a 4-to-1 multiplexer with 2 select signals
i0 s1 s0 out
i1 4-to-1 0 0 i0
out
i2 Mux 0 1 i1
i3
1 0 i2
1 1 i3
s1 s0
//4-to-1 mux using switches
module mux_4to1(out,s0,s1,i0,i1,i2,i3);
output out;
input s0,s1,i0,i1,i2,i3;
. . .
endmodule
Examples (Cont’d)
a level-sensitive CMOS flip-flop
switches C1 and C2 are CMOS switches
complement of the clock is fed to the ncontrol input of C2
C1 is closed if clock = 1
C2 is closed if clock = 0
d qbar
module cff(q,qbar,d,clk); FF
output q,qbar; clock
q
input d,clk;
wire e, nclk;
my_inv not1(nclk,clk); d C1 e qbar
cmos c1(e,d,clk,nclk);
cmos c2(e,q,nclk,clk); C2
my_inv not2(qbar,e);
my_inv not3(q,qbar); clock
q
endmodule
8
Exercises
1. draw the circuit diagrams for the following 2-input gates
(using nmos and pmos switches), and
write the Verilog descriptions for the circuits
a) xor
b) and
c) or
2. Design the 1-bit full-adder shown below using the xor, and and
or gates built above
a
b sum
c_out
c_in