New Designs of Redundant-Binary Full Adders and Its

Applications
Zine Abid Wei Wang
ECE Department, University of Western Ontario College of Nanoscale Science and Engineering
London, Ontario, Canada University at Albany, NY, USA

from new algorithms. All the proposed designs have been

Abstract—New designs of Redundant Binary full Adders implemented in 0.18µm and 0.35µm CMOS technologies.
are proposed for redundant binary system, and
implemented using 0.18Pm CMOS technology. The II. PPM ADDER BASICS
proposed full adder designs require low number of
transistors and show lower power dissipation and reduced A PPM adder performs the operation: x   y  x 2t   u  ,
time delay compared to currently available designs. These which is an addition of a redundant number x (where
new designs can be widely used for computer arithmetic x x   x  ) to an unsigned binary number y , resulting in
units in redundant binary systems. As case studies, two another redundant number expressed by an interim sum u 
efficient on-line multipliers are implemented using the
and a transfer digit t  . The input bits are defined as
new full adders, providing improved performance while
requiring lower number of transistors. x  , x  , y  {0,1} and the output bits are t  , u   {0,1} . In
redundant binary signed digit system, three possible digits {1,
I. INTRODUCTION 0, -1} can be encoded using two bits (Table I). Hence, each
signed digit is represented as x x   x  , where
Low power and high speed operation of a digital system,
including on-line multipliers and dividers, is greatly x  , x   {0,1} and x  {1, 0,1} .
influenced by the performance of its full adders. Among such The addition operation, performed by a PPM adder, is:
components is the Plus-Plus-Minus (PPM) adder and hence
improving its design helps meet the design constraints. PPM x  y 2t   u  , where x is the redundant number expressed
adders are based on the Redundant Binary (RB) number as: x x   x  therefore: x   x   y 2t   u  . Encoding of
system, which differs from conventional binary number the digit x , where x  
x  x , using radix-2 redundant
system in that the individual digit of an RB number can number system.
represent more than two values (binary 0 and 1). A radix-2
redundant signed-digit number system is based on a digit set x x x x { x ˜ x
S ^1, 0, 1` , where each digit can assume any of the three 0 0 0 00
values from the set S instead of just the two values, 0 and 1, as -1 0 1 01
in standard binary number system. Consequently, redundancy 1 1 0 10
is introduced in the number system. Such representation is 0 1 1 11
very advantageous while designing high speed systems, since
it allows “carry-free” addition [1-3]. In redundant binary 
Using the truth table, the interim sum u and the transfer digit
signed digit number system, the signed-digit operation is taken t  can be expressed by the following Boolean expressions:
care of by the PPM adder and consequently there is no need
for an explicit mechanism to handle signed digit number. u x x y  x x y  x x y  x x y (1a)
In this paper, we carry out a comprehensive study of new t     
x x yx x yx x yx x y    
(1b)
efficient designs of the PPM 1-bit adders, using different
number of transistors, for redundant number system
III. COMPARISON OF PPM ADDERS
applications. The first proposed design has 10 transistors only,
the lowest number possible of transistor, but suffers from Full adders are designed targeting a reduction in the power
output voltage level degradation which can be reduced by consumption, time delay and chip area. Therefore, reducing
proper design but can not be alleviated except by adding more the number of transistors in a PPM Adder, from more than 20
transistors. Three more PPM adders with 12, 14 and 16 [1,4,5] to 16 transistors (16-T) or less, without compromising
transistors are also designed and show improved its performance is presented in this paper. We recently
characteristics. Each of the four adders (10-Transistor (10-T), developed four new designs of PPM adders in [8]. The 10-T
12-T, 14-T, and 16-T) is designed using two configurations, adders is presented first then its characteristics are improved
based on the sharing and the balanced methods and derived by adding two transistors each time, to obtain a 12-T, a 14-T ,

978-1-4244-1684-4/08/$25.00 ©2008 IEEE 3366

and a 16-T PPM adders. Two variations of each PPM adder
design, called set-1 and set-2, are proposed. Set-1 adder is
based on sharing method (part of the circuit is shared to
generate the two outputs) and the generation of one output
depends on the other output signal, as shown below. Set-2
design is derived from a new algorithm, where both output
bits are generated simultaneously (called balanced method), as
shown next.
Based on the truth table, the logic functions of
and 2 of the PPM adder is obtained as:
u ( x  †x  † y )
Thus, the output u  can be generated by using two XNOR
gates. The generation of t  for the set-1 PPM adder is
obtained from (1b) as:
t x ( x † y)  x ( x †y)
Since x   {0,1} and x   {0,1} , we have either x 
x  x  . If x  x  , then t  u  . Otherwise, when x 
then t  x  .
Since x  x  œ x  †x  1 and x  x  œ x  †x  0 , the
signal x  †x  can be used as the control signal for two pass
gates to generate the correct output t  . If x  †x  1 , then
t  x  ; otherwise t  u  .
The second set (set-2) of PPM adder is an improvement
relative to the first set (set-1) of PPM adder, with a balance
generation of the output signals u  and t  . The resultant
improvement is due to the fact that the generation of signal t 
does not depend on the signal u  . Based on the truth table, the
logic function of t  , for the set-2 of the PPM adder, is
obtained as:
t  x  ( x  † x  )  y ( x  †x  ) (2c)
Since for x  x œ x † x 0 then t 
     
x x œ x †x 0 then t x . One XNOR gate and
one multiplexer are used to produce the output digit t  . This
design allows a simultaneous generation of both output digits
(balanced method) for set-2 Adder in contrast to set-1 adder
where the generation of u  is required to generate t  . The
following three equations summarize the above analysis:
u y ( x  †x  )  y ( x  † x  )
       
t x ( x † x )  u ( x †x )
t x  ( x  † x  )  y ( x  †x  )
where z ( x  † x  ) and z x  †x 
Based on equation (3a) and (3b), the interim sum ( u  ) and the
transfer digit ( t  ) for the proposed set-1 PPM adders can be
generated. Similarly (3a) and (3c) can be implemented for set-
2 of the proposed PPM adder. The above equation (3b) show
that the generation of the output ( t  ) is achieved by sharing
the u  sub-circuit. However, from equation (3c) it is evident
that the generation of signal t  does not depend on the signal
u  . All the proposed designs are implemented using pass
transistor logic and transmission gates and uses 10, 12, 14 or
16 transistors. The detailed analyses are summarized as
follows.

u for the set-1
(2a)
(a) (b)
(2b)
x  or
x ,
(c) (d)
(e) (f)
Figure 1. Designs for set 1 10-T (a), set 2 10-T adder (b), set 1 12-T (c) and
set 1 14-T (d), set 1 16T (e), and set 2 16 T (f) PPM adders.
A. Proposed 10-T PPM Adders
Based on equations (3a), (3b) and (3c), two sets of PPM
adders are proposed as shown in Fig. 1. The number of
transistors in the proposed PPM adder design can be reduced
to a minimum of 10 at the expense of degraded output voltage
level due the threshold voltage ( Vt ) loss. This is possible by
y . While for 
using two 4-transistors XNOR gates to generate u and two

Pass gates to generate t . However, these two gates (XNOR
and pass-gate) are based on pass-transistor-logic causing
threshold voltage VTN (threshold voltage of the n-MOS)
losses for some specific input sets. It is know that n-MOS pass
transistors suffers from voltage loss when transmitting logic 1
while p-MOS degrades the transmission of logic 0 voltage-
level by VTP (threshold voltage of the p-MOS) instead of the
y z  yz (3a)
ideal 0V. Table I shows the theoretical predictions of the

x zu z (3b)  
voltage levels of the output bits ( t and u ) for all possible
x z  y z (3c) eight input sets. The logic ‘1’ output voltage of the 10-
Transistor PPM adder may be degraded to VDD  2VT instead
of VDD . This might lead to an ambiguous or even erroneous
output for 0.18Pm and subsequent CMOS technology nodes.
The results for the shared and balance methods are the same in
terms of voltage level degradation. However, the time delay in

generating t is larger in the case of the shared method.
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B. Proposed 12-T PPM Adders TABLE II. FOR THE OUTPUT
LEVELS OF THE 12-T PPM ADDER FOR EIGHT SETS OF INPUTS
This is an improved design achieved by adding two transistors t t
x y x z x † x z u
to the previous 10-T PPM design as shown in Fig. 1. The (shared) (balanced)
voltage level may degrade by up to one VT for certain input 0 0 0 VDD 0 0 VT VT
sets, as shown in Table II, instead of 2VT . Here VT is the 0 0 VDD 0 VDD VDD 0 0
threshold voltage of the MOSFET transistor while VDD is the 0 VDD 0 VDD 0 VDD - VT VDD - VT VDD
0 VDD VDD 0 VDD 0 0 0
supply voltage. The PPM design based on the sharing method

VDD 0 0 0 VDD VDD VDD - VT VDD - VT
(set-1) may suffers from glitches at the output ( t ) and longer VDD 0 VDD VDD - VT 0 0 VT VT

time delay since the generation of t+ depend on the signal u VDD VDD 0 0 VDD 0 VDD - VT VDD - VT
leading to an accumulation of the time delay. The second PPM VDD VDD VDD VDD - VT 0 VDD - VT VDD - VT VDD

adder design (set-2) generates the two output signals ( t and
 TABLE III. FOR THE OUTPUT
u ) simultaneously which should results in a better
LEVELS OF THE 14-T ADDER FOR EIGHT SETS OF INPUTS
performance. The voltage level degradation may be y
x x z x  †x  z u t
detrimental to the correct performance of this design
0 0 0 VDD 0 0 0
especially for 0.18Pm and subsequent CMOS technologies, as
0 0 VDD 0 VDD VDD 0
some of the outputs maybe ambiguous or even erroneous.
0 VDD 0 VDD 0 VDD VDD
C. Proposed 14-Transistor PPM adders 0 VDD VDD 0 VDD 0 0
VDD 0 0 0 VDD VDD VDD
Two additional transistors are added to the 12-T design to
VDD 0 VDD VDD - VT 0 0 0
eliminate output voltage losses resulting in a 14-T adder with
better performance (Fig. 1). The proposed two designs have VDD VDD 0 0 VDD 0 VDD
VDD VDD VDD VDD - VT 0 VDD VDD
output voltage levels (of the signals u  and t  ) with no
voltage degradation. The output signal for both the sharing TABLE IV. FOR THE OUTPUT
and balanced designs have full voltage swing, thus the noise LEVELS OF THE 16-T ADDER FOR EIGHT SETS OF INPUTS
margins of these new designs are not compromised. However x y x z x  †x  z u t
under certain input sets, some internal nodes still suffer from 0 0 0 VDD 0 0 0
voltage ( Vt ) loss. Tables III shows the output levels of the 14- 0 0 VDD 0 VDD VDD 0
T adder for the eight sets of inputs. 0 VDD 0 VDD 0 VDD VDD
0 VDD VDD 0 VDD 0 0
D. Proposed 16-Transistor PPM adders VDD 0 0 0 VDD VDD VDD
A further improvement of the 14-T PPM adders is achieved by VDD 0 VDD VDD 0 0 0
adding two more transistors as shown in Fig. 1. All its internal VDD VDD 0 0 VDD 0 VDD
nodes have full voltage swing in contrast to the 14-transistor VDD VDD VDD VDD 0 VDD VDD
PPM adder design. This is to avoid possible erroneous
operation at 0.13um or subsequent CMOS technology; the
added two transistors are for the complete elimination of any E. Implementation Results of the PPM Adders
voltage loss at any node in the circuit. The 6-transistors XNOR The power dissipation and the time delay of the proposed
gate and the two complementary transmission gates, have no PPM adders are computed when implemented in 0.18 um
threshold voltage loss when transmitting logic 1 or 0 signals. CMOS technology nodes. All the values indicated in Table V
Table IV shows the full swing output levels of the 16-T adder have been obtained at 125MHz under a capacitive load of
for eight sets of inputs. Therefore, the proposed new PPM 10fF. In most designs today, the primary tradeoff is between
adders, requiring 16 transistors, generates ideal output voltage power and delay and therefore the Energy Delay Product
  (EDP) has been used for benchmarking the performance of
levels for both u and t .
these circuits. The longest critical path delay values are
TABLE I. OUTPUT VOLTAGE LEVELS OF THE 10-TRANSISTOR PPM ADDER
considered for each adder which covers all 56 transitions [7].
y Reducing the number of transistors in the design of the PPM
x x z x  †x  u t  (shared) t  (balanced)
adder to below 14 compromises the adder performance and
0 0 0 VDD 0 0 0
may lead to ambiguous outputs. Pass transistors are used
0 0 VDD 0 VDD VT VT instead of transmission gates to achieve such reduction. It is
0 VDD 0 VDD VDD – VT VDD – VT VDD – VT known that n-MOS pass transistors suffers from voltage loss
0 VDD VDD 0 0 VT VT when transmitting logic 1 while p-MOS degrades the
VDD 0 0 0 VDD VDD VDD transmission of logic 0 voltage-level to VTP (threshold voltage
VDD 0 VDD VDD - VT 0 0 0 of the p-MOS) instead of the ideal 0V. The 10- or 12-
VDD VDD 0 0 0 VDD VDD transitors Adders suffer from output voltage level degradation.
VDD VDD VDD VDD - VT VDD - VT VDD - 2VT VDD - 2VT This is in contrast to the ideal output voltage level obtained by
the 14 and 16 Transistor PPM adders. Body effect makes the

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value if the threshold voltage higher resulting in even worse adder designs in Table VI and Table VII. The results indicate
output voltage level degradation for the 10-T and 12-T adders. a significant improvement in terms of lower power
TABLE V. SIMULATION consumption and higher speed in addition to a reduction in the
RESULTS OF PPM ADDERS IN 0.18PM CMOS TECHNOLOGY chip-area (lower number of transistors) as a result of the use of
Power Delay EDP u1024
Output voltage the proposed 14 transistors PPM adder designs compared to
Adder type
(PW) (ns) (J s)
levels Losses the previously described 24 transistor PPM designs [4].
(worst cases)
Set-1 10-T PPM -- -- -- Logic 1: VDD-2VT TABLE VI. SIMULATION
Set-2 10-T PPM -- -- -- Logic 0: 2VT RESULTS FOR ARCHITECTURE-1
Set-1 12-T PPM 15.00 1.191 21.27 Logic 1: VDD-VT Architecture-1 [2] Delay (ns) Power (PW) EDP u1024 (J-s)
Set-2 12-T PPM 15.51 0.332 01.70 Logic 0: VT 24-T PPM 0.514 67.96 17.9
Set-1 14-T PPM 14.70 0.449 02.96 Ideal 14-T PPM (Set-1) 0.403 58.24 9.4
Set-2 14-T PPM 15.79 0.343 01.86 Ideal 14-T PPM (Set-2) 0.365 57.72 7.6
Set-1 16-T PPM 17.23 0.503 04.35 Ideal
TABLE VII. SIMULATION
Set-2 16-T PPM 17.75 0.375 02.50 Ideal
RESULTS FOR ARCHITECTURE-2
24T-PPM [1] 23.12 0.518 06.20 Ideal Architecture-2 [2] Delay (ns) Power (PW) EDP u1024 (J-s)
24-T PPM 0.509 93.8 24.3
The PPM design based on the sharing method (set-1) may 14-T PPM (Set-1) 0.387 89.32 13.3

suffers from glitches at the output ( t ) and longer time delay 14-T PPM (Set-2) 0.275 91.45 6.9

since the generation of t depends on the signal u- leading to
an accumulation of the time delay. The second PPM adder V. CONCLUSION
 
design (set-2) generates the two output signals ( t and u ) This study is the first comprehensive study in PPM adder
simultaneously which should results in a better performance. design. New PPM adder designs were analyzed based on a
sharing and balanced format derived from the PPM addition
It is evident from Table V that the proposed 14-T PPM Adder
equation and its corresponding truth table. Based on the
(set 2) has the lowest power dissipation with the shortest time
implementation results of 0.18um CMOS technology, the
delay compared to other designs that do not suffer from output
proposed 14- and 16-transistor designs have lower power
voltage level degradation. The time delay for the 14-T PPM
consumption and higher speed while requiring fewer
Adder (set 2) is smaller than that of the 24-T and the 14-T set-
transistors compared to the previously published PPM adders.
1 designs by 34% and 24% respectively. This is partially due

The 10- and 12-transistor designs, requiring the lowest
to the transfer digit t being generated independently from the possible number of transistors, have acceptable operation in

digit u . The two new 14-T PPM adders have an some input cases but their output voltage level degradation is
improvement of more than 31% in terms of power dissipation sometimes severe and unacceptable. The proposed new
when compared to the previously proposed 24-T PPM adder designs can be widely used for computer arithmetic units in
design [4]. The proposed 16-T PPM adder design has a close redundant binary systems and other applications. As a case
performance to the 14-T PPM adders (within 13%). These study, the proposed 14 transistors PPM adders are used to
designs, of the 14-T and 16-T PPM adders, are efficient in build a hybrid radix-2 on-line redundant multiplier. A
terms of speed, power consumption and area when compared significant reduction in power consumption, time delay, and
to the previously proposed PPM designs [4] [5]. Therefore, the area has been achieved in this multiplier implementation.
proposed designs are very attractive for area-efficient and low-
power and high speed applications. REFERENCES
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