IP Core Product Data Sheet 

DFP Adder Units 
DecAdd64/128 

DecAdd64 and DecAdd128 IP core units are Applications

novel DFP Adder designs, offered in 64-bit and
⇒ DFPA units for next generation processors
128-bit versions. The Adder unit computes the
⇒ DFPA on-chip co-processors
Sum or the Difference of two vector Operands.
⇒ DFPA accelerator boards
Inputs are encoded in Decimal Interchange
Format. The product is fully compliant with the
IEEE 754-2008 Standard.

IP Deliverable
Deliverable depends on the type of licensing
Key Features agreement and the negotiated business model. The
following items could be included:
⇒ Full IEEE 754-2008 compliance
⇒ Source code:
⇒ Decimal128 (34 decimal digits) format support
⇒ Decimal Interchange format with Densely Packed
▪ VHDL source code

Decimal (DPD) encoding support ▪ VERILOG source code

⇒ Seven rounding modes support ▪ Encrypted or plain text EDIF netlist
⇒ Automatic pipelining selectable with arbitrary ⇒ FPGA code versions, optimized for either speed
number of stages or area
⇒ Result is available at every clock cycle ⇒ VHDL & VERILOG test bench environments
⇒ Overflow, Underflow, Invalid, and Inexact operation ⇒ Full test suites compliant with IEEE 754-2008
flags standard.
⇒ Tested with over 500,000 test cases compliant with ⇒ Technical documentation
IEEE 754-2008 format ⇒ HDL core specification
⇒ Full DFP accuracy and precision support ⇒ Synthesis scripts
⇒ Fully synthesizable with no internal tri-states ⇒ IP Core implementation support

Performance Data Configurations

The table below summarizes gate-level synthesized
performance data in TSMC 90 nm, for sample
combinational and pipelined designs. The IP core source
code is provided with generic parameters to enable
automatic pipelining with arbitrary number of pipeline
stages. More detailed performance data can be found in
the product technical documentation.
DecAdd64/128 can be combined with other
SilMinds IP core units to comprise arbitrary decimal
coprocessor architectures. Deployment is made
easy and reliable through a compact core size,
parameterized RTL, and flexible test benches.

Delay Area
Design Product Verification 
nS FO4 μm2 NAND2
This product has been verified using an innovative
DecAdd64-comb 2.03 45.1 38,405.1 13,608 and efficient constraint driven test vector
generation tool. The test vectors cover all valid
DecAdd64-pipe4 0.74 16.4 72,963.3 25,852
cases in conformance with the IEEE 754-2008
standard.
DecAdd128-comb 2.55 56.7 71,594.4 25,367
Symbol & Block Diagram

A Inputs
Result
B A, B Augend and addend Outputs
RM (2:0) OF RM Rounding Mode Result Resultant
Op Op Operation OF Overflow Flag
UF
Clk Clk System Clock UF Underflow Flag
INE
Rst Rst System Reset INEF INExact Flag
INV
En DecAdd64/128 En Enable INVF INValid Flag

A, B Augend, Addend
RM Rounding Mode
RM
SR
Injector

Exception SA, SB Significands A and B

A SV PS Handler
EA, EB Exponents A and B
RR SV Special Values
Formulation and Detection

SLRA Flags SWA, SWB Swapped A,B

Output Formulation
SA
Shifter
Master Control

Placer

SWA SLRA Shift Left/Right Amount

SB RS PS Predicted Sign
Decimal Adder Core

IE Intermediate Exponent
Generator
Sticky bit

Result Sb Sticky Bit

EA SWB
RR Rounded Result
Sb
EB SC
B RE Rounded Exponent
RM RE RS Result Sign
Op IE
SR Special Result

Adder Unit Functions

Formulation & Detection Sticky-bit Generator Decimal Adder Core

▪ Decodes input operands Determines the Sticky bit that Performs decimal fixed point
(Augend and Addend) using results from logically ORing the bits addition and subtraction; addition
IEEE 754-2008 format to of the digits to the right of the occurs in parallel at digit level;
produce the sign bit, significand, round digit carry signals are propagated
and exponent through a flagged Kogge-Stone
Shifter prefix tree)
▪ Performs special input detection
Aligns the operands to reach the
preferred exponent Exception Handler
Master Control
Handles the exceptions and passes
▪ Determines if operand swapping Injector the special results to the output
is needed Performs insertion of special digits formulation unit
▪ Computes shift amounts for both into the smallest operand, before
operands addition, to get the appropriate Output Formulation
▪ Computes how many sticky rounded result ▪ Encodes the resultant significand
counter digits will be collected in in DPD format
Placer
the sticky bit ▪ Formulates the special values
Performs operands placement
▪ Encodes special values and
depending on the effective
(infinity or NaN) to comply with
passes them to the output the IEEE 754-2008 standard
operation (subtraction or addition)
formulation ▪ Sets the appropriate flags

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