1.7.

TIME - DIVISION MULTIPLEXING

As it was shown in paragraph 1.3, another method of multiplexing the signals of baseband
channels to transmit them over a wideband transmission path is the time - domain multiplexing
(TDM). Whereas FDM transmission makes a portion of the total bandwidth available to each
channel for all the time, TDM transmission uses the whole bandwidth for each channel but for
only part of the time.
Analogue speech signals are converted to digital signals by using pulse - code modulation
(PCM), as it was described in par. 1.3, and multiplexed onto a common bearer by using TDM. In
this way, telephone channels are combined to form an assembly of 24 or 30 channels. This is
known as primary multiplex group. The primary multiplex group is also used as a building
block for assembling larger numbers of channels in higher - order multiplex systems.
The block diagram of typical PCM primary multiplex equipment is shown in Figure 1.22.

The digit stream on the transmission path is arranged in frames of 125 µ s duration (i.e. the
interval corresponding to 8 kHz sampling). Each frame contains one coded speech sample from
each channel, together with digits for signalling and synchronization. Two frame structures are
widely used: the European 30 - channel system and the 24 - channel system (known as DS 1)
used in North - America and Japan. Both use 8 kHz sampling and 8 - bit samples. However, the
30 - channel system uses A - law companding and the 24 - channel system uses µ - law
companding.
The 30 - channel frame is shown in Figure 1.23. It is divided into 32 time slots each of eight
digits, so the total digit rate is 8∗ 8∗ 32 kbits/s = 2,048 Mb/s.
Time slot 0 is allotted to the frame - alignment word. Time slots 1 - 15 and 17 - 31 are each
allotted to a speech channel. Time slot 16 is allotted to signalling. For channel - associated
signalling this may be shared between the speech channels by a process of multiframing. In one
frame in every 16, each channel is allocated four bits in channel 16. This gives it four signalling
channels at 500 bits/s in each direction. Alternatively, the whole of time slot 16 may be used to
provide a 64 kb/s data link for common - channel signalling.
Higher - order digital multiplexing
The primary multiplex group of 30 or 24 channels is used as a building block for larger numbers
of channels in higher - order multiplex systems. At each level in the hierarchy, several bit
streams, known as tributaries, are combined by a multiplexer/demultiplexer, known as muldex
(or mux). The output from a multiplexer may serve as a tributary to a multiplexer at the next -
higher level in the hierarchy, or it may be sent directly over a line or radiolink.

If the inputs to a multiplexer are synchronous, i.e. they have the same bit rate and are in phase,
taking a bit or a group of bits from each in turn can interleave them. A switch that samples each
input under the control of the multiplex clock can do this. There are two main methods (as shown
in Figure 1.24) of interleaving digital signals: bit interleaving and word interleaving or byte
interleaving.
In bit interleaving, one bit is taken from each tributary in turn. If there are N input signals, each
with a rate of f1bit/s, then the combined rate will be Nf1 bit/s and each element of the combined
signal will have duration equal to 1/N of an input digit. In word interleaving groups of bits are
taken from each tributary in turn and this involves the use of storage at each input to hold the bits
waiting to be sampled.
Bit interleaving is simpler and was chosen for the first-generation hierarchy of higher-order
multiplexers, known as plesiochronous digital hierarchy (PDH).
- The plesiochronous digital hierarchy -
In a transmission network, which has not been designed for synchronous operation, the
tributaries entering a digital multiplex, will not generally be exactly synchronous. Although they
have the same nominal bit rate, they commonly originate from different crystal oscillators and
can vary within the clock tolerance. They are said to be plesiochronous. The first-generation of
higher-order digital multiplex systems was designed for this situation. It forms the
plesiochronous digital hierarchy (PDH).
There are three incompatible sets of standards for plesiochronous digital multiplexing, centred on
Europe, North America and Japan. These systems all use bit interleaving. The frame length is the
same as for primary multiplex, i.e. 125 µ s, since this is determined by the basic channel-
sampling rate of 8 kHz. However, as shown in Figure 1.25 and 1.26, when N tributaries are
combined, the digit rate of the higher-order frame is more than N times the digit rate of the
tributary frames. This is because it is necessary to add extra "overhead" digits for two reasons.
The first reason is frame alignment. A higher-order demultiplexer must recognize the start of
each frame in order to route subsequent received digits to the correct outgoing tributaries, just as
a primary demultiplexer must route received digits to the correct outgoing channels. The same
technique is employed. A unique code is sent as a frame alignment word (FAW), which is
recognised by the demultiplexer and used to maintain its operation in synchronism with the
incoming signal. The European hierarchy uses a bunched FAW at the start of each frame, but the
other hierarchies use distributed FAWs.
The second reason for adding extradigits to the frame is to perform the process known as
justification. This process is to enable the multiplexer and demultiplexer to maintain correct
operation, although the input signals of the tributaries entering the multiplexer may drift relative
to each other. In positive justification the transmitted digit rate per tributary is slightly higher
than the nominal input rate. If an input tributary is slower, a dummy (fictive), i.e. a justification
digit, is added to maintain the correct output digit rate. If the input tributary speeds up, no
justification digit is added. The demultiplexer must remove the justification digits, in order to
send the correct sequence of signal digits to the output tributary. Consequently, further additional
digits, called justification service digits, must be added to the frame for the multiplexer to signal
to the demultiplexer whether a justification digit has been used for each tributary. In negative
justification, instead of dummy digits being inserted when the digit rate of a tributary is too slow,
a data digit is occasionally removed when a tributary is too fast and is transmitted in a spare time
slot. Another option is to use both positive / zero / negative justification. The European PDH
uses only positive justification.
When bit interleaving is used, bits for a particular channel occur in different bytes of a higher-
order frame. To separate one channel from the aggregate bit stream, a total demultiplexing
process is required. This results in the "multiplexing mountain" shown in Figure 1.27.
The new synchronous digital hierarchy (SDH) employs byte interleaving. This enables drop and
insert or add / drop muldexes to insert or to remove lower order assemblies, down to a primary
group, with relative ease.
The synchronous digital hierarchy
Networks are becoming fully digital, operating synchronously, using high-capacity optical-fibre
transmission systems and time-division switching. It is advantageous for the multiplexers used in
these networks to be compatible with the switches used at the network nodes, i.e. they should be
synchronous rather plesiochronous.
In 1990 CCITT defined a new multiplex hierarchy, known as synchronous digital hierarchy
(SDH). In USA this is called the synchronous optical network (SONET), since the muldexes use
optical interfaces.
The SDH uses a digit rate of 155.52 Mb/s and multiples of this by factors of 4n, e.g. 622.08 Mb/s
and 2488.32 Mb/s. Any of the existing CCITT plesiochronous rates can be multiplexed into the
SDH common transport rate of 155.52 Mb/s. The SDH also includes management channels,
which have a standard for network-management messages.
The basic SDH signal, called the synchronous transport module at level 1 (STM-1) is shown
in Figure 1.28a.
This has nine equal segments, with nine "overhead" bytes at the start of each. The remaining
bytes (261) contain a mixture of traffic and overheads, depending on the type of traffic carried.
The total length is (9+ 261)*9 = 2430 bytes, thus the overall bit rate is 2430∗ 8 bits/125 µ s =
155,520 kb/s, which is usually called "155 Mb/s".
This frame is usually represented as nine rows and 270 columns of 8 - bit bytes, as shown in
Figure 1.28.b. The first nine columns are for section overheads, such as frame alignment, error
monitoring and data. The remaining 261 columns comprise the payload, into which a variety of
signals can be mapped.
Each tributary to the multiplex has its payload area, known as tributary unit (TU). In North
America, a TU is called a virtual tributary (VT). Each column contain nine bytes (one from
each row), with each byte having 64 kb/s capacity. Three columns (i.e. 27 bytes) can hold a 1.5
Mb/s PCM signal, with 24 channels and some overheads. Four columns (i.e. 36 bytes) can hold a
2 Mb/s PCM signal with 32 time slots. The STM-1 frame can also hold payloads at the European
rates of 8, 34 and 140 Mb/s and the North America rates of 6, 45 and 140 Mb/s.
Because the SDH provides interfaces for network - management messages in a standard format,
it can lead to a managed transmission - bearer network in which transport capacity can be
allocated flexibly to various services. The network can be reconfigured under software control
from remote terminals.