LPF2

34.
Two-Pole Low Pass Filter
Two-Pole Low Pass Filter Data Sheet

LPF2
Copyright © 2002-2009 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks API Memory (Bytes) Pins (per

Resources Digital Analog CT Analog SC Flash ±3% RAM External I/O)
CY8C29/27/26/25/24xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED03D/04D, CY8CNP102, CY8CTST120,
CY8CTMG120, CY8CTMA120, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52
0 0 2 120 0 1
For one or more fully configured, functional example projects that use this User Module go to
www.cypress.com/psocexampleprojects.
Features and Overview

• User-programmable gain
• User-programmable corner frequency and damping ratio with no external components
• Filter corner-frequency stability directly derived from clock accuracy
• Filter sampling rates to 1.0 MHz
The LPF2 User Module implements a general-purpose second order state variable, also called a biquad,
low pass filter. The corner frequency and damping ratio are functions of the clock frequency and the ratios
of the capacitor values chosen. Any of the classical all-pole filter configurations (Butterworth, Bessel, and
Chebyshev) can be implemented. The corner frequency can be set very accurately or adjusted by
controlling the sample rate clock. Fourth order and higher order functions can be implemented by
cascading two or more LPF2 User Modules.
C2 φ1 φ2
C4
CA
CB
Vin φ2 C1 φ2
φ1 C3 φ2
φ2 Vout
φ1 φ1
φ2 φ1
LPF2 Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-13572 Rev. *D Revised June 15, 2009
Functional Description
In the frequency domain, a two-pole low pass filter has the frequency response,
2
V OUT G ( ωn ω0 )
------------- = ---------------------------------------------------------
-. Equation 1
V IN 2
s + sω n ω 0 d + ( ω n ω 0 )
2
In the equation above, d is the damping ratio, ω0 is the natural frequency, and ωn is the normalized -3 dB
frequency. All two-pole filters have out-of-band attenuation asymptotic to 12 dB per octave (-6 dB per
octave per pole). In-band performance is determined by damping ratio and natural frequency. The
standard Butterworth filter has monotonic amplitude performance and maximally flat phase shift in the
pass band. Filters with low damping ratios (Chebyshev) have flatter in-band amplitude characteristics, but
non-linear phase shift in the pass band and pulse response characterized by ringing. Filters with high
damping ratios (Bessel) have linear phase shift in the pass band and pulse response characteristics with
minimum over-shoot, but reduced near out-of-band attenuation. Values for d and ω0 are readily available
in any filter design reference. All of these filter forms can be realized by adjusting the ratios of capacitors in
the switched capacitor PSoC blocks.
The basic form of the biquad filter is a pair of integrators with controlled DC and frequency-dependent
feedback paths. The biquad can be understood by examining the standard RC form, shown in the
following figure.
R2
C4
CA CB
1 R3
Vin R
1
1 Vout
RC-Biquad Block Diagram
The typical RC-biquad low pass uses 3 opamps. The transfer function of the RC biquad is as follows.
R2 1
– ------ ---------------------------
V OUT R1 R2 R3 CA CB
------------- = -------------------------------------------------------------------- Equation 2
V IN 2 C4 1
s + s -------------------- + ---------------------------
R3 CA CB R2 R3 CA CB
In the PSoC switched capacitor implementation, the center inverting opamp is eliminated by reversing the
polarity of the gain of the output block. Resistors are transformed into the switched capacitors, as seen by
comparing the schematics of the RC biquad and the switched capacitor implementation.
Because of the nature of switched capacitor circuits as time-sampled devices, the transfer function is
developed in the time domain, where z-1 is the time delay of one sample period, rather than the frequency
Document Number: 001-13572 Rev. *D Page 2 of 20

domain (s=jω). The transfer function is converted to the frequency domain using the bi-linear transform.
The transfer function resolves to the following.
 1 –  ------ s - 2 2
f
C1   2f s  s
– ------ ---------------------------------------------
C 2  C A C B 1 1 C 4
-------------- – --- – --- ------
V OUT  C 2 C 3 4 2 C 2
------------- = -------------------------------------------------------------------------------------------------------------------- Equation 3
V IN 2
2 C4 sf s fs
s + ------ --------------------------------------------- + ---------------------------------------------
C 2  C A C B 1 1 C 4  C A C B 1 1 C 4
-------------- --- --- ------ -------------- --- --- ------
 C 2 C 3 – 4 – 2 C 2  C 2 C 3 – 4 – 2 C 2
Evaluating this equation with the standard form of Equation 1 yields a set of design equations for gain, G,
corner frequency ωn ω0 and damping ratio, d.
C1
G = – ------ Equation 4
C2
1---
fs ( C2 C3 ) 2
ω n ω 0 = ------------------------------------------------------------1- Equation 5
C C – C 2 C 3 C 4 C 3 --2-
------------
- – -------------
 A B 4 2 
1---
C3
C 4  ------ 2
C2
d = ------------------------------------------------------------1- Equation 6
C C – C 2 C 3 C 4 C 3 2
---
------------- – ------------
-
 A B 4 2 
2
The numerator of Equation 3 has the term 1 – ( s ⁄ ( 2f s ) ) , which results in reduced filter attenuation as the
signal frequency approaches half of the Nyquist rate (i.e., the sampling rate fS). Higher sample rates result
in filter performance closer to the standard form of Equation 1 and smoother waveforms.
Filter Design
The design objective is usually to achieve the highest possible sample rate (fclk), for the best waveform
fidelity and minimum aliasing of out-of-band signals. Other system requirements (e.g., shared clocks) may
determine sample rates; capacitor values may be tailored to achieve the required sample rate.
The LPF2 provides 3 alternatives for determining the capacitor values. PSoC designer provides a filter
design wizard to automate the procedure for two-pole filters. This same procedure is implemented in the
spreadsheet, LPF2 Design.xls, which may be obtained from the “Documentation...” entry in PSoC
Designer’s Help menu. A similar design procedure for two pole pair (fourth order) filters is automated in a
separate Microsoft Excel spreadsheet, LPF4 Design.xls. Design constraints enforced by the wizard may
be modified experimentally in the spreadsheets. For the ultimate in hands-on control over the design
process, see the appendix at the end of this document for a numerical procedure that may be carried out

manually. It also provides an example showing how the procedure works for a Butterworth filter with a 1
kHz corner frequency.
To use the PSoC Designer’s built-in Filter Design Wizard, first place an LPF2 instance in the analog array.
Right click on the user module and choose “Filter Design Wizard...” from the pop up menu. The resulting
dialog, shown below, describes a simple iterative procedure for designing the transfer function.
LPF2 Filter Design Wizard Dialog Box
Scrolling down in the dialog reveals the table of values used to plot the magnitude response. Values from
this table may be cut and pasted into spreadsheets or other tools for further graphing and analysis.

DC and AC Electrical Characteristics

The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified, all limits guaranteed for TJ =+25°C, Vdd = 5.0V, Power HIGH, Opamp bias
LOW, output referenced to Analog Ground = 2*VBandGap.
5.0V LPF2 DC Electrical Characteristics
Parameter Typical Limit Units Conditions and Notes

DC Offset Voltage1 18 -- mV Reference to Analog Ground
DC Gain Error2 1.55 -- %
Operating Current
Low Power 290 -- µA
Medium Power 1065 -- µA
High Power 4015 -- µA
5.0V LPF2 AC Electrical Characteristics

Maximum Clock Frequency3
Low Power -- 2 MHz
Medium Power -- 4 MHz
High Power -- 8 MHz
Corner Frequency Error 2.3 -- % Deviation from Nominal2
Damping Ratio Error 1.85 -- %
Noise4 2140 -- nV/√Hz
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the following tables, limits guaranteed for TA = 25°C, Vdd = 3.3 V, Power
HIGH, Opamp bias LOW, output referenced to Analog Ground = Vdd/2.

DC Offset Voltage1 14 -- mV Reference to Analog Ground
DC Gain Error2 1.65 -- %
Operating Current
High Power 3275 -- µA

3.3V LPF2 AC Electrical Characteristics,

Maximum Clock Frequency3
Low Power -- 2 MHz
Medium Power -- 4 MHz
High Power -- 8 MHz
Corner Frequency Error 2.15 -- % Deviation from Nominal2
Damping Ratio Error 1.9 -- %
Noise4 1880 -- nV/√Hz
Electrical Characteristics Notes

1. Typical DC offset found using 1 kHz filter with Q’s of 3, 5 and 15; C2=1 thru 16; C3=3, 10 and 25. C1 and C4
found using filter design spreadsheet.
2. Deviation values determined from nominal filter: fcenter=1 kHz Butterworth, unity gain, C1=1, C2=3, C3=31, C4=1,
fclock=20.3 kHz, Q=10.
3. Sample rate is one fourth of column clock frequency.
4. Noise found at 1 kHz using a 10 kHz filter.
Unless otherwise specified, all limits guaranteed for TJ = -40°C to, +85°C, Vdd = 5.0V ±10%, Power
HIGH, Opamp bias LOW, output referenced to Analog Ground = 2*VBandGap.
Parameter Typical1 Limit2 Units Conditions1 and Notes

Offset Voltage5 42 mV see graph
DC Gain Error 1.55 % Ref Design = 1.0 kHz
Butterworth3
Operating Current
High Power 1560 2000 µA
Parameter Typical1 Limit2 Units Conditions and Notes

Corner Frequency Deviation -- 2.5 % Deviation from Nominal
Damping Ratio Deviation -- 2.6 % Deviation from Nominal
Noise -- 8.0 mV rms
Clock Frequency
Low Power -- 2.0 MHz
Medium Power -- 4.0 MHz
High Power -- 8.0 MHz

Unless otherwise specified in the following tables, limits guaranteed for TA = -40°C to +85°C, Vdd = 3.0 to
3.6 V, Power HIGH, Opamp bias LOW, output referenced to Analog Ground = Vdd/2.

Offset Voltage5 42 mV see graph
DC Gain Error 1.65 % Ref Design = 1.0 kHz
Butterworth3
Operating Current
High Power 1280 1800 µA

Corner Frequency Deviation3 -- 2.5 %
Damping Ratio Deviation3 -- 2.6 %
Noise -- 6.0 mV rms
Clock Frequency4
Low Power -- 1.0 MHz
Medium Power -- 2.0 MHz
High Power -- 4.0 MHz
Electrical Characteristics Notes

1. Typical values represent parametric norm at +25°C.
2. Limits are guaranteed by testing or statistical analysis.
3. Reference design C1=1, C2=1, C3=2, C4=31, CA=32, CB=32, f(sample)=139.2 kHz, damping ratio = 1.392.
4. Clock frequency is for filter of Note 3, with corner frequency scaled with clock.
5. 1kHz filter, fclk=35 kHz, horizontal inverting topology, C1=C2=8, C3=16, C4=31, CA=CB=32.
Performance Notes
Errors in gain and phase for the filter are only significant near the corner frequency. Other selections can
be made for filter capacitor values. C2 and C3 ratios can be adjusted to allow better resolution in the
damping ratio. Setting CA or CB equal to 16 allows for additional resolution in the damping ratio setting,
but at the cost of reducing sample rate from the maximum possible value.
The gains in signal fidelity, as a result of increased sample rate, may out-weigh transfer function error as a
result of non-ideal pole location. Lowering the sampling rate (by increasing C1 and C2) has the effect of
reducing the attenuation approaching the Nyquist rate.

20
Peak, Peak, OSR=70
Peak, OSR=10 OSR=35
Peak, OSR=140
0
Net, OSR=10
-20
dB
Net, OSR=35
-40
Net, OSR=70
-60
Net, OSR=140
Nom inal
-80
100 1000 10000 Freq (Hz) 100000 1000000
Filter Performance versus Over-Sampling Ratio
Filter performance deviates by some degree from the standard form as a result of the effects of op-amp
open loop gain, absolute capacitor value and filter placement. While low pass filters above 100 kHz are
mathematically possible, op-amp performance limitations make these choices unstable. Filters with corner
frequencies above 40 kHz should have user module power set to “HIGHPOWER” and Op-Amp Bias set to
“High” in the Global Parameters window. For a given filter characteristic there may be a number of
capacitor value solutions which will meet the requirement, but each variation will have a different sample
rate. In general, increasing the capacitor values decreases the oversampling ratio (i.e., ratio of sample
rate to nominal -3dB frequency). For the highest oversample ratio, and smoothest output waveform, the
filter should be built starting with the lowest possible value of C2 in either the design spreadsheet, design
wizard or "by hand" derivation using the design equations. For example, a Butterworth filter with C2=1 and
C4=31 has an oversample ratio of 140. Setting C2=2 results in oversample ratio of 70. In all cases, the
selected sample rate must be less than the maximum of 1.00 MHz (column clock = 4.0 MHz); higher
frequency filters will require lower oversample ratios to meet this requirement. The numerator of
Equation 3 shows a pair of complex zeros at 2fs. As the sample frequency is reduced, the effect of these
zeros becomes ever stronger, peaking the upper band edge as shown in the following figure.
Charge injection in the internal switch topology limits DC performance of the filter. This effect has a
random component and a placement determined component. Filters placed in horizontal block pairs have
lower DC offset than filters placed in vertical block pairs. Scaling the filter by increasing the value of C2
(and C1 and C3), results in reduced DC offset error. Typical values are shown below.

1
Volts Offset
Hor izont al, Inver t

Hor izont al, Non-Invert
Vert ical, Inver t
0.1
0.01
1 10 100
C2 Value
Typical Offset Dependence on C2 Value
Ver t ical, Invert

Volts Offset
Horizont al, Invert

Horizont al, Non- Inver t
0.1
0.01
1 10 C2 Value 100
Typical Offset Dependence on C2 Value
Placement
The Device Editor maps the logical FLIN and FLOUT blocks onto a pair of adjacent switched capacitor
PSoC blocks in the device’s analog array. There are several ways to construct the biquad filter circuit out
of the analog PSoC blocks. Each construction implements the LPF2 Schematic Diagram illustrated above,
but uses different capacitors and connections within the FLIN and FLOUT blocks. Each results in a
different circuit topology with different mapping and I/O consequences. The most noticeable difference is
whether the two PSoC blocks lie in a row or column of the analog array. The topologies also determine
which connections can be made to other blocks in the array. Regardless of the topology selected,
however, the filter inputs always connect to the FLIN block and outputs are driven by the FLOUT block.
Each time an instance of the LPF2 User Module is created, PSoC Designer presents a dialog with
illustrations and text to assist in selecting a circuit topology. The choice may be altered at any time by

right-clicking on the user module icon in the selection bar or, if already placed, right-clicking on one of its
PSoC blocks and choosing “Select User Module Options...” from the pop-up menu. Changing the topology
after placement requires that the user module be placed in the analog array again.
Parameters and Resources

To make a low pass filter, place an instance of the LPF2 User Module in the Device Editor's analog array.
Use one of the design procedure options to determine the values for the filter’s capacitors, then connect
the inputs and configure the analog bus connection and clock resources. Each of these parameters are
discussed below.
Input
Inputs to the filter are driven by the outputs of the adjacent PSoC blocks. Input selections are made by the
user in the Device Editor.
AnalogBus
The output of the user module's FLOUT block can be connected to adjacent PSoC blocks. Connection to
this output, from other user modules is made in the Device Editor. The output of the FLOUT block can be
connected to the analog column output bus using the AnalogOutBus_x selection (where "x" is the column
number). This enables connection to the Analog Output Buffer for the same column and prevents analog
output-bus access of other user modules in the same column. All interconnections are configured using
the Device Editor.
CompBus
The FLOUT block comparator output may be routed to the input bus of the digital PSoC blocks or to an
interrupt. The CompBus parameter must be set to Enabled to make any of these connections.
Capacitor Values C1, C2, C3, C4, CA and CB

The ratios of these six capacitor values determine the frequency and phase response of the filter. The
names refer to the capacitors drawn in the LPF2 Schematic Diagram, above. CA and CB may each take
values of 16 or 32 units of capacitance. C1 through C4 take values from 0 to 31 (though values greater
than zero are required for meaningful transfer functions). Design of the transfer function may be
accomplished using automated or manual procedures. To access the built-in design tool, right-click on the
placed filter and choose “Filter Design Wizard...” from the pop up menu. See the Filter Design section
above, for more information on design.
Polarity (A-Input Topology Filters Only)

This parameter determines the polarity of the output relative to the input. The output can be set to invert
the input signal by selecting Inverting or to maintain the same polarity by selecting Non-inverting. This
parameter applies to the A-input topology filters only.
Sample Clock
The required Sample Clock for the low pass filter is calculated using the design equations in the
Functional Description section. Unlike the other user module parameters listed above, the sample clock
does not appear in the list of user module parameters underneath the Device Editor’s list of Global
Resources. Unlike signal inputs that are specific to a particular user module, the sample clocks each serve
an entire analog column. The sample rate clocks for both PSoC blocks must be the same and where
horizontal placement of blocks is selected, both column clocks must be driven from the same source.

Each column-clock generator divides its input by four to produce φ1 and φ2, the internal clocks in the
blocks, so the source must be four times faster than the desired filter sample clock.
Choices for the clock source include any of the digital PSoC blocks and the system clock dividers. All of
the Timer, Counter and Pulse-Width Modulator (PWM) User Modules are suitable choices when system
clock dividers must be consigned to other uses.
The clock source to the column clock is selected using the CLK mutiplexer, for each column in the Device
Editor. The system clocks are direct inputs to this multiplexer. When PSoC blocks are used for clock
generation, they are connected through the ACLK0 and ACLK1 multiplexers to the CLK multiplexer.
Application Programming Interface

The Application Programming Interface (API) routines are provided as part of the user module to allow the
designer to deal with the module at a higher level. This section specifies the interface to each function
together with related constants provided by the “include” files.
Note In this, as in all user module APIs, the values of the A and X register may be altered by calling an
API function. It is the responsibility of the calling function to preserve the values of A and X prior to
the call if those values are required after the call. This “registers are volatile” policy was selected
for efficiency reasons and has been in force since version 1.0 of PSoC Designer. The C compiler
automatically takes care of this requirement. Assembly language programmers must ensure their
code observes the policy, too. Though some user module API function may leave A and X
unchanged, there is no guarantee they will do so in the future.
Entry points are provided to initialize the LPF2 User Module, change power settings, and disable the user
module.
LPF2_Start
Description:
Performs all required initialization for this user module and sets the power level for the switched capac-
itor PSoC blocks.
C Prototype:
void LPF2_Start(BYTE bPowerSetting)
Assembly:
mov A, bPowerSetting
call LPF2_Start
Parameters:
bPowerSetting: One byte that specifies the power level to both analog PSoC blocks. Following reset
and configuration, the PSoC blocks assigned to the instrumentation amplifier are powered down. Sym-
bolic names provided in C and assembly, and their associated values, are given in the following table.
Symbolic Name Value

LPF2_OFF 0
LPF2_LOWPOWER 1
LPF2_MEDPOWER 2
LPF2_HIGHPOWER 3
Note For proper performance, filters with corner frequencies above 40 kHz should (1) use
LPF2_HIGHPOWER and (2) set the global parameter “Op-Amp Bias” to High in the Global Param-
eters window.

Return Value:
None
Side Effects:
The A and X registers may be altered by this function.
LPF2_SetPower
Description:
Sets the power level for the switched capacitor PSoC blocks. May be used to turn the blocks in the
user module off and on.
C Prototype:
void LPF2_SetPower(BYTE bPowerSetting)
Assembly:
mov A, bPowerSetting
call LPF2_SetPower
Parameters:
bPowerSetting: Same as the bPowerSetting used for the Start entry point.
Return Value:
None
Side Effects:
LPF2_SetCA, SetCB
Description:
Sets the value of the feedback capacitors in the user module FLIN block (CA) and FLOUT block (CB).
This allows on-the-fly modification of the low pass filter transfer function.
C Prototype:
void LPF2_SetCA(BYTE FEEDBACK_CONSTANT)
void LPF2_SetCB(BYTE FEEDBACK_CONSTANT)
Assembly:
mov A, FEEDBACK_CONSTANT
call LPF2_SetCA ; or, call LPF2_SetCB
Parameters:
FEEDBACK_CONSTANT: One byte that specifies the size of the feedback capacitors CA or CB (see
the LPF2 Schematic Drawing). Symbolic names are provided in the C and assembly include files; their
associated values are given in the following table.
Symbolic Name Value

LPF2_FEEDBACK_16 0x00
LPF2_FEEDBACK_32 0x01
Return Values:
None
Side Effects:

LPF2_SetC1, SetC2, SetC3, and SetC4

Description:
Sets the value of specific capacitors in the user module. This allows adjustment of gain by modifying
C1, and alteration of filter transfer characteristics by adjusting the other values.
C Prototype:
void LPF2_SetC1(BYTE bCapValue)
Assembly:
mov A, bCapValue
call LPF2_SetC1 ; or, call LPF2_SetC2 (or SetC3 or SetC4)
Parameters:
CapValue: Integer value from 1 to 31 for C1, C2, C3 and C4 (see the LPF2 Schematic Drawing). Val-
ues outside this range will be truncated modulo 32.
Return Values:
None
Side Effects:
LPF2_SetPolarity (A-Input Topology Filters Only)

Description:
Sets the polarity of the output signal by selecting whether to invert or not to invert the input signal on
FLIN. This allows on-the-fly modification of the low pass filter output polarity. This function applies only
to A-input topology filters.
C Prototype:
void LPF2_SetPolarity(BYTE FEEDBACK_CONSTANT)
Assembly:
mov A, FEEDBACK_CONSTANT
call LPF2_SetPolarity
Parameters:
POLARITY_CONSTANT: One byte that specifies whether to invert or not to invert. Symbolic names
are provided in the C and assembly include files; their associated values are given in the following
table.
Symbolic Name Value

LPF2_POLARITY_INVERTING 0x00
LPF2_POLARITY_NON_INVERTING 0x01
Return Values:
None
Side Effects:
LPF2_Stop
Description:
Powers the user module off.

C Prototype:
void LPF2_Stop(void)
Assembly:
call LPF2_Stop
Parameters:
None
Return Value:
None
Side Effects:
Sample Firmware Source Code

In C, using the low pass filter is as simple as using the Start API to begin operation and calling the Stop
API when done.
#include "LPF2.h"
LPF2_Start(LPF2_HIGHPOWER);
... // (application processing)
LPF2_Stop();
It is possible to set and modify the filter transfer function on-the-fly. Assuming the analog column clock is
driven from a 24 MHz source with a divider of 304, the following code creates a filter with a center
frequency of 1000 Hz and a Q of 10, and then starts it. Note that this same code is used regardless of the
chosen topology or placement location in the analog PSoC block array.
LPF2_SetC1( 1 );
LPF2_SetC2( 10 );
LPF2_SetC3( 10 );
LPF2_SetC4( 3 );
LPF2_SetCA( LPF2_FEEDBACK_32 );
LPF2_SetCB( LPF2_FEEDBACK_32 );
LPF2_SetPolarity( LPF2_POLARITY_INVERTING );
LPF2_Start(LPF2_HIGHPOWER);
Equivalent assembly language code is as follows.

include "LPF2.inc"
mov A, 1
lcall LPF2_SetC1
mov A, 10
lcall LPF2_SetC2
mov A, 10
lcall LPF2_SetC3
mov A, 3
lcall LPF2_SetC4
mov A, LPF2_FEEDBACK_32
lcall LPF2_SetCA
mov A, LPF2_FEEDBACK_32
lcall LPF2_SetCB
mov A, LPF2_POLARITY_INVERTING
lcall LPF2_SetPolarity
mov A, LPF2_HIGHPOWER

lcall LPF2_Start
Note The design equations show that gain is proportional to the value of C1, but the corner frequency
and damping do not depend on it. Once the transfer function is chosen, the LPF2_SetC1 API func-
tion may be used to implement a programmable-gain control.
Configuration Registers
The topology and placement of the LPF2 User Module determines over half the bits in the configuration
registers for the analog switched capacitor PSoC blocks used. Of those, the ones that are independent of
placement location are indicated by fixed values in the register tables. Of the variable bitfields, most are
determined by selection of input and transfer function design. Definitions of the variable bitfields used in
the register definitions follow, at the end of this section.
Horizontal A-Input Topology
Block FLIN: Register CR0
Bit 7 6 5 4 3 2 1 0
CR0 CA 0 Polarity C1
CR1 Input C2
CR2 0 0 0 0 0 0 0 0
CR3 0 0 1 0 Feedback Power
Block FLOUT: Register CR0
Bit 7 6 5 4 3 2 1 0
CR0 CB 0 0 C3
CR1 FBIN 0 0 0 0 0
CR2 AnalogBus CompBus 0 C4
CR3 0 0 1 0 0 1 Power
Horizontal B-Input Topology
Block FLIN
Bit 7 6 5 4 3 2 1 0
CR0 CA 0 1 C2
CR1 Feedback C1
CR2 0 0 0 0 0 0 0 0
CR3 0 0 1 0 Input Power

Block FLOUT
Bit 7 6 5 4 3 2 1 0
CR0 CB 0 0 C3
CR1 FBIN 0 0 0 0 1
CR2 AnalogBus CompBus 0 C4
CR3 0 0 1 0 0 1 Power
Vertical A-Input Topology
Block FLIN
Bit 7 6 5 4 3 2 1 0
CR0 CA 0 Polarity C1
CR1 Input C2
CR2 0 0 0 C4
CR3 0 0 1 0 Feedback Power
Block FLOUT
Bit 7 6 5 4 3 2 1 0
CR0 CB 0 0 C3
CR1 FBIN 0 0 0 0 1
CR2 AnalogBus CompBus 0 0 0 0 0 0
CR3 0 0 1 0 0 1 Power
Vertical B-Input Topology
Block FLIN
Bit 7 6 5 4 3 2 1 0
CR0 CA 0 1 C2
CR1 Feedback C1
CR2 0 0 0 C4
CR3 0 0 1 0 Input Power

Block FLOUT
Bit 7 6 5 4 3 2 1 0
CR0 CB 0 0 C3
CR1 FBIN 0 0 0 0 1
CR2 AnalogBus CompBus 0 0 0 0 0 0
CR3 0 0 1 0 0 1 Power
Variable BitField Definitions

The following definitions apply to all preceding register definitions.
CA and CB set the FLIN and FLOUT feedback capacitors, respectively, to either 16 or 32 units. (See the
LPF2 Schematic Diagram.) CA and CB are configured directly in the Device Editor or indirectly through
use of the filter Design Wizard.
C1, C2, C3 and C4 set the capacitors illustrated in the LPF2 Schematic Diagram to integer values
between 1 and 32. Like the CA and CB capacitors, they are configured directly in the Device Editor or
indirectly through use of the filter Design Wizard.
Input controls the multiplexor that selects the input signal to be conditioned by the LPF2 User Module.The
user module “Input” parameter determines the value of this bitfield. The value of the Input parameter is
manually configured using the Device Editor. In certain cases, the values which this bitfield can take are
restricted in such a way that the C4 connection between the FLIN and FLOUT blocks is properly
guaranteed.
AnalogBus enables connection of the filter output to the analog bus. The user module “AnalogBus”
parameter determines the value of this bitfield. The value of the AnalogBus parameter is manually
configured using the Device Editor.
CompBus enables connection of the filter output to the comparator bus. The user module “CompBus”
parameter determines the value of this bitfield. The value of the CompBus parameter is manually
configured using the Device Editor.
Feedback is the C2 feedback connection, automatically determined by placement of the LPF2 User
Module in the Device Editor. In certain cases, this bitfield also establishes the C4 connection between the
FLIN and FLOUT blocks.
FBIN is the connection from the FLIN output to the FLOUT input, automatically determined by placement
of the LPF2 User Module in the Device Editor.
Polarity controls whether the output of the filter is inverted or not. This bit can be configured directly using
Device Editor. This option is available only to A-input topology filters.
Power controls the On/Off state of the PSoC block and bias current setting. It is set initially by calling the
user module API function LPF2_Start and can be modified by calling the functions LPF2_SetPower and
LPF2_Stop.

Appendix: Numerical Filter Design for the LPF2

This appendix details the design procedures implemented in the design wizard and and spreadsheets.
The required values can be calculated easily (but roughly). For a first order approximation, the design
equations are simplified to the following.
C1
G = – ------ Equation 7
C2
C2 C3
ω n ω 0 = f clk ------------------ Equation 8
CA CB
C4 C
d = ------------------ -----3- Equation 9
CA CB C2
These show the first order interaction of the ratios of the capacitors somewhat more clearly.
The clock frequency, fclk, is calculated by rearranging Equation 8.
CA CB
f clk = ω n ω 0 ------------------ Equation 10
C2 C3
Two-Pole Design Procedure

The objective of the design procedure is to yield the highest possible fclk, for the best fidelity and least
aliasing.
1. Set CA and CB to 32.
2. Set C2 to the minimum integer value, 1.
3. Set the initial value of C4 to the maximum value, 31.
2 CA CB
4. Find the smallest value for C3 such that C 3 ≥ d C 2 ------------------ .
C 4
5. Revise C4 from C 4 = d C A C B C 2 ⁄ C 3 and round to the nearest integer.

6. Using the required gain, calculate a value for C1 from Gain: Equation 4.
7. Calculate fclk from Equation 10.
8. Set analog column clocks to four times fclk. Pick an analog column clock resource, fsysclk, from the
selections available in PSoC Designer. See the Sample Clock section in this data sheet, for additional
details on clock selection.
f sysclk
9. Calculate the divider by rounding to the nearest integer as follows. n = int  ------------- + 0.5
 4f clk 
10. Divide the selected system clock resource by 4n, to get the actual clock frequency.
11. Calculate the damping ratio, d, and the natural frequency, ω0, from Equation 6 and Equation 5. Com-
pare the results to the desired values. This provides an adequate starting point for the filter design. d
and ω0 will both be in error by -2 to -10% from the required values.

12. Adjust the values of C2, C3 and C4 to achieve the required values of d and ω0 using Equation 5 and
Equation 6. In general, start by reducing C4 to meet the d requirement.
13. Recalculate system clock frequency to meet ω0 requirements with updated capacitor values.
The procedure above yields approximate values for the capacitors in the LPF2. More exact calculations,
with close adherence to design equations 4, 5 and 6, are executed in the development spreadsheets LPF2
Design for two-pole filters and LPF4 Design for four-pole filters. These spreadsheets are available in the
PSoC Designer documentation directory. LPF2 design is implemented in a filter wizard accessible by right-
clicking on the user module in the Device Editor. After filter optimization, the capacitor values and clock
frequency divisor coefficients can be entered in the PSoC Designer User Module Parameter window.
Two-Pole Example
For this design example, f-3dB is set to 1.0 kHz. For the Butterworth filter, the normalized corner frequency,
ω0, is 1.0 and the damping ratio, d, is 1.414. The filter will be designed for the maximum over-sample ratio.
The design procedure will be followed by the numbers.
1. CA, CB = 32.
2. C2 = 1.
3. C4 = 31.
4. Calculate C3 very close to 2.
5. No change to C4.
6. C1 = 1.
CA CB 3 32 ⋅ 32
7. f clk = ω n ω 0 ------------------ = 2π10 ⋅ 1 ⋅ -------------------- = 142.17 kHz
C2 C3 2
8. Analog Column Clock = 568.69 kHz.
9. n = 42 from 24V1, 24V2 clock or Timer, or Counter PSoC block.
10. fclk = 142.857 kHz.
1---
C3 2
C 4  ------
 C 2 31 2
d = -------------------------------------------------------------1- = ----------------------------------------------------1- = 1.392
--- ---
C C + C 2 C 3 C 4 C 3 ⋅2 2
2
------------
- + -------------  32 ⋅ 32 – 2--- – 31
-------------
 A B 4 2   4 2 
1
---
fs ( C2 C3 ) 2 142.857 kHz 2
ω n ω 0 = ------------------------------------------------------------1- = ----------------------------------------------------1-
C C – C 2 C 3 C 4 C 3 --2-
------------
- – ------------
-  32 ⋅ 32 – 2--- – 31 ⋅ 2- --2-
------------
 A B 4 2   4 2 
f-3dB = 1.020 kHz and ω0 = 1.00 or

f-3dB = 1.000 kHz and ω0 = 1.02
11. For many applications, 1.6% error in damping ratio and 2% error in corner frequency are adequate.
12. This performance can be improved. f-3dB can be adjusted closer to the desired value by using the 48
MHz input to a Timer or Counter User Module set to divide by 85, rather than setting the system clock
dividers to divide 24 MHz by 42. This yields f-3dB equal to 1.008 kHz.

Document Number: 001-13572 Rev. *D Revised June 15, 2009 Page 20 of 20

© Cypress Semiconductor Corporation, 2002-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
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34.

Two-Pole Low Pass Filter

Two-Pole Low Pass Filter Data Sheet

PSoC® Blocks API Memory (Bytes) Pins (per

Features and Overview

LPF2 Block Diagram

RC-Biquad Block Diagram

Document Number: 001-13572 Rev. *D Page 2 of 20

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LPF2 Filter Design Wizard Dialog Box

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DC and AC Electrical Characteristics

5.0V LPF2 DC Electrical Characteristics

Parameter Typical Limit Units Conditions and Notes

5.0V LPF2 AC Electrical Characteristics

Parameter Typical Limit Units Conditions and Notes

3.3V LPF2 DC Electrical Characteristics

Parameter Typical Limit Units Conditions and Notes

Document Number: 001-13572 Rev. *D Page 5 of 20

3.3V LPF2 AC Electrical Characteristics,

Parameter Typical Limit Units Conditions and Notes

Electrical Characteristics Notes

5.0V LPF2 DC Electrical Characteristics

Parameter Typical1 Limit2 Units Conditions1 and Notes

5.0V LPF2 AC Electrical Characteristics

Parameter Typical1 Limit2 Units Conditions and Notes

Document Number: 001-13572 Rev. *D Page 6 of 20

3.3V LPF2 DC Electrical Characteristics

Parameter Typical1 Limit2 Units Conditions and Notes

3.3V LPF2 AC Electrical Characteristics

Parameter Typical1 Limit2 Units Conditions and Notes

Electrical Characteristics Notes

Document Number: 001-13572 Rev. *D Page 7 of 20

Filter Performance versus Over-Sampling Ratio

Document Number: 001-13572 Rev. *D Page 8 of 20

Hor izont al, Inver t

Typical Offset Dependence on C2 Value

Ver t ical, Invert

Horizont al, Invert

Typical Offset Dependence on C2 Value

Document Number: 001-13572 Rev. *D Page 9 of 20

Parameters and Resources

Capacitor Values C1, C2, C3, C4, CA and CB

Polarity (A-Input Topology Filters Only)

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Application Programming Interface

Symbolic Name Value

Document Number: 001-13572 Rev. *D Page 11 of 20

Symbolic Name Value

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LPF2_SetC1, SetC2, SetC3, and SetC4

LPF2_SetPolarity (A-Input Topology Filters Only)

Symbolic Name Value

Document Number: 001-13572 Rev. *D Page 13 of 20

Sample Firmware Source Code

Equivalent assembly language code is as follows.

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Horizontal A-Input Topology

Block FLIN: Register CR0

Block FLOUT: Register CR0

Horizontal B-Input Topology

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Vertical A-Input Topology