CS258F 2002S

CS 258F

VLSI Physical Design Automation

Professor Jason Cong

Computer Science Department

VLSI Physical Design Automation

Objectives:

a Obtain a general understanding of IC designs.

a Understand the process of VLSI layout design
a Study the basic algorithms used in layout
design of VLSI circuits.
a Learn about the physical design automation
techniques used in the best-known academic
and commercial layout systems.
a Get know hot research topics and problems.

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Course Requirements

• Prerequisites
– CS 180 and CS 51A
– Consent of instructor
• Grading Policy
– 30% homeworks
– 30% midterm
– 40% class project and term paper

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Contact Information

aMy office hour: Tu 4-5pm

a E.mail: cong@cs.ucla.edu

a My office address: Boelter Hall, 4711

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Website for Lecture Notes

• http://cadlab.cs.ucla.edu/~cong/cs258f_handouts.html
• For class attendees only. Please don’t distribute.

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Chapter 1
Introduction to VLSI Design

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VLSI Design Cycle

Manual
System Chip
Specification Automation

a Large number of devices

a Optimization requirements for high performance
a Time-to-market competition
a Cost

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VLSI Design Cycle

a System Specification
a Functional Design
a Logic Design
a Circuit Design
a Physical Design
a Design verification
a Fabrication
a Packaging, Testing and Debugging

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VLSI Design Cycle

System Specification

Functional Design

X=(AB*CD)+(A+D)+(A(B+C))

Logic Design Y=(A(B+C))+AC+D+A(BC+D))

Circuit Design

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VLSI Design Cycle (cont.)

Physical Design

Fabrication

Packaging

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Physical Design
Physical design converts a circuit description
into a geometric description. This description is
used to manufacture a chip. The physical design
cycle consists of
1 Partitioning
2 Floorplanning and Placement
3 Routing
4 Compaction

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Physical Design Process

Design Steps:
Partition & Clustering
Floorplan & Placement
Pin Assignment a
clk clk
Global Routing
Detailed Routing clk
a

Methodology: a
Divide-and-Conquer

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Physical Design Cycle

Circuit
Physical Design
Design

cutline 1
(a) Partitioning

cutline 2

Floorplanning
(b) &
Placement

(c) Routing

(d) Compaction

Fabrication

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Complexities of Physical Design

a More than 10 million transistor
a Performance driven designs
a Time-to-Market

Design cycle

…...

High performance, high cost

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Moore’s Law and NTRS’97

• Moore’s Law
– The min. transistor feature size decreases by 0.7X every three
years (Electronics Magazine, Vol. 38, April 1965)
– True in the past 30 years!
• 1997 National Technology Roadmap for Semiconductors

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

Year 1997 1999 2001 2003 2006 2009
# transistors 11M 21M 40M 76M 200M 520M
On-Chip Clock (MHz) 750 1200 1400 1600 2000 2500
Area (mm 2) 300 340 385 430 520 620
Wiring Levels 6 6-7 7 7 7-8 8-9

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Productivity Gap
Logic Transistors/Chip (K)

Transistor/Staff-Month

10,000,000 100,000,000
1,000,000 10,000,000
100,000 58%/Yr. Complexity 1,000,000
growth rate
10,000 100,000
1,000 10,000
100 x x21%/Yr. 1,000
xx
xx
x
x Productivity growth rate
10 100
1 10
1998 2003

Chip Capacity and Designer Productivity

Source: NTRS’97
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Design Challenges in Nanometer Technologies

• Interconnect-limited designs
– Interconnect performance limitation
– Interconnect modeling complexity
– Interconnect reliability
– Impact of new interconnect materials
• High degree of on-chip integration
– Complexity and productivity
– Limitation of current design abstraction and hierarchy
– System on a chip
– Power barrier

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Design Styles
Complexity of
VLSI circuits

Performance Size Cost Market time

Different design styles

Full custom Standard Cell Gate Array FPGA

Cost ,Flexibility,Performance

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Full Custom Design Style

Pad Metal Via Metal 2

Data Path
I/O
PLA

ROM/RAM

Random logic
A/D Converter

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Standard Cell Design Style

Cell Feedthrough
VDD GND
Metal 1 Metal 2

D C C B

A C C

D C D B

C C C B

Cell A Cell B

Cell C Cell D
Feedthrough cell

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Gate Array Design Style

A
C
B

VDD Metal1 Metal2

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FPGA Design Style

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Field-Programmable Gate-Arrays
(FPGAs)

a Programmable logic
a Programmable interconnects
a Programmable inputs/outputs

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Comparisons of Design Styles

style
full-custom standard cell gate array FPGA
cell size variable fixed height * fixed fixed
cell type variable variable fixed programmable
cell placement variable in row fixed fixed
interconnections variable variable variable programmable

* uneven height cells are also used

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Comparisons of Design Styles

style

full-custom standard cell gate array FPGA

compact
Area compact moderate large
to moderate

Performance high moderate low

high
to moderate

Fabrication ALL ALL routing none

layers layers

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Packaging Styles
Packaging

Printed Circuit Board Multi-Chip Module Wafer Scale Integration

PCB MCM WSI

Area

Performance, cost

The increasing complexity and density of the semiconductor devices

are driving the development of more advanced VLSI packaging and
interconnection approaches.

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Printed Circuit Board Model

Package
Plated
through IC (a)

holes

(b)

a Large number of layers (150a

pitch)
a Larger area
a Low performance
a Low cost
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MCM Model

IC (a)

(b)
a Up to 36 layers ( 75a pitch)
a Moderate to small area
a Moderate to high performance
a High cost
a Heat dissipation problems
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Wafer Scale Integration

a Small number of layers (VLSI technology- 6a pitch)

a Smallest area
a Significant yield problems
a Very high performance
a Significant heat dissipation problems

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Comparisons of Packaging Styles

Figure of Merit
Technology
(inches/psec. density inches/sq in)
WSI 28.0
MCM 14.6
PCB 2.2

a Merit = propagation speed (inches/ psec.) * interconnection

density (inches/sq. in).
a Interconnect resistance was not considered

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History of VLSI Layout Tools

Year Design Tools
1950 - 1965 Manual Design

1965 - 1975 Layout editors

Automatic routers( for PCB)
Efficient partitioning algorithm

1975 - 1985 Automatic placement tools

Well Defined phases of design of circuits
Significant theoretical development in all phases

1985 – 1995 Performance driven placement and routing tools

Parallel algorithms for physical design
Significant development in underlying graph theory
Combinatorial optimization problems for layout

1995 -- present Interconnect layout optimization, Interconnect-

centric design, physical-logical codesign

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VLSI CAD Conferences

a ACM IEEE Design Automation Conference (DAC)
a International Conference on Computer Aided Design(ICCAD)
a IEEE International Symposium on Circuits and Systems (ISCAS)
a International Conference on Computer Design(ICCD)
a Design, Automation and Test in Europe, Conference and
Exhibition (DATE)
a Asia and South Pacific Design Automation Conference (ASP-
DAC)
a International Symposium on Physical Design (ISPD)

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VLSI CAD Journals

a IEEE Transactions on CAD of Circuits and systems

(T-CAD)
a ACM Trans. on Design Automation of Electronic
Systems (TODAES)
a Integration: The VLSI Journal
a IEEE Transactions on Circuits and Systems
a IEEE Trans. on VLSI Systems
a IEEE Trans. on Computers

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VLSI CAD Organization

a ACM SIGDA (Special Interest Group on Design

Automation)
a IEEE Circuits and System Society
a Design Automation Technical Committee(DATC) of
IEEE Computer Society

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Summary
a Physical design is one of the steps in the VLSI design cycle
a Physical design is further divided into clustering,
partitioning, floorplanning, placement, global and detailed
routing , and compaction
a There are four major design styles -- full custom, standard
cell, gate array, and FPGAs.
a There are three alternatives for packaging of chips -- PCB,
MCM and WSI
a Automation reduces cost, increases chip density, reduces
time-to-market, and improves performance.
a CAD tools currently lag behind fabrication technology,
which is hindering the progress of IC technology

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