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Introduction to Verilog
What you need to know to get started

1/13/2004 Introduction to Verilog 1

What is Verilog?
• Hardware description language (HDL)
– For designing and modeling hardware
• Different levels of abstraction
– From functional description to transistor model

Some constructs are only for simulation and are

not synthesizable!

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Design Hierarchy
• One top level module
– In which zero or more low- level modules can be
– Each low- level module can instantiate lower- level
• Verilog modules are like modules in schematics or
classes in C++
– Use them to make your design more readable and
– Debugging individual module is a lot easier than
debugging the whole system together
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module <module name> ( <list of ports> );
input <width> <input port name>;
output <width> <output port name>;
<variable declarations>

• Module statement defines the interface
– Communication with other modules are done with ports defined in
<list of ports>
• Each port has to be declared as input or output
– Width specified as [n-1:0] for a n-bit port

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Instantiating a Module
<module name> <instance name>(.<port name>(wire/reg name),… )

• Syntax is similar to a procedural call, but the

operation is more like new in C++
• Each .<port name>(signal name) pair specifies a
– Order of connection pairs specified in this style needs
not be the same as that defined in the instantiated
– Signal is a net, a reg or a port in the current module

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Constants and Data Types

• Numbers are decimal by default
– 6’b010010 (6-bit binary)
– 2’o22 (2-bit octal)
– 2’h12 (2-bit hexadecimal)
• Port – input, output, inout
• Net – wire, tri, etc.
– Think physical wire: value == value of driving device
• Reg
– Think storage: value == last assigned value
• Syntax for declaring a net/reg is the same as declaring a
– Width is default to 1-bit if omitted
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• Mostly the same as C operators
• Reduction operators: ~&, ~|, ~^
– AND/OR/XOR all bits together
– Note: same symbols are used for binary bit-wise
• Identity operators: ===, !==
– Compares x and z values (== returns x if either of the input is x)
• Concatenation: {<list of variables>}
• Arithmetic operators – be careful using them in code
intended for synthesis

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• If – else
if (<condition>)

• Case
case (variable)
<constant>: begin
default: begin

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• Continuous assignments
assign <net> = <expression>
– Whenever any changes on the RHS occurs, the
expression is evaluated and assigned to the LHS
– Always implement combinational logic
• Procedural assignments
<reg> = <expression>
– Used within initial and always blocks, which specify
triggers that cause the evaluation of the RHS and
assignment to the LHS

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Procedural Blocks
• Procedural blocks are like concurrent processes
– Statements in a block are executed sequentially, but all
within one unit of simulated time (unless delay is
– All blocks execute in parallel
• Initial blocks
– Execute only once
• Always blocks
– Execute repeatedly _ must have timing control, or else

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Timing Control
• Delays
– #n specifies n units of delay
– Used in between statements in initial and always blocks
• Sensitivity list (list of triggering events)
always @(signal [or signal …])
– Execution of statements in the block is suspended until
one of the signals changes
– Any signals appearing on the RHS of procedural
assignments or in conditions of if-else and case should
be included in the sensitivity list

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• Top level module has
– Instantiation of module(s) to be simulated
– Initial and/or always blocks that drive the input signals
– Code that generates output, stops simulation, etc.
• ModelSim
– Compiles and simulates Verilog (and VHDL)
– Includes tools like source editors and waveform

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Coding Style
• Comments (//, /* */)
– If writing comments is not a habit, develop it now!
• Naming convention
– Be consistent about cases, suffixes, etc.
– Name the file and the module it contains the same thing
– Use meaningful names
• Implicit states
– Make sure reg variables are assigned to through every path of if-
else and case statements
– Always have a matching else for an if and a default in a case
• `define
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