School of Engineering

Department of Electrical, Electronic and

Computer Engineering

Digital Systems
ERS 220
Lecturer: Mr S Reddy
Last revision: 2010-07-13
 TABLE OF CONTENTS

ORGANIZATIONAL COMPONENT ............................................................................................... 3

1. GENERAL PREMISE AND EDUCATIONAL APPROACH....................................................... 3

2. LECTURER, WEBSITE, VENUES AND CONSULTING HOURS ............................................ 3

3. STUDY MATERIALS AND PURCHASES.................................................................................. 4

4. LEARNING ACTIVITIES ............................................................................................................. 4

5. RULES OF ASSESSMENT ........................................................................................................... 5

6. GENERAL...................................................................................................................................... 6

STUDY COMPONENT........................................................................................................................ 8

1. MODULE OBJECTIVES, ARTICULATION AND LEARNING OUTCOMES ......................... 8

2. MODULE STRUCTURE ............................................................................................................... 9

3. GUIDELINES FOR MODULE AND STUDY THEME ............................................................. 11

4. PRACTICAL ASSIGNMENTS ................................................................................................... 13

Lab 1 ................................................................................................................................................. 13

Lab 2 ................................................................................................................................................. 16

Lab 3 ................................................................................................................................................. 19

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 ORGANIZATIONAL COMPONENT

1. GENERAL PREMISE AND EDUCATIONAL APPROACH

The purpose of this course is to familiarise the student with the principles of digital electronics.
Digital electronics is the substance of all modern Information Technology (IT) systems. The simplest
to the most sophisticated computer is based on the very principles you will learn here. The course also
involves the representation of numbers as they are used in digital electronic circuits and computers.
Furthermore, you will become acquainted with both combinational logic (AND-gates, OR-gates,
decoders, etc.) and sequential logic (flip-flops, controllers, etc.). The goal of this course is to develop
the skills to analyse, design and build combinational and sequential digital circuits.

2. LECTURER, WEBSITE, VENUES AND CONSULTING HOURS

Name Office Contact Details

seren.reddy@up.ac.za
Lecturer Mr. S. Reddy Eng 1 14-13
Tel: 420-4334
heleen.gous@eng.up.ac.za
Secretary 1 Mrs. H.S. Gous Eng 1 14-6
Tel: 420-2190
cornel.freislich@up.ac.za
Secretary 2 Mrs. C. Freislich Eng 1 14-8
Tel: 420-3735

ERS220 Web site

A web site has been set up for this course and can be found at
http://www.ee.up.ac.za/main/en/undergrad/subjects/ers220/index. Important announcements,
changes to the study guide, transparencies, class notes, tutorials and assignments, marks and memos,
as well as all arrangements with respect to the practical session will be posted here. Please consult this
page on a regular basis or as instructed during class. Make sure that the cache settings for your
browser are correctly set so that you receive a fresh copy of the ERS220 web site during each
browsing session.

Location of the lecture venues

Refer to the course webpage.

Location of the laboratory

B Lab, Eng 2 1-45 and C Lab, Eng 2 1-9.

Location of the notice board

All announcements/ notices will be posted on the course webpage.

Consulting hours
Hours for consultation of lecturers and teaching assistants will be announced at the beginning of the
semester and will also be displayed on their office doors. Students may consult lecturers and teaching
assistants only during the consulting hours as indicated. All appointments with the lecturer must be
requested and confirmed via email. This policy also holds before tests and examinations. In other
words, lecturers and teaching assistants are only available during their normal consulting hours on the
day before a test or examination. This policy aims to encourage students to plan their work and to
work continuously.

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3. STUDY MATERIALS AND PURCHASES

Prescribed textbook
JF Wakerly: Digital Design: Principles and Practices, 4th Edition, Prentice-Hall International. ISBN
0-13-769191-2.

This book will be used extensively and it is compulsory that each student obtain a copy. A set of the
slides (if applicable) presented during the lectures, as well as other relevant study materials, will be
made available on the module website.

4. LEARNING ACTIVITIES

4.1 Contact time and learning hours

Number of lectures per week: 4
Laboratory work: Three experiments of three hours each per semester.

This module carries a weighting of 16 credits, indicating that on average a student should spend some
160 hours to master the required skills (including time for preparation for tests and examinations).
This means that on average you should devote some 10 hours of study time per week to this module.

4.2 Lectures
Lectures are presented in a style of co-operative and student-centred learning. Brief clarification and
explanation of the subject matter and concepts are given during the lectures. Problems related to the
subject matter are posed and students are expected to attempt the problems on their own. All the
relevant study material is adequately referenced and is available in the textbook, the study guide and
on the module website.

N.B All lectures will be presented in English.

4.3 Class Tests

Three class tests will be given during the semester. The dates for these class tests will be announced
later. These class tests will contribute toward your semester mark (see below).

4.4 Assignments
Two to three homework assignments may be given during the semester. The dates for submission of
these assignments will be announced later. These assignments will contribute toward your semester
mark (see below). You will be given sufficient time to complete the assignments, and should plan
your time accordingly. No late assignments will be accepted.

4.5 Laboratory work

Each student has to attend and complete all three ERS220 practical sessions of three hours each,
during the semester. All practical sessions are compulsory: failure to fully complete a practical
session will lead to examination refusal. The schedule for the practical sessions, division of groups,
laboratory venue, as well as the practical guides will be issued during the course of the semester.
These details will also be posted on the ERS 220 module website. Please consult the General Guide
for Students for general procedures regarding the practical sessions, such as the laboratory rules and
after-hours access to the labs. Lab reports must be in English and NO late lab reports will be
accepted.

Additional information regarding the practical sessions will be made available on the module website
and also as hardcopies at the start of the semester. Groups must do their own work during each
practical.

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Laboratory notebooks
Each student of the team must acquire an A4-size hard-cover notebook, in which complete dated
notes and sketches are kept that show the development of the practical, including preliminary designs,
experiments done in the laboratory, design evaluations, and technical details of the design. Details of
how a laboratory notebook should be kept are given in the EEC Guide. The laboratory notebook may
be evaluated at any time.

N.B All laboratory lectures will be presented, and must be demonstrated, in English.

5. RULES OF ASSESSMENT

See also the examination regulations in the Year Books of the Faculty of Engineering, Built
Environment and Information Technology (Part 1: Engineering).

Examination admission
For examination admission, a semester mark of 40% and a special exam mark of 40% are required.

Pass requirements
In order to pass the module, a student must:

1. Obtain a final mark of at least 50%.

2. Obtain a sub minimum of 40% for the laboratory work and must also attend all the
scheduled laboratory sessions.

If a student has obtained a final mark of 50% or more but does not meet the laboratory requirements,
the laboratory work must be repeated successfully before a pass will be awarded.

Final mark
The final mark is calculated as follows:

Semester mark: 50.0%

Examination mark: 50.0%

Semester mark
The semester mark is calculated as follows:

Semester Test 1: 31.0%

Semester Test 2 : 31.0%
Lab Assignment 1: 3.5%
Lab Assignment 2: 5.0%
Lab Assignment 3: 7.5%
Class Test 1: 4.0%
Class Test 2: 4.0%
Class Test 3: 4.0%
Special Exam (FPGA): 10.0%

Semester tests
Two tests of 90 minutes each will be written during the scheduled test weeks of the School of
Engineering:

First test week: 14 – 21 August 2010

Second test week: 4 – 9 October 2010

Exact dates, times and venues will be announced as soon as the timetables become available.

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6. GENERAL

6.1. Absence from formal evaluation opportunities and practical sessions:

The Departmental procedure on special examinations and tests, including illness tests and
examinations, as described in the EEC Guide, which is available on the departmental web site at
http://www.ee.up.ac.za/main/en/undergrad/guides, will be followed in the event of absence from
examinations, tests and practical sessions, and when compulsory assignments are not handed in on
time.

Each student must attend all the practical session scheduled for his/her practical group, class test
scheduled for his/her class and semester test sessions. If you are unable to attend such a session, a
written apology, together with a medical certificate, must be presented to the lecturer. Failure to do
so will result in immediate examination refusal. This rule will also be enforced for all pre-practical
lecture sessions.

6.2. Academic dishonesty:

Refer to the EEC Guide at http://www.ee.up.ac.za/main/en/undergrad/guides for the procedures
that will be followed in the advent of academic dishonesty.

Plagiarism warning
Students are encouraged to discuss work with each other. However, each student should hand in
his/her own work for assignments. Plagiarism, which also includes copying the work of another
student during tests and exams and copying from the Internet, can lead to expulsion from the
University.

Even if another student gives you permission to use his/her assignments or other research to hand in
as you own, you are not allowed to do it. It is a form of plagiarism. You are also not allowed to let
anybody copy your work with the intention of passing it off as his/her own work.

Speak to your lecturer if you are uncertain about what is required. For more information, see
http://www.ee.up.ac.za/en/undergrad/guides or consult the brochure available at the Academic
Information Service.

A statement regarding the originality of your work must be appended to ALL written work submitted
for evaluation in this module. The statement can be found at
http://www.ee.up.ac.za/en/undergrad/guides.

6.3. Satisfactory completion of tutorials:

Each student must complete every tutorial. Failure to do so will result in examination refusal.

6.4. General rules regarding tutorials and practical reports:

Unless otherwise indicated, students must complete tutorials and practical reports individually.

Should you fail to comply with this rule, any of the following steps can be taken:
• Marks awarded to the students who handed in similar work, will be divided by a factor of N,
where N can take on any value from 2 to 4. Your mark will be divided even if you were not
aware that someone copied your work - Ignorance is not an excuse!
• You will receive examination refusal.

• No late lab reports or assignment will be accepted.

• If you have failed to complete all your tutorials to date, you will not be entitled to additional
assistance from the lecturers during their consulting hours.

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6.5. Take note of the following important points:
• It is not the responsibility of the lecturer to make you learn, but rather to assist you to make
the best use of your opportunities. Learning is best facilitated when there is a genuine need to
know. Make it your responsibility to best utilize all available resources, e.g. the lecturer’s
knowledge, lab facilities, the WWW, related magazines, etc., to maximize your understanding
and skill.
• Self-study will play an important role during this course.
• Although attendance of lectures is not compulsory, additional material supplementary to the
textbook may be presented during class and will be examinable. Where possible, this
additional material will be posted on the ERS220 web site.
• Since it is assumed that you are attending class, important announcements will be made there,
such as arrangements for practical sessions, tutorials and discussions relating to the content of
tests. Where possible, these announcements will also appear on the Announcements page of
the ERS220 web site.
• The lecturer reserves the right to make various changes to the content of this Study Guide
during the course of the semester. Any changes will be announced during class and will be
posted on the Announcements page of the ERS220 web site.

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 STUDY COMPONENT

1. MODULE OBJECTIVES, ARTICULATION AND LEARNING OUTCOMES

1.1 General objectives

1. Learning is best facilitated when there is a genuine need to know! It is the purpose of the
lectures to facilitate and aid your learning by creating the awareness of a knowledge vacuum.
However, the process of meaningful learning is only possible when it is driven by your
genuine enthusiasm and desire to learn, sparked by the challenge to acquire and master new
concepts. It is not the lecturer's responsibility to make you learn, but rather to work together
with you to help you make the best use of an opportunity.
2. The lectures provide an important overview of the work, and as far as time allows, an
opportunity to understand the details of various techniques. However, due to the limited
contact time, self-study is an essential component to the course, without which it will be
impossible to master the work.
3. This study guide provides only a rough outline of the work dealt with. Your most important
source of information is the textbook and the lectures.
1. It is assumed that you attend class, and hence, important announcements will be made there,
such as arrangements for practical sessions, homework assignments and tutorials, and
discussions relating to the content of tests. Where possible, these will also appear on the
ERS 220 module website.

1.2 ECSA Exit Level Outcomes

At the conclusion of this module the student will be capable of:

1.2.1 Problem solving

Learning outcome: Demonstrate competence to identify, assess, formulate and solve convergent and
divergent engineering problems creatively and innovatively.

1.2.2 Application of scientific and engineering knowledge

Learning outcome: Demonstrate competence to apply knowledge of mathematics, basic science and
engineering sciences from first principles to solve engineering problems.

1.2.3 Engineering Design

Learning outcome: Demonstrate competence to perform creative, procedural and non-procedural
design and synthesis of components, systems, engineering works, products or processes.

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 1.3 Cognitive level of assessment

Component %
1. Knowledge 20
2. Comprehension 15
3. Application 20
4. Analysis 10
5. Synthesis 20
6. Evaluation 5
7. Other Skills 10
• Report writing and language skills
• Team working skills

2. MODULE STRUCTURE

The following topics will be covered in the course (the allocated time is only approximate):

Study Themes and Mode of Instruction Notional Contact

Hours Sessions
Study Units

1. Administration Class discussion 1 1

Discuss course content and teaching approach

Encourage web registration

Assignment of practical groups

2. Basic Principles of Digital Systems (Chapter 1) Lectures and class 8 2

discussions, tutorial

Introduction
classes, tutorials, self-

Background to digital circuits and systems.
study

3. Number Representations (Chapter 2) Lectures and class 10 5

discussions, tutorial

Positional number systems, especially binary, octal
classes, tutorials, self-
and hexadecimal representations.
study

Addition and subtraction of the above numbers.

Representation of negative numbers.

Operations with negative numbers.

Binary multiplication and division.

Binary codes and error correction.

4. Digital circuits (Chapter 3) Lectures and class 12 6

discussions, tutorial

Logical signals and gates.
classes, tutorials, self-

Electronics overview: Ohm's Law, charge and
study
discharge of capacitors, and transistors.

CMOS logic circuits: general.

Static and dynamic behaviour of CMOS circuits.

Input and output structures, CMOS logic families.

Binary logic and TTL.

Integrated circuits.

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5. Combinational Logic Principles (Chapters 4) Lectures and class 12 6
discussions, tutorial

Principles of combinational logic
classes, tutorials, self-

Boolean algebra
study

Analysis of combinational circuits.

Synthesis and design of combinational circuits.

Hazardous conditions.

6. Hardware Description Languages (Chapter 5) Lectures and class 8 5

discussions, tutorial

HDL Based Design
classes, tutorials, self-

VHDL
study

7. Combinational Logic Design (Chapter 6) Lectures and class 18 7

discussions, tutorial

Practical aspects of combinational logic
classes, tutorials, self-

Documentation and timing diagrams.
study

Various components: decoders, encoders, buffers,
multiplexers, XOR-gates, comparators.

Combinational-circuit design examples

Combination logic using VHDL

8. Sequential Logic (Chapters 7 and 8) Lectures and class 30 13

discussions, tutorial

Sequential logic design principles (Chapter 7)
classes, tutorials, self-

Bistable elements and flip-flops.
study

Analysis of clocked (synchronous) state machines.

Design of clocked (synchronous) state machines.

Practical aspects of sequential logic (Chapter 8)

Documentation of sequential circuits.

Different components, e.g.: latches, flip-flops,
counters, shift registers, etc.

Iterative circuits.

Sequential logic using VHDL

9. Memory (Chapter 9) Lectures and class 8 2

discussions, tutorial

ROM, RAM, FPGA
classes, tutorials, self-
study

10. Revision Lectures and class 5 2

discussions, self-study

Themes 2 to 9

11. Practical Assignments Practical sessions, 40 24

simulations,

Assignment 1 demonstrations, reports

Assignment 2

Assignment 3

12. Special Exam Lectures and class 8 2

discussions, tutorial
classes, tutorials,
practical sessions,
simulations,
demonstrations,

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 reports, self-study

160 75

3. GUIDELINES FOR MODULE AND STUDY THEME

Learning outcomes of the study theme

The given learning outcomes for each study theme are essential to achieve the critical learning
outcomes as set out in Section 1.2.

Study units
The title of the study unit and references to appropriate study material (To be discussed in lectures and
on the course webpage) are given here. The study of the referenced study material is regarded as the
minimum required to achieve the learning outcomes satisfactorily.

Criteria of assessment
The criteria of assessment are a list of specific skills to be mastered by the student in order to achieve
the learning outcomes of the syllabus theme. During assessment (tests and the examination), students
will be evaluated in terms of these criteria.

The statements used to define the criteria of assessment are classified in terms of a series of lower- to
higher-order thinking skills (cognitive domains), in accordance with Bloom's Taxonomy of
Educational Objectives (Bloom BS and Krathwohl DR, Taxonomy of educational objectives.
Handbook 1. Cognitive domain, Addison-Wesley, 1984):

6. Evaluation

5. Synthesis

4. Application

Level of
3. Analysis Complexity

2. Comprehension

1. Knowledge

The characterization of the cognitive domains is given in the table below.

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 Cognitive Domain Definition Typical Action Verbs

1. Knowledge Remembering previously Arrange, define, describe,

learned information. identify, label, list, match,
name, outline

2. Comprehension Understanding the meaning of Classify, discuss, estimate,

information. explain, give example(s),
identify, predict, report, review,
select, summarize, interpret, "in
your own words"

3. Application Using the information Apply, calculate, demonstrate,

appropriately in different illustrate, interpret, modify,
situations predict, prepare, produce, solve,
use, manipulate, put into
practice

4. Analysis Breaking down the information Analyze, appraise, calculate,

into the component parts and compare, criticize, derive,
seeing the relationships. differentiate, choose,
distinguish, examine, subdivide,
organize, deduce

5. Synthesis Putting the component parts Assemble, compose, construct,

together to form new products create, design, determine,
and ideas. develop, devise, formulate,
propose, synthesize, plan,
discuss, support

6. Evaluation Making judgments of an idea, Appraise, assess, compare,

theory, opinion, etc., based on conclude, defend, determine,
criteria. evaluate, judge, justify,
optimize, predict, criticize

The list of criteria of assessment for a study theme and its accompanying envisaged learning outcomes
should contain statements applicable to all six levels of thinking. Accordingly, students will be
evaluated in terms of a mix of all six levels of thinking skills. On the first-year level, a larger
proportion of questions will be based on the lower levels (levels 1 to 3), whilst final-year
examinations will contain a larger proportion of questions based on the higher-level thinking skills
(levels 4 to 6).

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4. PRACTICAL ASSIGNMENTS

Lab 1

Combinational Logic Design

1. Description

For this practical a 3 bit adder will be designed. Two 3 bit binary numbers will be sent into a
combinational logic circuit using 6 DIP switches. The result will be displayed on 4 LED’s. They will
indicate the 3 bit result and also whether a Carry or overflow occurred.

Figure 1: Block diagram of 3 bit adder

2. Description of functional blocks

• The DIP switches are used to enter the two binary values Represented by A and B. A is a
three bit word composed of A2, A1 and A0 where A2 is the most significant bit and A0 the
least significant bit. B2, B1 and B0 are the most to least significant bits of B respectively7.
• There are 4 LED’s connected to the output of the 3 bit adder. C is the bit indicating that a
Carry has occurred. The result is represented by Y where Y2, Y1 and Y0 are the most to least
significant bits respectively.
• The output should also be displayed on a seven segment display. You will be rewarded with
an additional 10% (and immense satisfaction) for a working implementation using the 7-
segment display.

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3. Technical detail

3.1. DIP switches:

The DIP switches must be connected in such a way that when the switch is closed a HIGH output
condition is generated, and when open a LOW condition is generated. This is achieved by using a
pull-up resistor as shown in the figure below.

Figure 2: DIP switches and pull-up resistors

The resistor value R should be chosen so that the input is pulled up without wasting too much current
when the DIP switch is closed. A value of between 1 k ohm and 10 k ohm should suffice.

3.2. LED’s:

It will also be necessary to add resistors to the output of the gate driving the LED’s. Read the
manufacturers datasheet for the gateway driving the LED’s and determine the maximum current
allowed, and how big the resistors have to be to protect the LED’s from too much current, and also to
protect the output of the gate driving the LED. Usually such a resistor is around 100 to 330 ohms.

3.3. Components:

The following components must be purchased before the practical:

2 x 74HCT238

2 x 74HCT574

4 x 74HCT393

4 x 74HCT04

6 x 74HCT08

8 x 74HCT32

4 x 74HCT86

12 x 5mm Red LED's

2 x 4-Way DIP switch

2 x 7-Segment Display (including driver)

The datasheets will be made available on the course webpage.

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4. Deliverables

• Implementation of the system as described above using the provided components.

• A full report must be handed in during the demonstration following proper reporting
guidelines. The content must include the following:

o Truth tables
o Karnaugh map simplification
o Mathematical simplification
o Circuit diagrams for the simplified circuit

All planning and results must be written down in your lab books and this information used to generate
the full report.

5. Demo

The demo times will be made available as soon as the groups have been finalised.

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 Lab 2

Hamming Error-Correction Code

1. Goal

After this practical you should feel comfortable with designing and building combination logic
circuits. You will be exposed to Karnaugh maps and get a good idea of what is involved in translating
good idea into a logic circuit. At the same time you will experience the satisfaction of capturing some
beautiful Information Theory in silicon.

2. Assignment

2.1. Part 1 (Discrete Design)

You are expected to design and implement an error-detecting decoder using discrete gates. The
system will take a potentially corrupted 8-bit Hamming code as input and display the 'error diagnosis'
at its output. The codeword contains four data bits and four redundancy (parity-check) bits. The code
is defined by the parity-check matrix H.

This is a distance-4 Hamming code which means that it can detect and correct 1-bit errors and detect
2-bit errors. Fig. 1 shows a block diagram of an error-detecting decoder. The system can be divided
into two main parts, and each can be designed and built separately.

Part one consists of four parity generators (labelled as PG1-PG4 in the block diagram). Each one
produces a logical TRUE whenever the four bits that it monitors have odd parity. The bits connected
to each block are defined by the four rows of the parity-check matrix H.

Figure 3 Odd parity generators

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The position of a '1' in a row indicates that the bit that it refers to (7 to 0 from left to right) should be
connected to the corresponding block (1 to 4 from top to bottom). The top most block (PG1) serves as
an example. You are to design these four (identical) blocks using only XOR gates (74LS86). The
outputs of the four parity generators together constitute the syndrome vector.

There are sixteen possible syndrome vectors. The [0 0 0 0] vector indicates that there are no 1- or 2-
bit errors. The eight vectors that correspond to the columns of H signal a 1-bit error, and the position
of the corrupted bit in the codeword is the same as that of the column in the matrix (numbered from 7
to 0 from left to right). The remaining seven syndrome vectors each signal a 2- bit error (which cannot
be corrected). The following list is a summary of all the syndrome vectors with the number of error
bits and the bit position of the 1-bit errors where applicable.

The second part of the system is a syndrome vector decoder and represents a combination logic circuit
of your own design that maps the syndrome vectors to the outputs as defined by the above list (see
also Figure 3). The decoded information can be displayed in one of two ways:

• You may use an array of LED's, each connected to one of the 10 outputs of the decoder. Since
the output is a 1-out-of-10 code, only one LED is illuminated at a time, or
• The output may be displayed on a seven segment display. If a one bit error occurs, the number
of the corresponding corrupted bit should be displayed.

An eight should be displayed when a 2 bit error occurs and a nine when legal code words occur. You
will be rewarded with an additional 10% (and immense satisfaction) for a working implementation
using the 7-segment display.

For this section of the design you may only use AND (74LS08), OR (74LS32) and NOT (74LS04)
gates. As you will be buying the components for the practical yourself, you will enjoy optimizing the
design for cost (that is, number of gates). No PICs will be allowed.

It would be a good idea to use an '8 bit switch' to generate the input byte. This may be implemented
with a DIP switch. For demonstration purposes, input bits 7 to 0 should be made available for direct
visual inspection by connecting them to LED's (You will find it to be an invaluable aid when testing
and debugging the circuit).

2.2. Part 2 (FPGA Design)

You are expected to design and implement Part 1 using VHDL and an FPGA.

3. Report

In designing a good system, one tends to generate huge amounts of documentation. Properly selected,
prepared and presented, this can be made into a report that will earn you a potential 40% of the marks
for the practical. A good report should consolidate a description of the working of the system, the
relevant logic equations, Karnaugh maps and circuit diagrams. You only have to hand in one report
per group.

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4. Demonstration

Your exercise in creative electronics will be evaluated during the practical. You will work in groups
of two and the group will be evaluated as a whole. Marks will be awarded for the performance of your
circuit, the report and answers to informal questions. You have to work on the practical on your own
time. The practical session is only for demonstrations.

5. Lecture

A preparation lecture will be given prior to the practical.

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 Lab 3

Sequential Circuit Design (Ping-pong)

1. Description

In this practical a ping-pong game will be designed. Figure 1 illustrates what the system should look
like.

Figure 4: LED ping pong game illustration

2. Description of operation

The game will start with the LED's flashing in sequence indication the movement of a ping-pong ball
in two dimensions. The ball will start at the right with RLAMP and move left to LLAMP. The
purpose of the game is to bounce the ball back by pressing the LPB button when the ball has reached
the LLAMP. Holding the button will hold the ball at LLAMP till it is released/bounced back by
releasing LPB. The ball will then move from LLAMP to RLAMP and must be bounced back by using
button RPB.

The ball is missed by pressing the LPB button when the LLAMP is not lit and will result in the ball
starting from RLAMP (automatic serve). Similarly, the ball is missed when RPB is pressed when
RLAMP is not lit.

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3. Technical detail

The state diagram in figure 5 may be used (and modified) to suit the game. The diagram is not
complete and is intended as a starting point only.

Figure 5: State diagram for ping-pong game

It is worth noting that at least 4 flip-flops will be required to solve this problem. Three flip-flops may
be used to indicate the specific LED that should be lit, and the fourth used to indicate the direction of
motion of the ball.

The supplied DIP switches may be used as buttons, although it will require the game to operate quite
slowly. Alternatively, push buttons may be used.

Hint: It could be possible to simplify the above diagram to four possible states:

1. Stopping on the left hand side (STOPL)

2. Moving/ running from right to left (RUNR)
3. Moving/ running from left to right (RUNL)
4. Stopping on the right hand side (STOPR)

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4. Deliverables

4.1. Hardware:

No PICs will be allowed.

4.1.1. Part 1 (Discrete Design)

A ping-pong game, as described above, built using discrete gates and/ or register and latch circuits.
Additional marks will be given for implementing a counter system using CMOS counters and 7
segment displays. The counters should keep track of the scores of the two players. The first player to
reach 9 wins.

Hint: Investigate the use of Shift Registers.

4.1.2. Part 2 (FPGA Design)

You are expected to design and implement Part 1 using VHDL and an FPGA.

4.2. Documentation:

Full report following reporting standards as for practical 1 with the following specific details:

• Detailed state diagram

• Transition list
• Karnaugh simplification (if applicable – note there is a lot of room for simplification, even by
inspection)
• Logic diagram

5. Demo

The date for the demo of this practical will be made available at a later date.

6. Lecture

A preparation lecture will be given prior to the practical.

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