SN54/74LS540

OCTAL BUFFER/LINE DRIVER SN54/74LS541

WITH 3-STATE OUTPUTS
The SN54 / 74LS540 and SN54 / 74LS541 are octal buffers and line drivers
with the same functions as the LS240 and LS241, but with pinouts on the
opposite side of the package. OCTAL BUFFER / LINE DRIVER
These device types are designed to be used as memory address drivers, WITH 3-STATE OUTPUTS
clock drivers and bus-oriented transmitters / receivers. These devices are
especially useful as output ports for the microprocessors, allowing ease of LOW POWER SCHOTTKY
layout and greater PC board density.
• Hysteresis at Inputs to Improve Noise Margin
• PNP Inputs Reduce Loading
• 3-State Outputs Drive Bus Lines
• Inputs and Outputs Opposite Side of Package, Allowing Easier J SUFFIX
Interface to Microprocessors CERAMIC
• Input Clamp Diodes Limit High-Speed Termination Effects CASE 732-03
20
LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) 1

SN54 / 74LS540
VCC
N SUFFIX
20 19 18 17 16 15 14 13 12 11
PLASTIC
CASE 738-03
20
1

DW SUFFIX
1 2 3 4 5 6 7 8 9 10 SOIC
GND 20
CASE 751D-03
SN54 / 74LS541 1
VCC
20 19 18 17 16 15 14 13 12 11

ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
1 2 3 4 5 6 7 8 9 10
GND

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54 – 12 mA
74 – 15
IOL Output Current — Low 54 12 mA
74 24

FAST AND LS TTL DATA

5-1
 SN54/74LS540 • SN54/74LS541

BLOCK DIAGRAM
LS540 LS541
(1) (1)
E1 E1
(19) (19)
E2 E2 INPUTS OUTPUTS
E1 E2 D LS540 LS541
(2) (18) (2) (18)
D1 Y1 D1 Y1 L L H L H
H X X Z Z
(3) (17) (3) (17) X H X Z Z
D2 Y2 D2 Y2 L L L H L
(4) (16) (4) (16) L = LOW Voltage Level
D3 Y3 D3 Y3 H = HIGH Voltage Level
(5) (15) (5) (15) X = Immaterial
D4 Y4 D4 Y4 Z = High Impedance
(6) (14) (6) (14)
D5 Y5 D5 Y5
(7) (13) (7) (13)
D6 Y6 D6 Y6
(8) (12) (8) (12)
D7 Y7 D7 Y7
(9) (11) (9) (11)
D8 Y8 D8 Y8

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54, 74 2.4 3.4 V VCC = MIN, IOH = – 3.0 mA
VOH Output HIGH Voltage
54, 74 2.0 V VCC = MIN, IOH = MAX, VIL = 0.5 V

54, 74 0.25 0.4 V IOL = 12 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 24 mA per Truth Table

VT+–VT– Hysteresis 0.2 0.4 V VCC = MIN

IOZH Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V
IOZL Output Off Current LOW – 20 µA VCC = MAX, VOUT = 0.4 V
20 µA VCC = MAX, VIN = 2.7 V
IIH Input HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current – 0.2 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) – 40 – 225 mA VCC = MAX
Power Supply Current
mA
Total, Output HIGH LS540 25

LS541 32 mA

ICC LS540 45 mA VCC = MAX

Total Output LOW
Total,
LS541 52 mA
LS540 52 mA
Total Output 3-State
LS541 55 mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

5-2
 SN54/74LS540 • SN54/74LS541

AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tPLH LS540 9.0 15
tPLH Propagation
P p g i D Delay,
l y, LS541 12 15
ns
tPHL Data to Output LS540 12 15
tPHL LS541 12 18 VCC = 5.0
50V
CL = 45 pF
Output
p Enable Time LS540 15 25 RL = 667 Ω
tPZH ns
to HIGH Level LS541 15 32

Output
p Enable Time LS540 20 38
tPZL ns
to LOW Level LS541 20 38

Output
p Disable Time LS540 10 18
tPHZ ns
to HIGH Level LS541 10 18
CL = 5.0
5 0 pF
F
Output
p Disable Time LS540 15 25
tPLZ ns
to LOW Level LS541 15 29

AC WAVEFORMS
VCC
VIN 1.3 V 1.3 V
RL
tPLH tPHL

VOUT 1.3 V 1.3 V

SW1
Figure 1
TO OUTPUT
UNDER TEST
VIN 1.3 V 1.3 V
tPLH tPHL
5 kΩ
VOUT 1.3 V 1.3 V
CL* SW2
Figure 2

VE
1.5 V 1.5 V
VE
tPZL tPLZ

VOUT 1.5 V ≈ 1.5 V

VOL
0.5 V SWITCH POSITIONS
Figure 3 SYMBOL SW1 SW2
tPZH Open Closed
VE tPZL Closed Open
1.5 V 1.5 V
VE tPLZ Closed Closed
tPZH tPHZ
≥VOH tPHZ Closed Closed
VOUT 1.5 V ≈ 1.5 V
0.5 V
Figure 4 Figure 5

FAST AND LS TTL DATA

5-3
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