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Abstract-To reduce the power consumption, a 4:1 multiplexer The block diagram of the MUX is shown in Fig. 1. The 4:1
using the CMOS logic is presented for high-speed operation. The MUX consists of two low-speed 2:1 MUXs which synthesize
proposed circuit adopts tree-type and half-rate structure. The
CMOS logic, such as the dynamic CMOS and pseudo-static four 2.5 Gb/s input random signals to two 5 Gb/s signals, a
CMOS logic, is renewed in this design. The designed circuit is high-speed 2:1 MUX which receives two 5 Gb/s data streams
realized in a standard 0.18 μm CMOS process and uses 1.8 V and outputs 10 Gb/s data stream and an output buffer used to
supply voltage. The post simulated result shows that the fully drive the external 50 Ohm load.
integrated MUX operates well up to 10 Gb/s. The simulated eye In this paper, all 2:1 MUXs are composed of a master-slave
opening is 200 mVpp on an external 50 Ohm load. The power
consumption of the MUX is 53.3 mW at 10 Gb/s. The overall chip flip-flop (MS-FF), a master-slave-master flip-flop (MSM-FF)
has a size of 0.575×0.475 mm2 and the core size is 0.18×0.12 mm2. and a 2:1 selector. Compared with the signal passing through
the MS-FF, the signal passing through the MSM-FF emerges
I. INTRODUCTION an additional 180○ phase shift. To ensure that two signals for
the 2:1 selector are in-phase, a pair of input buffers (InBuf and
Serial data communication systems operating at throughputs
InBufn, shown in Fig. 1) is used.
of 10 Gb/s have been applied in recent years to increase
In order to obtain a large enough phase margin, the data
transmission capacity. A data multiplexer (MUX) is a key block
selector should sample in the center of the input data. That is
in high-speed data communication systems. Several MUX
the reasons for inserting the clock delay buffer to the clock
circuits have been reported in technologies such as SiGe, GaAs
channel of low-speed 2:1 MUXs. However, in the high-speed
and InP at speeds of 10 Gb/s or higher [1]-[3]. However, in
2:1 MUX, the delay of latches produces enough phase
deep-submicron, the CMOS process could also operate at high
difference between the data sampled and clock pulse for the 2:1
speed. In consideration of the fabrication cost, it is desirable to
selector. Therefore, the clock delay buffer can be omitted in the
utilize a standard CMOS process for 10 Gb/s or higher
high-speed 2:1 MUX.
systems.
The digital CMOS logic is always used for low speed
operation. Reference [4], the authors believe that the maximum
data rate of the chips using CMOS logic flip-flop circuits, are
limited by the toggle frequency of CMOS logic. For example,
the maximum toggle frequency of a conventional 0.18 μm
CMOS inverter could not operate at more than 3.5 GHz.
According to their simulated result, they consider that the
power consumption of current mode logic (CML) becomes
smaller than the CMOS logic at more than 2.5 Gb/s. Therefore,
during the past decade, multiplexer circuits in most
international papers have used CML structure for super high
speed systems in CMOS process [5]-[7]. Figure 1. Overall architecture 4:1 MUX
Actually, the CMOS logic can operate at higher frequency Difference clock signals at 5GHz are supplied to the
than the frequency above and maintain low power consumption. high-speed 2:1 MUX. The clock signals are transformed to 2.5
It also has some contribution of reducing layout area. In this GHz clock for low-speed 2:1 MUXs by the 1/2 divider.
paper, a 4:1 MUX using CMOS logic has been designed to
operate up to 10 Gb/s in 0.18 μm CMOS process. It adopts III. CMOS LOGIC CIRCUIT
half-rate and tree-type structure and consumes relatively low In the traditional design of MUX, all sub-circuits of the
power. MUX use CML. The logic circuit can achieve high operation
II. MULTIPLEXER STRUCTURE rate, but has a sustained current power consumption. That is
Figure 4. Circuit schematics of latches (A) 5 GHz Latch (B) 2.5GHz latch
Therefore two kinds of latch, shown in Fig. 4, are used in
high-speed and low-speed MUX respectively, which optimizes
4:1 MUX for low power consumption while achieving high
speed.
IV. SIMULATED RESULT
Fig. 5 shows the layout of 4:1 MUX. The chip has a size of
Figure 6. Simulated eye diagram for 10 Gb/s 4:1 MUX
0.575×0.475 mm2 and is determined by the pad frame. The core
area is only about 0.18×0.12 mm2. In post simulation, four V. CONCLUSION
pseudo-random input signals (PRBS) with a sequence length of
27-1 are provided to the MUX. The input signal voltage swing A 4:1 MUX circuit is successfully designed in 0.18 μm
is 1.8 V (from VDD to GND). The difference clock signals have CMOS process. The circuit uses the CMOS logic to multiplex
a voltage swing of 1.8 V. With PRBS data inputs applied, the four data streams to a high-speed signal. The simulation proves
10 Gb/s output eye diagram, simulated by Cadence software, is that it operates well at 10 Gb/s under normal temperature with
shown in Fig. 6. The eye diagram has 200 mV vertical eye only about 53.3 mW power consumption.
opening with random jitter of 14ps on an external 50 Ohm
load.
TABLE 1
SUMMARY OF THE 4:1 MUX
Figure 5. 0.18 μm 4:1 MUX layout
Function 4:1 MUX
Four data patterns (D1: 11001000, D2: 01101001, D3:
Input bit rate 2.5 Gb/s
10000111, D4:01110001) at 2.5 Gb/s and 5 GHz difference
Output bit rate 10 Gb/s
clock signals input to 4:1 MUX. Then the corresponding output
Supply voltage 1.8 V
pattern at 10 Gb/s should be that: 1010, 1101, 0101, 0001, 1100,
Current consumption 29.6 mA
0010, 0010, 0111. Fig. 7 shows the output signal pattern
Power dissipation 53.3 mW
diagram as the result. By comparing the right data pattern and
the simulated diagram, the logic function of MUX is proved to Chip size 0.575×0.475 mm2
be correct. Technology 0.18 μm, fT = 49 GHz
multiplexer/demultiplexer ICs using current mode logic with tolerance to
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