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Proceedings of International Symposium on Signals, Systems and Electronics (ISSSE2010)

A 10 Gb/s Low-power 4:1 Multiplexer

in 0.18 μm CMOS
Xiang Sun1,2, Jun Feng1
1 Institute of RF- & OE-ICs, Southeast University, 210096, Nanjing, China
2 School of Integrated Circuit, Southeast University, 210096, Nanjing, China

Abstract-To reduce the power consumption, a 4:1 multiplexer The block diagram of the MUX is shown in Fig. 1. The 4:1
using the CMOS logic is presented for high-speed operation. The MUX consists of two low-speed 2:1 MUXs which synthesize
proposed circuit adopts tree-type and half-rate structure. The
CMOS logic, such as the dynamic CMOS and pseudo-static four 2.5 Gb/s input random signals to two 5 Gb/s signals, a
CMOS logic, is renewed in this design. The designed circuit is high-speed 2:1 MUX which receives two 5 Gb/s data streams
realized in a standard 0.18 μm CMOS process and uses 1.8 V and outputs 10 Gb/s data stream and an output buffer used to
supply voltage. The post simulated result shows that the fully drive the external 50 Ohm load.
integrated MUX operates well up to 10 Gb/s. The simulated eye In this paper, all 2:1 MUXs are composed of a master-slave
opening is 200 mVpp on an external 50 Ohm load. The power
consumption of the MUX is 53.3 mW at 10 Gb/s. The overall chip flip-flop (MS-FF), a master-slave-master flip-flop (MSM-FF)
has a size of 0.575×0.475 mm2 and the core size is 0.18×0.12 mm2. and a 2:1 selector. Compared with the signal passing through
the MS-FF, the signal passing through the MSM-FF emerges
I. INTRODUCTION an additional 180○ phase shift. To ensure that two signals for
the 2:1 selector are in-phase, a pair of input buffers (InBuf and
Serial data communication systems operating at throughputs
InBufn, shown in Fig. 1) is used.
of 10 Gb/s have been applied in recent years to increase
In order to obtain a large enough phase margin, the data
transmission capacity. A data multiplexer (MUX) is a key block
selector should sample in the center of the input data. That is
in high-speed data communication systems. Several MUX
the reasons for inserting the clock delay buffer to the clock
circuits have been reported in technologies such as SiGe, GaAs
channel of low-speed 2:1 MUXs. However, in the high-speed
and InP at speeds of 10 Gb/s or higher [1]-[3]. However, in
2:1 MUX, the delay of latches produces enough phase
deep-submicron, the CMOS process could also operate at high
difference between the data sampled and clock pulse for the 2:1
speed. In consideration of the fabrication cost, it is desirable to
selector. Therefore, the clock delay buffer can be omitted in the
utilize a standard CMOS process for 10 Gb/s or higher
high-speed 2:1 MUX.
The digital CMOS logic is always used for low speed
operation. Reference [4], the authors believe that the maximum
data rate of the chips using CMOS logic flip-flop circuits, are
limited by the toggle frequency of CMOS logic. For example,
the maximum toggle frequency of a conventional 0.18 μm
CMOS inverter could not operate at more than 3.5 GHz.
According to their simulated result, they consider that the
power consumption of current mode logic (CML) becomes
smaller than the CMOS logic at more than 2.5 Gb/s. Therefore,
during the past decade, multiplexer circuits in most
international papers have used CML structure for super high  
speed systems in CMOS process [5]-[7]. Figure 1. Overall architecture 4:1 MUX
Actually, the CMOS logic can operate at higher frequency Difference clock signals at 5GHz are supplied to the
than the frequency above and maintain low power consumption. high-speed 2:1 MUX. The clock signals are transformed to 2.5
It also has some contribution of reducing layout area. In this GHz clock for low-speed 2:1 MUXs by the 1/2 divider.
paper, a 4:1 MUX using CMOS logic has been designed to
operate up to 10 Gb/s in 0.18 μm CMOS process. It adopts III. CMOS LOGIC CIRCUIT
half-rate and tree-type structure and consumes relatively low In the traditional design of MUX, all sub-circuits of the
power. MUX use CML. The logic circuit can achieve high operation
II. MULTIPLEXER STRUCTURE rate, but has a sustained current power consumption. That is

978-1-4244-6355-8/10/$26.00 ©2010 IEEE

because it has a continuous tail current. It is a typical leakage and diode leakage current, resulting in error. Therefore,
power-for-speed design. In this paper, CMOS logic is used. a dynamic latch, the storage node A must be periodically
Because the CMOS logic uses power only when charging and refreshed. High-speed 2:1 multiplexer over the clock in the
discharging, the chip almost has no static power consumption. 5GHz fully meet the requirement.
Fig. 2 shows inverters of the CMOS logic and the
conventional CML. When the CMOS inverter is operating in
steady state, there is no direct path between power supply and
the ground. That means the inverter does not consume static
power (ignore the leakage current). But the power consumption
of the CMOS logic is product of the operation frequency and
the charging and discharging energy per unit switching. With
the increase of the operation frequency, the power consumption
of the CMOS logic also increases. In contrast, the CML
inverter have the static power consumption which is the drain
current of the current source transistor M5. Moreover the
power consumption of the CML is nearly independent of the
operation frequency. So the power consumption of the CMOS
logic may overtake that of the CML at the certain operation
frequency. In this design, by selecting the parameters
reasonably, up to 10 Gb/s, the power consumption of the
CMOS logic is still smaller than that of the CML. That is
different from the early researches. Furthermore, as shown in
Fig. 2, there are two MOSFETs in the CMOS logic inverter and  
five in the CML. Therefore, a chip area with a given function is Figure 3. Circuit schematic of a pseudo-static latch
larger in the CML than in the CMOS logic. As shown in Fig. 4b, the latch (Lat2.5G) with a
level-recovering transistor, named 4_T latch, is used in the
low-speed 2:1 MUX. When the transistor M1 transfers high
level VDD to the node B, the voltage of node B is less than
VDD-Vth. In order to solve the threshold voltage (Vth) loss
problem, a PMOS (M4) bridge connects between the inverter
input and output. While the input signal is high, the output
signal of the inverter reaches low but not ground. Even if the
output is not ground, M4 turns on and charges to Cp. So the
voltage of node B is pulled to VDD. And the latch realizes the
full swing of signal transmission. Compared with the dynamic
latch, the 4_T latch saves half of the clock spending. Because it
uses the transmission transistor instead of transmission gate
used in dynamic latch. In theory, only when the input signal is
  switching from low to high, the M4, a level-recovering device,
Figure 2. Inverter circuits of the (A) CMOS logic and (B) CML turns on. That further reduces power consumption than the
According to the analysis above, the CMOS logic is selected dynamic latch. However, limited by the rate of operation, 4_T
to design all sub-circuits of the 4:1MUX. In addition, selecting latch can only be used for the low-speed 2:1 MUX.
a reasonable topology is a serious matter in CMOS logic circuit Compared with the low-speed latch using pseudo-static
design. In Fig. 3, there is a pseudo-static latch including two CMOS logic in Fig. 3, two kinds of latch described above have
inverters and two transmission gates. Whereas, in this paper, advantages including layout area and power consumption.
latches for high-speed 2:1 MUX choose the dynamic CMOS There are eight MOSFETs in the structure shown in Fig. 3,
logic and that for low-speed 2:1 MUX choose the pseudo-static whereas each latch in Fig. 4 has only four MOSFETs. The
CMOS logic. number of transistors decides the size of the layout. So the
Fig. 4 shows circuit schematics of latches for 4:1 MUX. Fig. layout of the latches which are used in this paper would be only
4a shows the dynamic latch (Lat5G) circuit operating at 5 Gb/s. half of that of the early latch. Moreover, every MOSFET in
The latch relies on transferring input data to the node A and latches can produce the power consumption. That means the
inverting this data to the output node while the clock is high. power consumption of the latch shown in Fig. 3 is larger than
The instantaneous data in the node A is held on the parasitic that of the latches shown in Fig. 4 at the same operation
capacitances Cp when the clock is low. While the clock is low, frequency. And the latch in Fig. 3 needs two pairs of difference
the charge in the Cp loses for some reasons, such as charge clock signals, which increate the burden of the clock channel.
When the 4:1 MUX operates in the 10 Gb/s rate, the average
of dynamic current in Power supply is 29.6 mA at 1.8V. At this
supply voltage, the chip consumes 53.3 mW. Table.1
summarizes the features of the chip.

Figure 4. Circuit schematics of latches (A) 5 GHz Latch (B) 2.5GHz latch
Therefore two kinds of latch, shown in Fig. 4, are used in
high-speed and low-speed MUX respectively, which optimizes
4:1 MUX for low power consumption while achieving high
Fig. 5 shows the layout of 4:1 MUX. The chip has a size of
Figure 6. Simulated eye diagram for 10 Gb/s 4:1 MUX
0.575×0.475 mm2 and is determined by the pad frame. The core
area is only about 0.18×0.12 mm2. In post simulation, four V. CONCLUSION
pseudo-random input signals (PRBS) with a sequence length of
27-1 are provided to the MUX. The input signal voltage swing A 4:1 MUX circuit is successfully designed in 0.18 μm
is 1.8 V (from VDD to GND). The difference clock signals have CMOS process. The circuit uses the CMOS logic to multiplex
a voltage swing of 1.8 V. With PRBS data inputs applied, the four data streams to a high-speed signal. The simulation proves
10 Gb/s output eye diagram, simulated by Cadence software, is that it operates well at 10 Gb/s under normal temperature with
shown in Fig. 6. The eye diagram has 200 mV vertical eye only about 53.3 mW power consumption.
opening with random jitter of 14ps on an external 50 Ohm

Figure 7. Input and corresponding output waveforms of the 4:1 MUX

simulated at 10 Gb/s operation

Figure 5. 0.18 μm 4:1 MUX layout
Function 4:1 MUX
Four data patterns (D1: 11001000, D2: 01101001, D3:
Input bit rate 2.5 Gb/s
10000111, D4:01110001) at 2.5 Gb/s and 5 GHz difference
Output bit rate 10 Gb/s
clock signals input to 4:1 MUX. Then the corresponding output
Supply voltage 1.8 V
pattern at 10 Gb/s should be that: 1010, 1101, 0101, 0001, 1100,
Current consumption 29.6 mA
0010, 0010, 0111. Fig. 7 shows the output signal pattern
Power dissipation 53.3 mW
diagram as the result. By comparing the right data pattern and
the simulated diagram, the logic function of MUX is proved to Chip size 0.575×0.475 mm2
be correct. Technology 0.18 μm, fT = 49 GHz
multiplexer/demultiplexer ICs using current mode logic with tolerance to
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