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1 Issue 160 November 2003 CIRCUIT CELLAR® Issue 160 November 2003 1
As you can see in Timing parameter Minimum value Maximum value
how to do it.
Photo 1, there is a D
input set-up time prob- Nominal CLK frequency 25 MHz 25 MHz HOW IS IT DONE?
lem to flip-flop B. CLK to Q delay (both flip-flops) 2 ns 5 ns Timing analysis has
Clock delay 1 ns 3 ns
Sometimes, when dis- Propagation delay through logic gates 1 3 ns 15 ns
been achieved in many dif-
cussing timing issues, I Propagation delay through logic gates 2 5 ns 12 ns ferent ways over the years.
hear designers say that D input setup time to CLK (both flip-flops) 10 ns You can use anything from
timing doesn’t really D input hold time after CLK (both flip-flops) 6 ns a manual approach (i.e.,
matter because the Table 1—Here are the timing values for the circuit illustrated in Figure 1. using spreadsheets and a
processor has a memory drawing program or just
controller with variable pen and paper) to what I
timing. This may be true, but it usual- Handbook of Black Magic). refer to as semimanual CAD pro-
ly means that the processor allows for Obviously, this is not a good situa- grams. You can also use fully auto-
a programmable number of wait tion, because the output of the flip- matic static and dynamic timing-
states. If you add another wait state flop may be wrong, and it may take analysis tools.
(i.e., one more clock cycle before longer than the normal propagation I am visually oriented like most
clocking in the data), then the prob- delay to get to the wrong value. engineers, so I prefer to draw my timing
lem in Photo 1 will go away. But what Knowing that you have a problem is diagrams. For the first board I devel-
if you don’t want the performance hit the first step. So, how can you fix it? oped, I used my schematic drawing
of adding a wait state, or what if the There are many ways to solve timing tool to draw the timing waveforms. For
processor doesn’t allow wait states? problems. In this simplified circuit, you the signal timing, I put on the dia-
You would have to solve the timing are off by 1 ns. You can change either gram the minimum and maximum
problem. logic gates 1 or 2 so that they are faster timing for every signal edge. Each
Another case involves hold prob- parts. Another option is to select a flip- time I changed the components in a
lems. Adding wait states often cannot flop that has a smaller set-up and hold signal path, I updated the numbers on
solve this, because the timing chain window. Timing analysis doesn’t fix the drawing. The next possible step in
for the D input is tied to the current the problem; it just tells you that there the evolution of timing analysis
clock edge not to the delays from the is a problem. Remember, when you would be to put the timing numbers
previous clock edge. In such a case, make a change to your circuit, rerun in a spreadsheet and let the spread-
you need to make some changes to the timing analysis to make sure that sheet do the calculations.
the design to make the timing work. the problem is fixed and that another Table 2 shows the original simpli-
Okay, so you agree that there is a one hasn’t been created. Hopefully, I fied circuit analyzed in a spreadsheet
problem. So what? What will happen have convinced you that timing analy- format. For the set-up time calcula-
if you don’t fix it? There are three sis is important. Now I’ll show you tion, use the maximum data delay and
possibilities for set-up and hold times
(see Figure 2).
As you can see in Figure 2a, the sig-
nal of interest can meet the timing
with proper set-up and hold times.
The next possibility is that the signal
may miss it completely and get
caught on the next clock edge (see
Figure 2b). (Note that this can be a
problem if you don’t want the per-
formance penalty.)
The last possibility is that the input
signal changes inside of the set-up and
hold window (see Figure 2c). What
happens in this case? The output of
the flip-flop can become metastable,
which means that the output can
oscillate from zero to one or from one
to zero a few times (or many times)
before it stabilizes to a zero or one.
The resulting state is random. (For
more information on metastability,
refer to H. Johnson and M. Graham’s Photo 1—I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray
book, High-Speed Digital Design: A areas on the waveform denote regions of uncertainty. The red areas show a timing violation.
A PROBLEM SOLVED
At a former employer of mine, we
had a problem with a card we were
working on. We couldn’t write to some
of the address space in one of our
ASICs on a new spin of the card. So,
Photo 2—Note the width of the Board Clkout signal. This is the result of it being an ordinary buffer that is heavily
loaded on the board. Again, red indicates a timing violation. after playing with the software to make
sure that it was not the cause of the
problem, we hooked up the logic ana-
An interface is any part of the design AUTOMATIC CAD TOOLS lyzer to see what was going on. At first
that interacts with another part, such ASIC designers have been using stat- glance, the timing looked fine, and we
as a write cycle from a microprocessor ic timing analysis tools for a long time. scratched our heads. But just before we
to a memory and a connection to a PCI Synopsys’s Primetime is an example. went home late that evening, one of
bus. These interface specifications The tools go through the entire design the ASIC designers said that he found
form the basis for subsequent design and determine if there are any timing it funny that the first write cycle that
decisions; they may give the designers violations (with some constraints from had worked was the only one that
an early indication as to whether the the user to minimize false paths). There worked. It would have been nicer if he
design is feasible, impossible, or sheer are static timing analysis tools for had mentioned that earlier!
lunacy. For instance, if the interface board-level design, as well (e.g., BLAST, When we returned to the lab the
specifications dictate that you will which was developed by Innoveda). next day, we concentrated on looking
have to use a 34-ps SRAM, you’ll These tools generally cost significantly at the second and subsequent write
probably try to get on another design more than Timing Diagrammer Pro cycles. One of the control signals to
project! and Timing Designer. the ASIC was rising at the same time
As the design progresses, put real tim- What if a tool shows that you are in as the clock. Our hypothesis was that
ing numbers into Timing Diagrammer error? Is this always true? You may say the timing wasn’t OK.
Pro, which will immediately tell you that timing analysis is too pessimistic We decided to try moving the clock
if the constraints are still met. At and, at times, you may be right. For signal in time by delaying the clock.
some point, there may be more than instance, if the elements in the simpli- We initially did this by adding a long
one option. Using this tool, you can fied circuit depicted in Figure 1 are in wire to the clock signal. As a result,
model each of the possible solutions one FPGA, it is less likely that the the write cycle worked! Well, it most-
to determine if they work. If they do
not work, then redesign, whether that
means simply changing to a faster
component or a completely new cir-
cuit. An alternative might be to
change the original requirements,
assuming that your customer allows
you to do so. Don’t count on it!
When it comes time to review your
design prior to building your PCB, for
instance, if the Timing Diagrammer
Pro files are up to date, you have proof
that your design will meet the timing
requirements. Note that if your circuit
has critical timing paths, you may
want to include PCB delays in the
timing analysis as well. Photo 3—I used a zero-delay clock driver. The area of uncertainty on this clock is significantly less than the Board
Clkout signal in Photo 2. Notice the lack of red this time. It works!