Basics of Packet Switching

1
Outline

„ Introduction to Packet Switching

„ Fundamental Switching Concepts
„ Switch Fabric Classification
„ Buffering Strategy in Crossbar-based
Switching

2
 Introduction

Where is the switching fabric? Router Management

Controller Controller

Line Card 1 CPU Memory Memory

Transponder/
Framer Network Traffic
Transceiver
Processor Manager

Switch
Fabric

Line Card CPU Memory Memory

N
Transponder/ Network
Framer Traffic
Transceiver Processor Manager
3
 Introduction - IP routers

Forwarding= Routing + Switching Router Management

Controller Controller

Line Card 1 CPU Memory Memory

Transponder/
Framer Network Traffic
Transceiver
Processor Manager

Switch
Fabric

Line Card CPU Memory Memory

N
Transponder/ Network
Framer Traffic
Transceiver Processor Manager
4
Introduction

„ Traditional telephony networks

„ use circuit switching techniques to
establish connections.
„ in the circuit switching scheme, there is
usually a centralized processor
„ determines all the connections between input
and output ports.

5
 Introduction

„ For IP Routers
„ Use packet switching. Time for each switching is much shorter
OC192 OC768 OC3072
Line rate 10Gbps 40Gbps 160Gbps

One time slot 32ns 8ns 2ns

(packet size: 40 bytes)
„ Each router consists of multiple input/output ports
„ Packets from different places arrive at the input ports of the

IP router
„ They are delivered to appropriate output ports by a switch

fabric according to a forwarding table, which is updated by

routing protocols

6
Introduction

„ Main research issues in packet switching

„ Switching fabric. Physical path to deliver packets
from input sides to output sides
„ Different kinds of switch fabrics (Switching Fabric Design)
„ Contention resolution. In the packet switch
network, packets from various input ports may
destine for the same output port simultaneously,
resulting in output port contention.
„ How to buffer the contented packets. (Buffering Strategy)
„ How to arbitrate and schedule packets when contention
arises. (Scheduling Algorithm)

7
Outline
„ Introduction to Packet Switching
„ Fundamental Switching Concepts
„ Switching and Routing
„ Unicast and Multicast
„ Throughput and Speedup
„ Non-blocking and Output Contention
„ Cell-mode Switching and Packet-mode Switching
„ Switch Fabric Classification
„ Buffering Strategy in Crossbar-based
Switching

8
Fundamental Switching Concept

„ Switching and Routing

„ Both try to transfer information from one
part to another.
„ Switching
„ The information exchanged within a network
node.
„ only a function of a single device, and is based
on a forwarding table, switching architectures,
and scheduling algorithms.

9
Fundamental Switching Concept
„ Typical switching example

10
Fundamental Switching Concept

„ Routing
„ Represents a large-scale perspective, where
information is exchanged between two nodes
that can be separated by a large distance in the
network.
„ Needs the cooperation of other network nodes,
and is based on a routing protocol.

11
Fundamental Switching Concept
„ Typical routing example

12
Fundamental Switching Concept

„ Unicast and Multicast

„ Unicast
„ Traffic that enters an input port of a switch
fabric is only destined for an output port.
„ Multicast
„ Copy data from one input port to multiple
output ports.

13
Fundamental Switching Concept

„ Unicast and Multicast in switching fabric

14
Fundamental Switching Concept

„ Throughput and Speedup

„ Throughput
„ the ratio of the average aggregated output rate to the
average aggregated input rate when all the input ports
carry 100% traffic at line rate.
„ a positive value no more than one.
„ Speedup
„ A speedup of k means that the internal forwarding rate
of the switch fabric is k times the input line rate.
„ when a speedup exceeds one, buffers must be used at
output ports.
„ allows one switch fabric to forward more than one
packet at the same time to the output port to alleviate
output contention, resulting in a higher throughput.
15
Fundamental Switching Concept

„ Blocking and Output Contention

„ Non-blocking
„ when there is a request generated between an
idle input port and an idle output port, a
connection can always be set up.
„ an idle port refers to a port not connected nor
requested.
„ Blocking
„ it is possible that no connection can be set up
between the idle input/output pair.

16
Fundamental Switching Concept
10 0
1 0 0 0 0 0 0
0 1
1 0 0 0 0 0 0 0
„ Internal blocking in a Clos network (5 to 3)
0 0 0 0 1 0 0 0 0
0 0 0 11 0 0 0 0 0
0 011 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 1

17
Fundamental Switching Concept
„ An N x N crossbar switch
consists of a 2-dimensional
array of N2 cross-points,
one corresponding to each
input-output pair.

Cross state Bar state

„ Each cross-point has two

possible states: cross
(default) and bar. A
connection between input
port i and output port j is
established by setting the
(i, j)th cross-point switch to
the bar state while letting
other cross-points along the
connection remain in the
cross state

18
Fundamental Switching Concept

„ Output Contention
„ is due to the nature of bursty IP traffic, but not
the design of switch architecture.
„ if more than one input port requests the same
output port, only one can be granted, so the
others have to wait.
„ the output contention resolution greatly affects
the overall utilization of the switching fabric.

19
Fundamental Switching Concept
„ Output port contention

20
Fundamental Switching Concept
„ Cell-mode Switching and Packet-mode Switching
„ Cell-mode Switching
„ in ATM networks, information is packed into fixed-size cells.
„ in an ATM switch, scheduling takes place per cell time, which is
called the time slot.
„ But in IP networks, variable-length packets are adopted

21
 Fundamental Switching Concept

„ Cell-mode switching in IP routers

„ An input queueing cell switch with segmentation and
reassembly
required in each output port to
The cells are buffered in the cell queues (CQs), reassemble cells of the same
e.g., virtual output queues (VOQs), each packet together.
associated with each output.

used to buffer the reassembled

In each input port, an input segmentation
packets when the ORM has a
module (ISM) is employed to convert the
speedup.
variable-size IP packet into several fixed-size
cells.
22
Fundamental Switching Concept

„ Packet-mode Switching
„ A packet is divided into fixed-size cells like in
cell-mode , but cells of the same packet are
scheduled contiguously, not independently.
„ Advantage
„ Both the scheduling of cells and the reassembly of
packets become much easier.
„ It benefits from lower average packet delay towards
cell-mode scheduling when the variance of packet
length distribution is small.

23
Outline

„ Introduction to Packet Switching

„ Fundamental Switching Concepts
„ Switch Fabric Classification
„ Time-Division Switching
„ Space-Division Switching
„ Buffering Strategy in Crossbar-based
Switching

24
 Switch Fabric Classification
„ Classification of switching architecture
„ The switch fabrics can be classified based on their switching

techniques into two groups: time-division switching (TDS)

and space-division switching (SDS).

Packet Switches

Time Division Space Division

Shared Shared
Single Path Multipath
Medium Memory

Crossbar Fully Banyan Augmented Clos Multiplane Recirculation

Interconnected Banyan

25
Switch Fabric Classification

„ Time-Division Switching
„ Advantage
„ Since every cell flows across the single
communication structure, it can be easily
extended to support multicast/broadcast
operations.
„ Disadvantage
„ Limited by the internal communication
bandwidth that should reach the aggregated
forwarding bandwidth of all the input ports.

26
 Switch Fabric Classification

„ Shared-medium switching architecture

Cells arriving at input ports are time-
division multiplexed into a common
high-speed medium, such as a bus or
a ring, of bandwidth equal to N times
the input line rate.
Examines the header of each
incoming cell and then accepts
only the cells destined for itself.
Due to the separate FIFO buffer in
each output port, the memory
utilization of shared-medium switch
is lower than the shared-memory
structure.

27
Switch Fabric Classification
„ Besides the bandwidth of shared medium,
the switch size is also limited by the
memory read/write access time, within
which N incoming and 1 outgoing cells in a
time slot need to be accessed.
„ Suppose
„ the time for a cell slot is Tcell
„ the memory access time slot is Tmem
„ the number of switch size N can be calculated
using the following equation:
Tcell
(N+1) ≤
Tmem
28
Switch Fabric Classification
„ The shared-memory structure
A memory unit is used to store
cells from all input ports.
The memory contains N logical
queues, one per output port,
and each queue stores the cells
destined for the corresponding
output.
29
 Switch Fabric Classification
„ Shared-memory switch
„ Compare with shared-medium switches
„ Same
„ Cells from all the input ports are time-division
multiplexed into a cell stream
„ Difference
„ They are not forwarded immediately and flood to all
the outputs.
„ Instead, cells are buffered in a central memory, and
then scheduled to the de-multiplexer, where cells
destined for different output ports are separated.

30
Switch Fabric Classification

„ Shared-memory switch
„ Advantage
„ The memory is shared by all the output ports
and the utilization of memory is maximized.
„ Disadvantage
„ In each time slot the memory must
accommodate N concurrent write accesses and
N concurrent read accesses, which limits the
switch to a small size.

31
Switch Fabric Classification
„ Space-Division Switching
„ One or multiple data paths is available between
the input and the output ports.
„ Cells of the different input-output connections can
be forwarded concurrently, when no blocking is
present.
„ Total switching capacity is then the product of the
bandwidth of each path and the number of paths
that can transmit cells simultaneously.
„ The SDS switches are classified based on the
number of available paths between any input-
output pair.
„ Single-path switches
„ Multiple-path switches

32
Switch Fabric Classification –
Single-path switches
„ Only one path exists for any input-output
pair.
„ Has simpler routing control.
„ Classified into
„ crossbar-based switches.
„ fully interconnected switches.
„ banyan-based switches.

33
 Switch Fabric Classification –
Single-path switches
„ Crossbar Switch Basically, an N x N crossbar switch
consists of a 2-dimensional array

A 4x4 crossbar switch

of N cross-points, one
2

„ corresponding to each input-

output pair.

Each cross-point has two

possible states: cross (default)
and bar. A connection
between input port i and
output port j is established by
setting the (i, j)th cross-point
switch to the bar state while
letting other cross-points
along the connection remain
in the cross state.

Cross state Bar state

34
Switch Fabric Classification –
Single-path switches
„ The self-routing property
„ The bar state of a cross-point can be triggered
individually by each incoming cell when its
destination matches with the output address.
„ No global information about other cells and their
destinations is required.
„ The control complexity is significantly reduced in the
switching fabric as the control function is distributed
among all cross-points.
„ The crossbar switch allows the transferring
of up to N cells with different input ports
and different outputs in the same time slot.

35
Switch Fabric Classification –
Single-path switches

„ Crossbar switches have two attractive

properties:
„ internally non-blocking.
„ simple in architecture.
„ If constructing larger multistage switches
with small crossbar switch modules, the
complexity can be improved to O (NlogN).

36
Switch Fabric Classification –
Single-path switches

„ There are three possible locations for the

buffers in a crossbar switch:
„ at the crosspoints in the switch fabric
„ at the inputs of the switch
„ at the inputs and outputs of the switch.

37
Switch Fabric Classification –
Single-path switches

„ A fully interconnected switch

38
Switch Fabric Classification –
Single-path switches
„ Fully interconnected switches
„ The complete connectivity between inputs
and outputs is usually accomplished by
means of N separate broadcast buses from
every input port to all output ports
„ N separate buffers are required in such a
switch, one at each output port.

39
Switch Fabric Classification –
Single-path switches
„ Operates in a similar manner to the shared
medium switch. A cell from any input port is
broadcast to every output port.
„ The difference is that multiple cells from
several input ports can be simultaneously
broadcasted to every output ports.
„ Therefore, separate cell filters and dedicated
buffers, one for each output port, are
required to filter out the mis-delivered cells
and to temporarily store the properly
destined cells.
40
Switch Fabric Classification –
Single-path switches

„ Advantage
„ Its simple and nonblocking structure, similar to
the crossbar-based switch.
„ Disadvantage
„ Space overhead requirement of the total
separate N 2 broadcast buses.

41
Switch Fabric Classification –
Single-path switches
„ Three different topologies of banyan-
based switches

42
Switch Fabric Classification –
Single-path switches

„ Banyan-based Switches
„ single-path space-division switches.
„ self-routing switch constructed from 2 x 2
switching elements with a single path
between any input-output pair.
„ there are three isomorphic topologies:
delta, omega, and banyan networks,
belonging to banyan-based family.
„ All of them offer an equivalent performance.

43
 Switch Fabric Classification –
Single-path switches
„ Banyan switching structure

Example: 0
000
A cell in input port 1 destined 001
for output port 2, ('010') is
1
rounded to the top link (0) of
the 1st switch element, to the 0
010
down link (1) of the 2nd 011
switch element, and to the
top link (0) of the third switch
element. 100
101

110
111

44
Switch Fabric Classification –
Single-path switches

„ Banyan-based Switches
„ An NxN banyan network consists of log2N stages
of 2x2 switching elements.
„ Each stage has multiple 2 x 2 switching elements
whose inputs and outputs are labeled 0 and 1.
„ The inter-stage connection patterns are such that
only one path exists between any input of the first
stage and any output of the last stage.

45
Switch Fabric Classification –
Single-path switches
„ The banyan network has self-routing
capability.
„ When a cell enters in one of the input ports, it
uses the output address as the routing
information when traversing all the stages.
„ Advantage
„ It has fewer switch elements than the crossbar-
based and the fully interconnected switch,
O(NlogN) vs. O(N 2).
„ Self-routing property is also an attractive
feature in that no control mechanism is needed
for routing cells.
„ Disadvantage
„ It is an internally blocking switch. 46
Switch Fabric Classification –
Multiple-path switches

„ Multiple-path space-division switches

47
Switch Fabric Classification –
Multiple-path switches
„ More than one path exists for any input-
output pair.
„ Has better connection flexibility and fault
tolerance.
„ classified as
„ Augmented banyan switches
„ Clos switches
„ Multi-plane switches
„ Recirculation switches.

48
Switch Fabric Classification –
Multiple-path switches

„ Augmented Banyan Switches

„ refers to the banyan switch that has more
stages than the regular banyan switch.
„ deflected cells are provided more chances
to be routed to their destinations again by
using later augmented stages.
„ when the deflected cells do not reach their
destinations after the last stage, they will
be discarded.

49
 Switch Fabric Classification –
Multiple-path switches

Connection from input 1 to output 3 is blocked

000 000
001 001
010 010
011 011

100 100
101 101

110 110
111 111

50
 Switch Fabric Classification –
Multiple-path switches

Connection from input 1 to output 3 is not blocked

000 000
001 001

010 010
011 011

100 100
101 101

110 110
111 111

51
Switch Fabric Classification –
Multiple-path switches
„ Advantage
„ By adding augmented stages, the cell loss rate is reduced.

„ The performance of the switch is improved.

„ Disadvantage
„ Its complicated routing scheme. Cells are examined at every

augmented stage to determine whether they have arrived at

their requested output ports.
„ If so, they will be sent to the output interface module.

Otherwise, they are routed to the next stage and will be

examined again.
„ The number of augmented stages needs to be sufficiently large

to satisfy desired performance.

„ Adding each augmented stage to the switch causes increased

hardware complexity.

52
Switch Fabric Classification –
Multiple-path switches

„ Three-Stage Clos Switches

„ consists of three stages of switch modules:
„ The first stage is used to distribute traffic.
„ In the middle stage, several parallel switch
modules are built to provide multiple paths
through the switches.
„ In the third stage cells from different switch
modules of the middle stage are switched to
the correct output ports.

53
Switch Fabric Classification –
Multiple-path switches
„ Three-Stage Clos Switches

...

...
...

...
...

...
54
 Switch Fabric Classification –
Multiple-path switches
„ Example of internal blocking in a three-
stage Clos switch

It can be seen that

input port 9 cannot be
connected to either
output port 4 or 6, x
even though both of x x
these output lines are
idle.
55
Switch Fabric Classification –
Multiple-path switches

„ Three-Stage Clos Switches

„ By rearranging the existing connections,
the new connection request can be
accommodated. Thus, the Clos network is
rearrangably nonblocking.
„ By increasing the value of m (the number
of middle-stage switch modules), the
probability of blocking is reduced.
„ To find the value of m needed for a strictly
nonblocking three-stage switch, let us refer
to next slide.
56
 Switch Fabric Classification –
Multiple-path switches
„ Nonblocking condition for a three-stage
Clos switch

We wish to establish a path from

input port a to output port b.

57
Switch Fabric Classification –
Multiple-path switches
„ Three-Stage Clos Switches
„ Worst case situation for blocking occurs if all of
the remaining n - 1 input lines and n - 1 output
lines are busy and are connected to different
middle-stage switch modules.
„ Thus a total of (n - 1) + (n - 1) = 2n – 2
middle-stage switch modules are unavailable
for creating a path from a to b.
„ However, if one more middle-stage switch
module exists, an appropriate link must be
available for the connection.
„ Thus, a three-stage Clos switch will be
nonblocking if m ≥ (2n − 2) + 1 = 2n − 1 .
58
 Switch Fabric Classification –
Multiple-path switches

„ How many crosspoints in a three-stage Clos

switch when it is symmetric (i.e., m = k)?

For large switch size,

59
Switch Fabric Classification –
Multiple-path switches

„ Differentiate Nx with respect to n and set the

result to 0
2
⎛N⎞
N x' = 4 N − 2 ⎜ ⎟ = 0
⎝n⎠

„ Substituting into Nx

60
Switch Fabric Classification –
Multiple-path switches
„ Three-Stage Clos Switches
„ Advantage
„ Reduces the hardware complexity from O( N 2) 3in
the case of the crossbar-based switch to O( N 2 )
while the switch could be designed to be
nonblocking.
„ Provides more reliability since there is more
than one possible path through the switch to
connect any input port to any output port.
„ Disadvantage
„ Some fast and intelligent mechanism is needed
to rearrange the connections in every time slot
so that internal blocking can be avoided.
61
Outline
„ Introduction to Packet Switching
„ Fundamental Switching Concepts
„ Switch Fabric Classification
„ Buffering Strategy in Crossbar-based Switching
„ Output Queueing (OQ)

„ Input Queueing (IQ)

„ Virtual Output Queueing (VOQ)

„ Combined Input and Output Queueing

„ Crosspoint Queueing

62
Buffering Strategy in Crossbar-
based Switching
„ Since the burst arrival of traffic are likely to contend for
the output ports and/or internal links, buffers are
required to temporarily store cells that lose the
contention.

„ Various buffering strategies:

„ Output Queueing (OQ)

„ Input Queueing (IQ)

„ Virtual Output Queueing (VOQ)

„ Combined Input and Output Queueing

„ Crosspoint Queueing

63
Buffering Strategy in Crossbar-
based Switching
„ The output queueing structure

64
Buffering Strategy in Crossbar-
based Switching
„ Characteristics of output queueing structure
„ All arriving packets can be transferred to output port immediately
„ Since only one packet can be transmitted via the output link at a
time, the remaining packets are queued at the output port.
„ Scheduling is needed at the output of output queues.

„ Advantage
„ OQ switch is working conserving: an output line is always busy
when this is a packet destined to it.
„ Highest throughput, lowest average latency
„ Disadvantage
„ Suffers from memory speed constraint and thus switch size
limitation.
„ Memory must run at the speed of N+1 times of the line rate (N times
writes, and once reads)
„ As the line speed or the switch port number increases, this scheme
becomes practically impossible to implement.

65
Buffering Strategy in Crossbar-
based Switching
„ Scheduling algorithms in OQ Switch
„ The purpose of the scheduling algorithms is to guarantee
the fairness among flows, and control the
throughput/latency of flows
„ Some typical OQ scheduling algorithm (already learned in
last week)
„ FIFO
„ Weighted Round Robin
„ Max-Min Fairness
„ GPS (Generalized Processor Sharing)
„ PGPS (Weighted Fair Queuing)
„ DRR (Deficit Round Robin)
„ Self-Clocked Fair Queuing (SCFQ)
„ Worst-Case Fair Weighted Fair Queuing (WF2Q)
„ …

66
Buffering Strategy in Crossbar-
based Switching
„ Example (memory bandwidth)
„ Assume we have an 8x8 OQ switch.
„ We use DDR SDRAM to store the packets.
„ The frequency of system clock is 200MHz, so the frequency of
data rate is 400MHz.
„ The data bus width of SDRAM is 64bit.
„ The peak throughput of the SDRAM is 25.6Gbps
„ In OQ switch, the memory must run at 9 times as fast as
line rate, so the maximum line rate supported in this OQ
switch is 2.8 Gbps
„ If the port number increases, the maximum line rate
supported will decrease.

67
Buffering Strategy in Crossbar-
based Switching
„ The input queueing structure

Head of Line
Blocking!

Scheduler 68
Buffering Strategy in Crossbar-
based Switching

IQ switch with
HoL blocking
OQ switch

69
2 − 2 ≈ 58%
 Buffering Strategy in Crossbar-
based Switching

The input queue is divided VOQs

into N logical queues,
Called VOQ (virtual Output Queue),
storing the Scheduler
cells destined for the
associated output port. 70
Buffering Strategy in Crossbar-
based Switching
„ Characteristics of Input Queueing with VOQ (Virtual Output
Queue)
„ In each time slot, only one packet is allowed to go to a certain
output port.
„ A scheduling scheme at the crossbar is required to arbitrate the
packets that are destined for the same output port.
„ Packets that lose contention have to wait at input queue
„ At the output side, no scheduling is needed

„ Advantage
„ Much more scalable than OQ: memory only need to run as twice
fast as the line rate (once read, once write) regardless of the
switch size
„ Eliminate HOL blocking.
„ Disadvantage
„ Since the logical queue number is N times the input queueing
structure, scheduling algorithm is much more sophisticated.
71
Buffering Strategy in Crossbar-
based Switching
„ Example (memory bandwidth)
„ Assume we have an 8x8 IQ switch.
„ We use DDR SDRAM to store the packets.
„ The frequency of system clock is 200MHz, so the frequency of
data rate is 400MHz.
„ The data bus width of SDRAM is 64bit.
„ The peak throughput of the SDRAM is 25.6Gbps
„ In IQ switch, the memory must run as twice fast as line
rate, so the maximum line rate supported in this IQ switch is
12.8 Gbps (2.8 Gbps for OQ switch)
„ With the increasing of port number, the maximum line rate
supported will not change

72
Buffering Strategy in Crossbar-
based Switching

VOQs Departing
First
SecondSwitching
Scheduling
Switching
Scheduling
Arriving
Scheduler
73
Buffering Strategy in Crossbar-
based Switching
„ What do we need in a switch with speedup between
1 and N
„ Input Queues
„ Output Queues
„ Schedulers at both crossbar and output side

„ Advantage
„ A tradeoff between complexity and performance
„ High performance can be easily achieved by simple
scheduling algorithm
„ Disadvantage
„ Memory must run at the speed of S+1 times of the line rate
(S is the speedup)

74
 Buffering Strategy in Crossbar-
based Switching

„ Example (memory bandwidth)

„ Assume we have an 8x8 CIOQ switch with speedup of
2
„ We use DDR SDRAM to store the packets.
„ The frequency of system clock is 200MHz, so the
frequency of data rate is 400MHz.
„ The data bus width of SDRAM is 64bit.
„ The peak throughput of the SDRAM is 25.6Gbps
„ In this CIOQ switch, the memory must run as thrice
fast as line rate, so the maximum line rate supported
is 8.53 Gbps (2.8 Gbps for OQ switch, 12.8 Gbps for
IQ switch)
„ With the increasing of port number, the maximum
line rate supported will not change
75
Buffering Strategy in Crossbar-
based Switching
„ The crosspoint buffered crossbar
structure A buffer can be placed at
each cross-point.
Incoming cells are first
placed in the
corresponding crosspoint
buffer (XB), waiting to be
transmitted to the output
ports.

An arbitrator of each output

selects a cell among the XBs on
the same column based on
some scheduling scheme, e.g.,
round-robin.

76
Buffering Strategy in Crossbar-
based Switching

„ Advantage
„ Achieve the same performance as the OQ
switches because of no HOL blocking.
„ Disadvantage
„ Since there are N 2 discrete buffers, the sharing
effect is very poor.
„ With limited chip space, only a few cells can be
implemented.
„ As a result, this switch usually combines VOQs at
each input.

77