Home Work-2

CSE211-computer architecture

SUBMITTED TO
MISS.pradeep kaur
LEC IN CSE/IT
LPU

SUBMITTED BY
Kartik sharma
ROLL NO-29
REG-3470070140
Q1. How many clock cycles are needed to execute
(a) LDA and STA
(b) BUN and BSA
(c) AND and ADD
Ans1-

LDA stands for load to accumulator .

D2T4: DR M[AR]
D2T5: AC DR, SC 0

STA stands for store accumulator .

D3T4: M[AR]  AC, SC 0

BUN stands for branch unconditionally.

D4T4: PC AR, SC 0

BSA stands for branch and save return address.

D5T4: M[AR]  PC, AR AR + 1
D5T5: PC AR, SC0

(3) AND
D0T4: DR M[AR]
D0T5: AC AC ^DR, SC 0

ADD
D1T4: DRM[AR]
D1T5: ACAC + DR,ECout,SC0
Q2. Fetching and decoding of any instruction takes three clock
cycles. How?

Ans-2 FETCH & DECODE

microoperations for the fetch and decode phases can be specified by the
following register transfer statements.
T0: ARPC
T1: IRM[AR] ; PCPC+1
T3 : D0 ,…,D7 Decode IR(12-14) ,ARIR(0-11) ,IIR(15)

Q3. Draw timing diagram for D3T4: SC ← 0

Ans-3
Q4. How is I bit useful in determining the type of instruction?

Ans-4 The utility of I bit in determining the type of instruction.

MEMORY REFERENCE INSTRCUCTION

1- D'7I'T3: Nothing
When a memory-reference instruction with I = 0 is encountered, it is not
necessary to do anything since the effective address is already in AR.It tells that it
is in direct addressing mode.
2- D'7'I T3: AR M[AR]
When a memory-reference instruction with I = 1 is encountered, it is
necessary to read the effective address from memory.
REGISRTER REFERENCE INSTRCUCTION

Register-reference instructions are recognized by the control when D7 = 1

and I = 0.
D7I’T3: Execute a register-reference instruction.
INPUT/OUTPUT REFERENCE INSTRUCTION
Input—output instructions have an operation code 1111 and are recognized
by the control when D7 = 1 and I= 1.
D7IT3: Execute an input-output instruction.

Q5. (a) How are data, address and control buses involved in data
transfer to and from memory? Consider a computer system with
16 registers of 32 bit each and RAM of 1GB. Calculate the size of
data bus and address bus required for the same.
(b) Find out register size of registers in Pentium Processor.
Ans-5
A)MEMORY TRANSFER
The memory bus is the set of wires that is used to carry memory addresses and data to
and from the system RAM. The memory bus in most PCs is also shared with the
processor bus, connecting the system memory to the processor and the system chipset.
B) Most high performance 32-bit and 64-bit processors (some notable exceptions are
most ARM and 32-bit MIPS CPUs) have integrated floating point hardware, which is
often, but not always, based on 64-bit units of data.

Q6. Demonstrate the execution of interrupt cycle with the help of

an example.
Ans-6
INTERRUPT CYCLE
The interrupt cycle is a hardware implementation of a branch and save
return address operation. The return address available in PC is stored in a
specific location where it can be found later when the program returns to
the instruction at which it was interrupted. This location may be:
a) Processor.
b) Register.
c) A memory stack.
d) A specific memory location.

An example
_ This example shows what happens during the interrupt cycle.
_ Suppose that an interrupt occurs and R is set to 1 while the control is
executing the instruction at address 255.
_ At this time, the return address 256 is in PC. The programmer has previously
placed an input—output service program in memory starting from address
1120 and a BUN 1120 instruction at address 1……
_ When control reaches timing signal T0 and finds that R = 1, it proceeds with
the interrupt cycle. The content of PC (256) is stored in memory location 0,
PC is set to 1, and R is cleared to 0. At the beginning of the next instruction
cycle, the instruction that is read from memory is in address 1 since this is
the content of PC.
_ The branch instruction at address 1 causes the program to transfer to the
input-output service program at address 1120.