PROBLEM:-Diagram and Function table for RAM and ROM chips and

connect the memory to cpu

Q) a) Draw the block diagram of function table for 128x8 RAM chips and 512x8
ROM chips?
b) A computer uses RAM chips of 1024x1 capacity.
i) How many chips are needed and how should their address lines be
connected to provide a memory capacity of 1024 bytes?
ii) How many chips are needed to provide a memory capacity of 16K bytes.

SOLUTION:

RAM:
1. A RAM chip better suited for communication with the cpu. If it has one or
more control inputs that selected chip only when needed.
2. Another common feature is a bidirectional databus. That allows the transefer
of data either from memory to cpu during a read operation or from cpu to
memory during a write operation.

The block diagram of the RAM chip whose capacity of the memory is
128 words of 8bits per word is as follows.

Chipselect1 CS1

Chipselect2 CS2

Read RD 128X8
RAM
Write WR

7-bits AD7 8-bit data bus

Address

FUNCTION TABLE:

CS1 CS2 RD WR MEMORY FUNCTION STATE OF DATABUS

0 0 X X Inhibit High impedence
0 1 X X Inhibit High impedence
1 0 0 0 Inhibit High impedence
1 0 0 1 Write Input data into RAM
1 0 1 X Read Output datafrom ROM
1 1 X X Inhibit High impedence
ROM:-

• A ROM chip organized in a similar manner of RAMchip.

• Since a ROM can only read the data hence databus can only be in an output
mode.

THE BLOCK DIAGRAM OF 512X8 ROM CHIP IS AS FOLLOWS:

Chipselect1 CS1

Chipselect2 CS2 512X8

ROM
8-bit
databus
Read RD

9-bit
Address AD9

FUNCTIONTABLE:-

CS1 CS2 RD Memory function State of databus

0 0 X Inhibit High impedence
0 1 X Inhibit High impedence
1 0 0 Inhibit High impedence
1 0 1 Read Output data from ROM
1 1 x Inhibit High impedence

b).1). Given ram chip capacity=1024x1 bits

Required memory capacity=1024 bytes
Number of 1024x1 RAM chips neede to provide
Memory capacity 1024x8 bits=(1024x8)/(1024x1)=8 chips
Number of RAM chips needed=8 chips
 The following figure shows how these RAM chips address lines are connected to CPU

CPU
Address bus RD WR Data bus
16 15 14 13 12 11 10-1

Cs1
Cs1
Cs2
3x8 Decoder Cs2
Rd
Rd 1024X1
Wr
Wr RAM
76543210 Ad10
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024X1
Wr RAM
Ad10

Cs1
Cs2
Rd 1024x1
Wr RAM
Ad10
 Memory address map for the above circuit:
Component Hexadecimal Address bus
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RAM1 0000-03FF 0 0 0 0 0 0 X X X X X X X X X X
(0-1023)
RAM2 0400-07FF 0 0 0 0 0 1 X X X X X X X X X X
(1024-2047)
RAM3 0800-0BFF 0 0 0 0 1 0 X X X X X X X X X X
(2048-3071)
RAM4 0C00-0FFF 0 0 0 0 1 1 X X X X X X X X X X
(3072-4095)
RAM5 1000-13FF 0 0 0 1 0 0 X X X X X X X X X X
(4096-5119)
RAM6 1400-17FF 0 0 0 1 0 1 X X X X X X X X X X
(5120-6143)
RAM7 1800-1BFF 0 0 0 1 1 0 X X X X X X X X X X
(6144-7167)
RAM8 1C00-1FFF 0 0 0 1 1 1 X X X X X X X X X X
(7168-8191)

b)
ii) Given RAM chip capacity =1024x1 bits
required memory =16bytes.
Number of 1024x1 RAM chip needed to provide memory capacity of 16x1024c bits
=(16x1024x8)/(1024x1)
= 128 chips
Number of RAM chips required = 128 chips