A 2.

4 GHz fully integrated CMOS LC V CO

Hao Shi·, Guoyan Zhang , Yangyuan Wang

Institute of Microelectronics, Peking University, Beijing 100871, China

*Email: shihao(alirne.pku.edu.cn

Abstract GHz, low phase noise 'and low power

consumption become the major concerns. To

A fully i n tegr ated 2.4 GHz CMOS LC meet this requirement, LC tank voltage

VCO is designed and fabricated in 0.35 um controlled oscillators are a b etter choice th an

BiCMOS process us ing PN varactor and planar relaxation oscillator or ring oscillator for the

modern telecommunication standard.

,

spiral inductor. Trade offs for LC tank design as

Ilell as symmetry design considerations from In this paper, the design of a full\'

schematic level to layout are presented. The integrated 2.4 GHz CMOS LC VCO is presen ted.

VCO achieves a measured phase noise of -90 The trade offs for the LC tank design [Ire

dBClHz at 100 KHz oflset and - 1 16 dBClHz at discussed. Symmetry designs for the VCO to

2 lv!I'Iz o ffset . The measured output frequency is reduce phase noise are presented. Measurement

li'om 2.2045 GHz to 2.4970 GHz, which considerations for the VCO on a FR-4 PCB tes t

corresponds to 290 MHz tunin g range obtained fixture are also shown.

bl qnl�' tuning the PN varactor pairs. The VCO LC tank' Active device
.--------------1
core draws 4 mA of current from the 3.3 V
I
supply. The whole measurement is accomplished I
I
I
by u sing a FR-4 PCB test fixture. I
I

� - - __ - - - __ - - __ I

I. Introduction

Dril'cn by the ever-increasing demands for 2. LC tank design

telccommunication market, the trend toward low

power, low cost and full integration of the radio The LC VCO can be deemed as a negative

frequency (RF) transceiver in a single chip by Gm oscillator as shown in Fig.!. L, C and g,an"

CMOS process is accelerated [I ,2J. Fully constitute the LC tank, where gtflI1l; re pres ents the

integratcd \'oJtage control l e d oscillator (VCO) is tank loss. -gactiv. is the effective negative

one of the most important and challenging conductance of the active devices thaI

building blocks in a RF transceiver. With the compensate the losses in the tank. The resonant

demand for 101\' power and low cost, on chip frequency of the oscillator can be approximately

VCO with no ex t erna l components is the best expressed as:

chOIce.
l I
gene r a l . 0
""

The specifications for the 27r.,f'iC

monolithic integrated VCO de s igns are power In this design, the target output frequency is

consumption, tuning range and phase noise. As around 2.4 GHz. For theVCO to t un e its output

the operating frequency is as high as several frequency, PN varactors are applied to vary the

0-7803-8511-X/04/$20,OO ©2004 IEEE.

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eapaclt,ll]ec: due to that it has hettcr linearity and fixed capacitance Cli, is added m parallcl with

I,mer gain than the MOS \"araetor counterpart the LC tank tha t not only adjusts the resonllnce

The on chip inductor is implement ed by us in g frequency to be within the rcquired range hut

planar spir a l inductor. To determine thp C value also lower the gain of the \'mactor. After

in Fig. I , several aspects sh ould be considered : ll) parasitic extraction and post-simulation, the

The tOla! c a pa cit a nce C includes vamctor si mulated freq uency range is between 2.366

capacitance. pamsitic capacitancc und uny other GHz to 1.655 GEz. When doi n g layout, the LC

fixed capncitnllce. Parasitic capa c itances afe tm1k should be placed <IS symmetry <IS possible,

around sc"eral hundreds tF. (1) The tuni ng range wh i ch makes the two output nodes have

of the "mactor Cllla)Cnun should be l arge enough equivalent output impedan ce.

�
L
to ensure the output frequency cover not only the T

�
specified frequency range but also the process

t1ucluation and temperature variation, where L .

Cnm and Culln <I re the m<lximull1 <lnd minimum I �Vml,

capacitancc II chievll ble by the var<lctor. (3) If

CI1O"/Cnufl is t oo high, a large gain or large Kvoo is

induc:c:d which will lead to high phase noise. As

�
�� �
J
I
0.

t,x Ihe inductor, the d esig n is also bounded to II--L-?----ij I c.

sC\'cral limitations: (1) The <l chiev<l ble

1 T
inductance is usually from 0.5-10 nB. (1) The Fig.3 Schematic of the VCO core

quali ty factor of the inductor QL should be as

high liS po ssible because the tank quality factor 3. Aetive Circuit Design

is mainl\' dctemlined by QL and QL h<ls dramatic

inlll1cnce on th e VCO phase noise perfomlanee. The rest of the LC tank in Fig. I is active

L L circui t part, which is implemented to act as a

negative Gm that compensates the losses in the

tank. The total schematic of the VCO core is

shown in Fig.3, which constitutes NMOS-PMOS

cross-coupled p<lirs and a NMOS ta il current

Fig.l LC tank in VCO core source. This structure is vel)' popular because: (I)
it has the tank a mplitude twice of that oC the

In this desi gn . after several iterations the NMOS-onl�' or PMOS-only cross-coupled pairs

finalh' achievcd LC tan k is illustrated in Fig. 1. structure, (2) it has more single -en ded s:l'mmetl)'

Note in thc tigure that two identical inductors in on e<lch of the rcson<lnce nodes by equating the

series act as the total inductance of the LC tank, positive and negati v e driven strength [4,5]. As

which features fully symmetry between the explained in [5], not only is it important to

diffcrenti<ll outpu t nodes [3}. Each inductor is maximize the differential symmetry to achieve

designed with an induct<lnce of 1.955 nH and a low ph a se 1l00se, but a lso to maximize

series resistance or 2.2 Ohl11. The QL is 7.8 <It 1.4 sin gle - ended symmetry such as the ch<lrging �nd

GHz. Thc two PN vamctors easi ly preserve discharging stren gth on the output nodes. From

sYmmetr\' with their cathodes connected to the Hajim iri phase noise model [6], the si ngle - ended

con trol voltage and anodes connected to the two symmetry will minimize the low frequency

output nodes, The designed value of Cm", is device noise up-conversion into the output

about 1000 tF and C,m" is about 380 tF Ano th er frequency spectrum and lower the I/f comer of

1:330
the ph'lse noise" ·t Measurement
In this design, to achieve differential
symmelr.\"- the NOMS pairs and PMOS pa i rs are To measure the circuit, a FR-4 test board is
designcd with good matching in layout. To fabricated as illustrated in Fig.4 (a). The chip is
achie\"C single-ended symmetry, the widths of fixed on the board with its pads bond-wired on
the PMOS pairs nre designed to be tlm:e times of the PCB (see Fig.4 (b). The test circuit for the
the NMOS pairs widths. which lends to 8nUl "" gmp. veo is shown in Fig.4 (c), in which the
The bias current of the veo core IS 4 mA, matching: components of the output nodes are
which is i mplemen t ed by the NMOS c urren t ealculated ta king the bond-wire inductance into
source. Note in the schematic Ihnl a iO pF consideration. Besides, three capacitors e l-C3
capncit or is added in pawllel with the current (O.luF, lnF, !OpF in sequence) are added in
source II'h ich prlwides a loll' impedance path to parallel on the board at the s u pply voltage node
Ae ground for higher harmonics. As is and control voltage node respectively to tilter the
ex plai ned in [7J, it helps to improve the phase noises [8}. The minimum capacitor added should
noise of the whole Yeo. To ensure that the veo be plac e d as close as possible to the chip.
can oscillate, it is suggested that the veo gain

a
3.0
which is equal to gactiv.lg",l\k be at least
greater than 3. 2.8
-0 - Measured

"N -0- Simulated

� O--{,I-C,"___O_C,
... 2.6 "0-
0
�
u

c:r
c

O--D---O_O_O
-'°- �'r).......
�

2.4 °_0 0....,_

...
,j: -0-
�

-; °_
0
,a.
� 2.2
0
2.0
0.0 0.5 1.0 1.5 2.0 2.5

Control voM.go (VI

Fig.S Output frequency \'5. control voltage

��M ; �l).�! �!�

, , �":i -I)'i.-:;!',�l[:r:::�=
,_.

,11 T_.!:::

(a)
�.. '. ���'1i�JJ:it._�;�:
! , '" Ii' �.. . , . .

t=--=�:H��l.i;
i h :\';
t��
!; II : ii' : iii , I ' , . i 'i
: .�. ·d , i "I il ,. , . ; .,.
I , i ,J ! t � i
.: r I, j -, . •

: ; ,J ; L j .l l
(b) : 11 f!i:- Frequency OffsC!t ;;� :.J�I:-
_ _ � I 4

Fig.6 Measured phase no ise of the veo

When the control voltage sweeps from 0 V

to 2.3 V, the OLlt put frequency varies from

2.4970 GHz to 2.2045 GHz, which corresponds
(c) to a t uning range of 290 MHz. This tuning range
FigA (a) FR-4 test ti:.:turc for the veo (b) completel�' depends on tuning the PN varactors
Illustration of bond wire . (c) Test circuit for the with no switched capacitor coarse tuning
veo implemented. Thus, the veo gain Kv,,", can be
1331
calcul<lted 10 be 127 MHz/V. In Fig.5, thc

sl11ll1laled and measured curves t(1r the output References

frequency versus the c ontrol voltage ar e shown.

The tested results are smnller than the simulated Pl. T. H. Lee, H. Samavati, and H. R. Ratcgh,

data hccallse some parasitic are not considcre d "5-GHz CMOS Wireless LAN,'- IEEE

during simulation. The devi atio n is nbout 150 Tmns. Microwave Theory and Teclmiques,

MHz on the average. In Fig.6, the measured vol. 50, pp. 268-280, Jan. 2002.

phase n o i se is -90 dBC/Hz at LOO KHz offset [2]. M. Stey aert et aI., "A 2-V CMOS cellular

and - 1 1 6 dBC/Hz at 2 MHz offset from the transceiver front-end," IEEE J. Solid-State

cente r frequencv. As the Kvoo in this design is Circuits, vol. 35, pp. 1895-1907, Dec.2000.

relatively la rge , by reducing the gain of the [31. Domine Leenaerts et aI., -'A 0 . 18 urn

"aractor and using switchcd capacitors to extend CMOS 2.45 GHz Low-Power Quadrature

the wning range, the Kvco can thus be reduced VCO wi th 1 5% Tuning Range,'- IEEE

which can further improve the phase noise Radio Fre qu ency I nteg rated Circuits

perfom1ance without sacrificing the tuning Symposium, M02C-3, pp. 67-70,2002.

range. [4] . .Tishnu Bhattachm:iee, et aI., -'A 5.8 GHz

Fully Integrated Low Power Low Phase

5. Conclusions N o is e CMOS LC VCO for WLAN

Applications," IEEE Ra d i o Frequency

A fully integrated 2.4 GHz CMOS LC I nteg ra ted Circuits Symposium, IF-TU-54,

VCO is designed and fabricated in 0.35 urn pp 475-478,2002.

BiCMOS process. Trade o ffs on the LC tank [5). Tamara 1. Ah r ens, Thomas H. Lee, -'A

design IS discussed. Symmetry des ign l'.4-GHz 3-mW CMOS LC Low Phase

considerations of the wliole VCO core from Noise VCO Using Tapped Bond Wire
schematic level to lay o ut , which are very Inductances," ISLPED98, Monterey, CA,
important for the phase noise reduction, are also USA 1998.

presented. Test considerations for the fabricated [6]. T homa s H. Lee, Ali Hajimiri, "Oscillator

VCO without pac kage are presented. The 2.4 Phase Noise: A Tutorial," IEEE J.

GHz VCO achieve s a mea5ured phase noise of Solid-State C irc ui t s , vol.35, NO.3 pp.

-00 dBClHz at 100 KHz oirset and -1 16 326-336, Mar.2000.

dBC/I-lz at 2 MHz o [T5et from the center [7). Ali Hajimiri, Thomas H. Lee, -·Design
frequency. A t uning range of 290 MHz is Issues 111 CMOS Differential LC

obtained only by tuning the PN varactors. The Oscillators," IEEE J. Solid-State Circuits,

VCO core consumes 4 mA current from the 3.3 vol.34, NO.5 pp. 717-724, May 1999.

V suppl\". [8). Dean Bane�iee, "PLL Performance,

Simulation and Design,-· chapter 12, 3rd

Aclrnowlcdgement Edition, 2003

This work is supported by National Natural

Science fund No. 60306005, No. 90207004 and

National 863 High Tech Project. The authors

would likc to thank Comlent Semiconductor,

Shanghai (0 support (esting the circuit.

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