ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

AN ACCURATE STATISTICAL YIELD MODEL FOR

CMOS CURRENT-STEERING D/A CONVERTERS
A. Van den Bosch, M . Steynert and W. Sansen
K.U. Leuven,
Department of Electrical Engineering, ESAT-MICAS,
Kard. Mercierlaan 94, B-3001 Heverlee, BELGIUM
e-mail : anne.vandenbosch@esat.kuleuven.ac.be

ABSTRACT 2. INL-YIELD ESTIMATION IN

To obtain a high resolution CMOS current-steering digital-
to-analog converter, the matching behavior of the current
source transistors is one of the key issues in the design. At
this moment, these matching properties are taken into
account by the use of time consuming and CPU intensive
Monte Carlo simulations. In this paper a formula is derived
that allows to accurately describe the impact of the
mismatch on the INL (integral non-linearity) yield of
current-steering D/A converters without any loss of design
time.
1. INTRODUCTION
The evolution in the field of wireless communications and
the mixed signal area pushes the designer to put an
increasing amount of effort in the integration of digital and
analog systems on one chip. Consequently, the interface
between these systems is becoming one of the most
challenging blocks to design in the telecommunication
devices of today. The demand for high performance
digital-to-analog converters - with applications in the area
of e.g. video, HDTV and GSM - has strongly increased.
Nowadays CMOS current-steering D/A converters are
frequently used for such applications since these circuits
can be implemented using a small silicon area (in
comparison with resistor ladder based implementations)
and can be easily integrated in fully digital CMOS
technologies implying a considerable cost reduction.
However, a current-steering D/A converter falls into the
category of circuits which are made using a large number
of identical building blocks (current sources) and therefore
its most important specifications are dependent on the
matching behavior of these blocks. It is important to be
able to determine the number of functional current-steering
D/A converters as a function of the matching properties of
the current sources.
In section 2, the yield estimations found in open literature
are evaluated and their pro’s and contra’s are discussed. In
the following section a new yield model will be presented
that in a minimum of time gives the wanted result. Finally
a conclusion will be formulated in section 4.
LITERATURE
2.1 Introduction
Due to the mismatch of the current source transistors, the
INL (integral non-linearity) specification of different D/A
converters made in the same process technology will vary
randomly. It is therefore important to be able to predict this
specification within certain boundaries. For this purpose,
the concept of the D/A converter’s INL-yield has been
introduced. This yield figure is defined as the percentage
of functional D/A converters with an INL specification
smaller than half an LSB (least significant bit).
In this section analytical expressions for the D/A
converter’s INL-yield found in open literature will be
discussed and evaluated. All of the models including the
new one start from the assumption that the unit current
source errors have a gaussian nature.
2.2 Lakshimikumar approach
A first suggestion to analytically determine the yield of a
D/A converter as a function of the matching parameters of
the current source transistors has been made in [ 11 :
-1
INL - yield = n erf Jz
i=2
(-)Q i
Qi
N = the number of bits,
-
z i = the mean normalized output at code i
0I0 = unit current relative standard deviation
However, this formula is based on the assumption that
there exists no correlation between the outputs of the
current-steering D/A converter. The INL-yield can then be
obtained by multiplying the probabilities that each output
has an error smaller than half an LSB (eq.1). To
demonstrate that this assumption is not correct the
following example is given. The outputs corresponding

0-7803-5482-6/99/$10.0002000 IEEE

IV- 105
with the digital input word 01100 and 01101 are strongly
correlated since they are both implemented using the same
current sources. The formula given in eq.1 gives us a rather
pessimistic view on the INL-yield (fig.1) leading to an
oversizing of the current source transistors [2] (eq.2) and
hence of the total chip area.
In [3] an adjustment of the formula in eq.1 has been
presented. Here the MSB (most significant bit) transition is
viewed as the most critical one since in a binary
implementation this transition has the largest probability of
generating an output error. Furthermore, the D/A
converter's outputs before and after the MSB transition are
not correlated and the yield can then be described as :
2" -I
ZNL-yield =
i=2"-'-1
erf (a)
Jz
(3)
Qi
N = the number of bits,
-
zi = the mean normalized output at code i
= unit current relative standard deviation
I
However, the yield estimation given in eq.3 is too
optimistic (fig.1) since the influence of only two outputs is
taken into account while the errors generated by the other
outputs are being ignored.
Comparing the two approaches one can conclude the
following : designing a chip using eq.1 can lead to a large
but nearly fault-free D/A converter while eq.3 gives you a
compact but low yield circuit. The correct yield estimation
is situated somewhere in between these two results.
2.3 Monte Carlo approach
To obtain an accurate estimation of the I N L j i e l d , the
Monte Carlo simulation [4,5] has been up till now
considered to be the only good altemative.
The following procedure can be used. Each of the (2N-1)
current sources has a random value that has been derived
from a gaussian distribution with mean value and a
standard deviation o(1). For every digital code the output
current of the D/A converter is calculated and compared to
the ideal value. If the difference is larger than half an LSB
- even for only one digital code - the D/A converter is
regarded as not functional and is therefore rejected. For
every o(1) this procedure is repeated a Iarge number of
times (> 100) to obtain reliable results. The INL-yield is
then given by the ratio of the number of functional D/A
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converters (INL<1/2 LSB) to the total number of try-outs.
In this way the relation between the unit current standard
deviation and the INL-yield is determined (fig.1).
However, to obtain the results depicted in fig.1 a large
amount of CPU time is necessary. Running a Monte Carlo
simulation for a high resolution D/A converter takes
several hours and that is a major drawback for this
approach.
, !
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
sigma(lyl
Fig. 1 : Monte Carlo simulations(0)of the INL-yield
compared to the results of the formulas in eq.l(+) and
eq.3(.) for a 10 bit DIA converter
3. NEW INL-YIELD FORMULA
3.1 Introduction
In this section, a formula will be presented that describes
the INL-yield of the D/A converter as accurately as the
Monte Carlo simulations but without any loss of design
time. The idea will be elaborated for an arbitrary number
of bits N. For the simplicity of notation the following
symbols are defined :
Definition 1 : X(j) is the sum of j non correlated unity
current sources
Definition 2 : Yfj) is the difference between Xu) and the
sum of the ideal current sources
Every current source has a normal distribution with a mean
value I,, and a standard deviation o(1).This implies that
both Xu) and Yu) also have a normal distribution with the
following properties (eq.4) :
3.2 Theory
The exact possibility that an INL error will occur is based
on the fact that each current source can generate an error
and hence is given by the following sum of probabilities
(eq.5) :
P(INL-error) = can be deduced from eq.9. At this point, the INL yield is
no longer described as a sum of probabilities (eq.5) but as
P((Y(1)l Z 0.5 & IY (2)(< 0.5 &
I -I
...& Y ( 2 N 1) < 0.5) +
the possibility that a sample from a normal distribution is
P(IY(2)I 2 0.5 & ...& Y ( 2 N -1) < 0.5) + ...+ (5)
I I smaller than half an LSB. This requirement can be written
as :
P ( k ( 2 N -l)l> 0.5)

However, this equation is not transparent and therefore not

-1 I ZLSB -Co (10)
suitable for practical use.
INL - yield
= 0.5 +
The basic idea behind the new theory is based on the 2
assumption that if at any point IY(i)l reaches half an LSB,
there exists a 50% chance that the error increases and 50% with P ( Y ( ~ ~the
) ) probability density function (fig.2).
chance that it decreases again since a normal distribution Eq.10 directly gives the following result :
with mean value zero is used. Extending this line of 1
C *B ( Y ( 2 N))I-LSB
thought one can say that if an INL error occurs - when 2
passing through all the possible codes generated by the with:
2N-1digital input words - there is a 50% chance that this
C = inv -norm(-,,,)(0.5 + INL - yield
> 0.5).
error still exists for the fictive code 2N((Y(2N)J )
2

Fig.2 : the shaded area determines the probability

P(Y(2N))< 112 LSB

This idea can be expressed as :

P(3j E [1..(2N - 111 :IY ( j ) l > 0.5)
I NI
P(Y(2 ) > O S ) =
2
(6)
At this point the INL-yield of the D/A converter can be
integrated in the calculation since there exists an obvious
relation between the yield and the possibility of an INL C = inv -norm(-,,,)(0.75 + INL-4yield 1
error to occur :
Eq.11 can be rewritten as a relationship between the unit
INL-yield = 1 - P ( 3 j ~[1..(2N - l ) ] : ~ Y ( j ) ~ > O S ) (7) current relative standard deviation and the INL-yield of
the D/A converter (incorporated in coefficient C) :
Combining eq.6 and eq.7 :
1 - INL - yield
2
From eq.8 the possibility that no INL error occurs at code Fig.3 shows the Im-yield of the D/A converter in
2Ncan be easily derived and equals : function of the coefficient C.
INL- yield In fig.4 the INL-yield of a 10 bit D/A converter calculated
(9) using the new formula (eq.12) and simulated using the
2
Monte Carlo approach are depicted. From this figure it can
Since Y(2N) has a normal distribution with a standard be concluded that the formula is in good agreement with
deviation P o ( I ) (eq.4), the relation existing between the Monte Carlo simulations.
the IN-yield of the current-steering D/A converter and To gain more insight in eq.12, the unit current standard
the matching properties of the current source transistors deviaticn is plotted in logarithmic scale versus the

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 100
Fig.4 : Comparison between the Monte Carlo simulations
(*) and the formula (line) for a IO bit D/A converter
resolution of the D/A converter (fig.5). As can be seen
from fig.5 these are straight lines since
Furthermore, one can easily conclude from this figure that
for the design of a high accuracy current-steering CMOS
D/A converter the matching parameters play a significant
role. A small deviation of the required sigma(I)/I can lead
to a severe yield degradation.
01
0.01
______ _ -
0.001 4
I------ I
6 8 10 12 14
number of bits
Fig.5 : The unit current relative standard deviation in
function of the resolution of the D/A converter for a 30
yield of 99.7% (+), a yield of 50% ( 0 )and of 10% (m)
The time to create a figure like fig.5 using Monte Carlo
simulations in MATLAB is given in table 1. In this table
the results for the INL-yield from 100% to 10% for a
current-steering D/A converter with different resolutions
can be found. For all the simulations twenty values for the
relative unit current standard deviation were taken. This
can be understood as follows. In a first coarse
approximation a simulation using 10 values for sigma(I)/I -
that span a wide range- is run. From the obtained result the
interval for the sigma(I)/I that obtain a high INL-yield can
be specified. In this interval another 10 points are
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simulated. In almost all cases this procedure gives accurate
results.
Constructing fig.5 using the new formula takes only a few
minutes. The time to write the short program For
MATLAB is so to speak the most time consuming. It is
also worth noting that the time necessary to calculate .the
yield is independent of the resolution of the D/A converter
while the time consumption of the Monte Carlo
simulations “explodes” with an increasing D/A converte:r’s
accuracy.
14 bit
Table1: comparison between the time consumption of the
Monte Carlo simulations and the new formula
4. CONCLUSION
Since high resolution current-steering D/A converters are
strongly dependent on the matching characteristics of the
technology in which they are processed, it is important to
know the number of functional chips in a set of fabricated
devices. It is proven in this paper that time consuming
Monte Carlo simulations are no longer necessary to obtain
results for the Im-yield with a good accuracy. A new
formula has been presented that directly gives you the
INI-yield of a current-steering D/A converter in function
of the transistor mismatch parameters of the current
sources without any loss of design time.
5. REFERENCES
[ I ] K. Lakshimikumar and al., “Characterization and Modeling
of Mismatch in MOS Transistors for Precision Analog
Design”, IEEE Journal of Solid State Circuits, v01.21, Dec
1986, pp. 1057-1066
[2] M. Pelgrom, A. Duinmaijer and A. Welbers, “Matching
Properties of MOS Transistors”, IEEE Journal of Solid
State Circuits, vol. SC-24, Oct. 1989, pp. 1433-1439
[3] K. Lakshimikumar and al., “Reply to ‘A Comment on :
Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design”, IEEE Journtzl of
Solid State Circuits, vo1.23,Feb. 1988, pp. 296
[4] C. Conroy, W. Lane and M. Moran, “A Commenf. on
‘Characterization and Modeling of Mismatch in MOS
Transistors for Precision Analog Design,’” IEEE Journd of
Solid State Circuits, ~01.23,Feb. 1988, pp. 294-296
[5] J. Bastos and al., ‘‘ A 12 bit Intrinsic Accuracy High Speed
CMOS DAC,” IEEE Journal of Solid Slate Circuits, vo1.33,
No.12, Dec. 1998,pp. 1959-1969