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Simulating MOS Transistor ft

By Arthur Schaldenbrand on August 9, 2008
Comments(9) Login with a Cadence account.
Filed under: RF design, bipolar transistor, MOS transistor

One other question that you might ask is, this approach works for bipolars but what happens when you
need to characterize a MOS transistor. Nothing changes, use the same testbench and measurements, see Not a member yet?
figure 1. In this testbench a MOS transistor is being compared to a bipolar transistor. Create a permanent login
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Figure 1: MOS and BJT Comparison

Industry Insights
The simulation results are shown in Figure 2. The difference in the results is that the low frequency bipolar Low Power
transistors current gain is limited by the base current, while the MOS transistor current gain is not limited. Mixed-Signal Design
Note, in advanced node processes, MOS transistors do have significant gate leakage and the plot for the System Design
MOS transistor would look more like the plot for the bipolar transistor. and Verification
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ADE-L Analog Simulation

Circuit design Circuit
simulation DAC Electromagnetic (EM)

Harmonic Balance Measuring

Transistor ft MMSIM MMSIM71

PSS RF RF Block

Simulation RF design RF
designer RF Simulation RFIC
Figure 2: Comparison of current gain
Spectre Spectre RF
spectreRF Virtuoso
So the same techniques that you would to characterize a bipolar transistor and also be applied to MOS
transistor. Virtuoso Spectre
Virtuoso Spectre
Simulator GXL Virtuoso
Spectre Simulator XL
wireless integrated circuit
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Simulating MOS Transistor ft - RF Design - Caden... http://www.cadence.com/Community/blogs/rf/archi...

Comments(9)

By Guy on November 9, 2008

Hi,Can you send me a zoom for figure 1? I can't see device parameters in this screen. My email:
guysari@gmail.com

By yves dufour on November 14, 2008

Hello, Allow me to react on the previous comment, Can you please add the netlist in the article so we can
reproduce the analysis. Thank you.Yves

By Yutao Liu on April 26, 2009

I don't understand which component you place between the gate terminal of the MOS and ground. It seems that it is
not included in analoglib in spectre, right?

By Art Schaldenbrand on April 27, 2009

Yutao,

The components is the current-controlled, current source, cccs, from the analogLib.

Best Regards,

Art Schaldenbrand

By Art3 on April 27, 2009

Hi,

Sorry I should have posted the netlist sooner, it would have

avoided a lot of confusion for everyone.

Best Regards,

Art Schaldenbrand

simulator lang=spectre
global 0
parameters ICE=100u VCE=5
//
// these model files should be available in the samples directory
//
include "./models/NPNlower.scs"
include "./models/cornerMos.scs" section=TNTP

V0 (net014 0) vsource dc=VCE type=dc

// MOSFET ft
// NOTE: the element instance names have been changed
// the default names are shown in the bjt section
// IREFERENCE --> 0V voltage source
// IFEEDBACK --> current-controlled, current source
IIN (net014 net9) isource dc=ICE mag=1 type=dc
IREFERENCE (net6 0) vsource dc=0 type=dc
IFEEDBACK (net9 0) cccs gain=1.0 probe=IREFERENCE
NM0 (net014 net9 net6 0) nmos24 w=24u l=1.5u m=10

// BJT ft
I2 (net014 net025) isource dc=ICE mag=1 type=dc
V1 (net012 0) vsource dc=0 type=dc
F0 (net025 0) cccs gain=1.0 probe=IREF_BIPOLAR
Q0 (net014 net025 net012 0) NPNlower

ac ac start=1 stop=100G annotate=status

save NM0:g NM0:d Q0:c Q0:b

By Art3 on May 1, 2009

One more comment,

Yutao has pointed a limitation of the testbench. This testbench should not be used
when the Vds of the DUT, transistor is 0. Forcing the transistor to conduct constant current when Vds=0 causes
convergence and accuracy issues. In general, this should
not be an issue since testbench is intended to measure the characteristics of devices biased in saturation: ft, gm,
gds, ...

Best Regards,

Art Schaldenbrand

By greg on July 15, 2009

Hi, i tried to simulate ft of the mosfet.
I tried to rebuild the circuit you list and plot it.
dB20(IF("/M0/D")/IF("/M0/G"))
And it show a error. it can handle nil / nil.
Can you tell me how to simulate correctly? Thanks.

By Art Schaldenbrand on July 17, 2009

Greg,

Sorry for the delay in replying, I have been at CDNLive! Japan this week.
It was fun but hectic!

The issue is that the syntax example from the bipolar ft testbench is the

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Simulating MOS Transistor ft - RF Design - Caden... http://www.cadence.com/Community/blogs/rf/archi...

syntax for the bipolar ft schematic testbench simulation. In the testbench

schematic, the DUT is called Q0. In this netlist, the DUT is NM0. So the
correct syntax would be

dB20(i("NM0:d" ?result "ac-ac")/i("NM0:g" ?result "ac-ac"))

which matches the format used in the save command.

Also as mentioned in the bipolar append, it is easiest if you actually

build the expression yourself rather than trying to remember the syntax.
For example, if you are using ViVA:
1. Open the Results Browser
2. Select the output data directory, raw/psf/...
3. Select the results, ac-ac
4. Right mouse button on NM0:d and select calculator
5. Right mouse button on NM0:g and select calculator
6. Select divide, "/" from the calculator keypad
7. Select, dB20 from the "Math" functions

Also, just noticed that there is a typo in the bipolar portion of the netlist.
The probe and the instance name are mismatched. The issue can be
resolved by renaming the instances,

simulator lang=spectre
global 0
parameters ICE=100u VCE=5
//
// these model files should be available in the samples directory
//
include "./models/NPNlower.scs"
include "./models/cornerMos.scs" section=TNTP

V0 (net014 0) vsource dc=VCE type=dc

// MOSFET ft
// NOTE: the element instance names have been changed
// the default names are shown in the bjt section
// IREFERENCE --> 0V voltage source
// IFEEDBACK --> current-controlled, current source
IIN (net014 net9) isource dc=ICE mag=1 type=dc
IREFERENCE (net6 0) vsource dc=0 type=dc
IFEEDBACK (net9 0) cccs gain=1.0 probe=IREFERENCE
NM0 (net014 net9 net6 0) nmos24 w=24u l=1.5u m=10

// BJT ft
IIN_BIPOLAR (net014 net025) isource dc=ICE mag=1 type=dc
IREF_BIPOLAR (net012 0) vsource dc=0 type=dc
IFDBK_BIPOLAR (net025 0) cccs gain=1.0 probe=IREF_BIPOLAR
Q0 (net014 net025 net012 0) NPNlower

ac ac start=1 stop=100G annotate=status

save NM0:g NM0:d Q0:c Q0:b

Best Regards,

Art Schaldenbrand

By bVenu on April 29, 2010

Hi Art,

Could you possibly put up a test bench to simulate the Fmax of a transistor too?

Thanks
Venu

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