Ain Shams University 3/5/2009

Pipelined ADC

Mohamed Dessouky
Ain Shams University
I.C. Lab.

ADC Architectures
Low-to-Medium Speed, Medium Speed, High Speed,
High Resolution Medium Resolution Low-to-Medium
Resolution

Integrating Successive Flash

(Rampfunction) Approximation
Two-step
Delta-Sigma Algorithmic Pipelined
Interpolating
Folding
Time-interleaved

Speed ↑, Resolution ↓
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ADC Applications

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ADC Architectures

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Outline

• Introduction

• Stage Errors

• Digital Error Correction

• Example

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Flash ADC (Parallel)

• Input is simultaneously compared with 2N–1 reference voltages.

• Reference voltages typically derived from a resistor string.

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Two-Step ADC – Operation

Vin-DAC

DAC
MSB 01
0100
2nd ADC
Fine LSB + 11
0011
_____
Result 0111
1st ADC
Coarse

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Two-Step ADC

• Number of comparators = 2M + 2Q – 2.
• Example: # of comparators for 8 bits
– Flash = 28 – 1 = 255
– Two-Step (5-5) = 24 + 24 – 2 = 30
• Compared to the Flash A/D converter, the two-step A/D
converter trades speed for reduced complexity and power.
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Pipelined ADC

Multiplying-DAC (MDAC)

• General extension of the two-step ADC with interstage gain.
• Trade conversion speed for latency using interstage SHA
• Speed is limited by conversion speed of one stage.

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Pipelined ADC

• Throughput is independent of the number of stages.

• Number of components grows linearly with resolution.

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Stage Transfer Function

• Consider a 3-bit pipeline, based on a 1 bit per stage topology.

Vout = 2Vin − DnVref + DnVref

Residue 11
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Precision Multiply-by-Two Amplifier

C1 = C2
floating

• Phase φ1: both capacitors are

charged to Vin0.


• Phase φ2: Since node X is floating,
the second capacitor charge is floating
transferred to the first one such
that
Vout = 2Vin 0
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Pipeline 1-Bit Stage Implementation

Vn −1 = 2Vn − DnVref + DnVref

• In CMOS technologies, the gain, subtraction, and SHA

functions are readily merged into a single SC block.
• A precision multiply-by-two amplifier. Instead of grounding C1,
it is connected to ±Vref to perform the required subtraction
through an inverting amplifier configuration.
• Digital correction is used to alleviate comparator requirements.
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Outline

• Introduction

• Stage Errors

• Digital Error Correction

• Example

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The Contribution of Stage Errors

∑ ∑ ∑
×G ×G ×G
e1 e2 ek

k
ei
• Input referred error: ein = e1 + ∑
i=2 G i −1
FS i −1
• Each error must be < LSB/2: ei ≤ G
2 N +1

• The first stage error is the most significant

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Stage Errors
ε VA
Vin
Gain/Nonlinearity error
Duty _ cycle f s t VS
Settling error SHA Residue
+ 2M

Offset

DAC output errors

ADC comparator errors

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Sub-ADC Errors

• Offset, Gain, and Nonlinearity

• All move the decision levels of the ADC

• Digital correction & redundancy can eliminate such errors

• Only the last stage errors are not corrected. However, their

contribution to the overall ADC errors are divided by the

product of all inter-stage gains.

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Sub-DAC Errors
• Offset:
– Equivalent to an offset in the sub-ADC
– Can be corrected by digital correction/redundancy

• Gain error:
– Equivalent to gain error in the sub-ADC + inter-stage
gain error
– Gain error in the sub-ADC can be corrected by digital
correction/redundancy
– Inter-stage SHA gain error, see later

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Sub-DAC Errors (contd.)

• Nonlinearity: Error that depends on the DAC output
– Must be < LSB/2
δi FS δi FS
∴ i −1
≤ N +1 or i −1
≤ N +1
G 2 G 2
FS
s G = 2M ∴δ i ≤ [N − M (i −1)]+1
2
N-M(i-1) ≡ The number of bits remaining to be
determined by the stage i and the following stages
– The DAC in each stage must be at least as linear as the
combined resolution of this and the later stages.
– The first stage DAC must be as linear as the entire ADC.
– 1-bit DACs are inherently linear

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SHA Gain Errors

• Offset:
– Equivalent to DAC offsets
– Can be corrected by digital correction/redundancy

• Gain error:
– In the first stage, no quantization has occurred yet, SHA
gain error just causes ADC gain error.
– In the following stages, the resulting error must be at
least as linear as the combined resolution of this and
the later stages.

• Nonlinearity error:
– Same as the gain error, but includes also the first stage.

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Errors Summary

Block Error Requirement

Sub-ADC Offset, Gain, & digital correction

Nonlinearity
DAC Offset digital correction

Gain digital correction + SHA Gain error

Nonlinearity ≤ Resolution of this and following stages

SHA Offset digital correction

Gain ≤ Resolution of this and following stages

Nonlinearity ≤ Resolution of this and following stages

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Outline

• Introduction

• Stage Errors

• Digital Error Correction

• Example

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Digital Error Correction in 2-step ADC: Idea

Out of range
(underflow) Input range
extension with
one additional
bit

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Digital Error Correction in 2-step ADC: Procedure

Input range
extension with
one additional

bit




Offset

MSB 1000
10
LSB + 0001
001
Offset − 0010
10
_____
Result 0111

±2 LSB of comparator offset can be tolerated in the coarse ADC.
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Digital Error Correction

• 1-bit pipeline stage.

• Offset in sub-ADC transition level (Vth = 0V) causes the output
to exceed the output range ±Vref.
• To solve this problem
– Extend output range and use extra bit for correction!
– Decrease the interstage gain to maintain the output range
±Vref.
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Digital Error Correction: Idea

V1
3-bit
Lower gain
Pipelined 2 bits 1 bit 2 instead of
ADC 22 = 4


1 extra bit
FS 2V V Digital Correction for correction
∆ = N = ref = ref
2 22 2

∆ × 2 = Vref
V1

V1

Vref
+ MSB 110
1 1
2
LSB + 01
001
Offset − 01
001
Vref _____
−
2 Result 110

Residue 1st stage Residue 2nd stage

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Digital Error Correction: with Offset

Same input 110

MSB 100
1 0
LSB + 11
011
1/4 Vref Offset − 01
001
1/4 Vref _____
Result 110

Residues

• First ADC error can be as large as ¼ Vref and still in input range.


• Both addition and subtraction operations are needed.
• To use only addition, subtract the offset from the input signal
directly.
• Offset = 1 LSB = 2 Vref / 23 = Vref / 4.

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Digital Error Correction: Modified Stage

• To use only adders in the digital error correction circuit.

• Add intentional –¼ Vref = 1 LSB offset at the input.

• Can be transferred as –¼ Vref offset at input and output of
ADC/DAC in circuit implementations.

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Digital Error Correction: Modified Stage

Same input 110

MSB 100
1 0
LSB + 10
010
_____
Result 110

Residues

• With ¼ Vref offset at input, no need for offset subtraction.

• First ADC error can be as large as ¼ Vref and still corrected.
• Since the last segment in the first stage (11) is redundant,
i.e. can be corrected for, we can totally remove it.

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Digital Error Correction: 1.5 bit/stage

Residue

• Only two levels or 1.5 bits.

• Equivalent to 2 bits with correction in the following stage.
• Most popular pipeline stage. Only 2 comparators.
• For N-bit converter with 1.5 bit/stage, N-1 stages are
required: The first stage provides 2 bits, while other stages
provide only 1 bit each reserving the second bit for digital
correction.
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1.5 bit/stage: Transfer Function

Vref
10
Vref/4
01
-Vref/4
00
-Vref

thresholds

Vin d1 d0 DAC Output Residue

Vin>Vref/4 1 0 Vref 2* Vin - Vref

-Vref/4<Vin<Vref/4 0 1 0 2* Vin
Vin<-Vref/4 0 0 -Vref 2* Vin + Vref

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1.5 bit/stage: SC Implementation

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Outline

• Introduction

• Stage Errors

• Digital Error Correction

• Example

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Example: 10-bit ADC – 1.5 bit/stage

• 9 stages.
• First stage gives two bits
• Stage 2 to 9 give one bit + one bit for digital correction of
the previous stage.

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Example: 10-bit ADC – Last Stage

Vref Vref
10 11
Vref/2
Vref/4 10
01 0
-Vref/4 01
00 -Vref/2
00
-Vref -Vref

2-bit digital-correction thresholds 2-bit flash standard thresholds

• The Nth stage cannot be digitally corrected (since there are

no following stages)
• It is implemented by only a Flash ADC
– have standard thresholds.
– If digitally corrected offsets are used, the top code
1111… will be missing which is typically not critical.

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Number of bits/Stage
• Tradeoff between speed, power, and accuracy of each stage.
• For fewer number of bits per stage,
+ the sub-ADC comparator requirements are more relaxed
+ the inherent speed of each stage is faster because the
inter-stage gain is lower allowing higher speed due to the
fundamental gain-bandwidth tradeoff of amplifiers.
– more stages are required if there are fewer bits per stage.
– the noise and gain errors of the later stages contribute
more to the overall converter inaccuracy because of the
low inter-stage gain.
• High-speed, low-resolution specifications favor a low number
of bits per stage.
• Low-speed, high-resolution specifications tend to favor higher
number of bits per stage.

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References
• Bruce Wooley & Katelijn Vleugels, « EE315: VLSI Data Conversion
Circuits – Handouts », Department of Electrical Engineering,
Stanford University, http://www.stanford.edu/class/ee315/
• Paul G. A. Jespers, « Integrated Converters: D to A and A to D
Architectures, Analysis and Simulation », Oxford University Press,
2001.
• Georges Chien, «High-Speed, Low-Power, Low Voltage Pipelined
Analog-to-Digital Converter », M.Sc., University of California,
Berkeley, 1996.
• S. Lewis, «Optimizing the Stage Resolution in Pipelined,
Multistage, Analog-to-Digital Converters for Video-Rate
Applications», IEEE TCAS-II, Vol. 39, No. 8, August 1992.
• Andrew Masami Abo, «Design for Reliability of Low-voltage,
Switched-capacitor Circuits », Ph.D., University of California,
Berkeley, 1999.
• Behzad Razavi, « Design of Analog CMOS Integrated Circuits »,
McGraw-Hill, 2001.

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