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Abstract − This paper describes the design of a 12-bit ulator are beyond of scope of this paper, but more
80MS/s Digital-to-Analog converter implemented in a information can be found in [5].
0.13µm CMOS logic technology. The design has been
The paper is organized as followed. In Section II,
computer-aided by a developed toolbox for the simulation
the D/A converter architecture as well as the main
and verification of Nyquist-Rate Analog-to-Digital and
Digital-to-Analog converters in MATLAB. The converter design trade-offs are discussed. In Section III, the basic
is segmented in an unary current-cell matrix for 8 MSB's building blocks are presented, namely the current cell,
and a binary-weighted array for 4 LSB's. Current the driver, the level-shifter, the latch and the thermom-
sources of the converter are laid out separately from cur- eter decoder. Layout issues are explained in Section
rent-cell switching matrix core block and distributed in IV. Finally, transistor-level simulation results are
double centroid to reduce random errors and transient shown in Section V.
noise coupling. The linearity errors caused by remaining
gradient errors are reduced by a modified Q2 Ran-
II. D/A ARCHITECTURE
dom-Walk switching sequence. Transistor-level simula-
tion results show that the Spurious-Free Dynamic-Range The basic block diagram of a segmented current
is better than 58.5dB up to 80MS/s. The estimated Sig- steering DAC is shown in Fig.1, where the input N-bit
nal-to-Noise Distortion Ratio yield is 99.7% and better are split in b Least Significant Bits (LSB’s), which
than 58dB from DC to Nyquist frequency. Multi-Tone steer a binary weigthed array of current sources -binary
Power Ratio is higher than 59dB for several DMT test sig- segment-, and t = N – b Most Significant Bits
nals. The converter dissipates less than 129mW from a (MSB’s), which are thermometer-wise decoded to steer
3.3V supply and occupies less than 1.7mm2 active area.
an unary array of current sources −thermometer seg-
Keywords: digital-to-analog converters, current ment. The current sources are commuted on/off by
source, segmentation, switching sequence. means of complementary switches which are synchro-
nized and biased by latches and drivers circuits, respec-
I. INTRODUCTION tively.
The trend to reduce the cost of market communi- In this block diagram it can be distinguished three
cation devices has motivated the interest for embedded high-level important factors: the segmentation, i.e. the
high-speed high-resolution Digital-to-Analog Con- number of thermometer (t) and binary (b) bits, the
verters (DAC’s). These converters are essential com- switching scheme, that is, the sequence in which the
ponents of modern applications such as video signal
bN bN – 1 … bb + 1 bb bb – 1 … b1
processing, digital signal synthesis, and both broad-
… …
band and wireless communications. Of several archi-
tecture alternatives, CMOS current steering DAC’s Thermometer Latency
have demonstrated to be an attractive solution for these equalizer
decoder
applications [1][2][3] because of two reasons mainly:
(a) they can be implemented in adverse digital CMOS
technology with evident power consumption and inte-
grability advantages and (b) they are intrinsically faster Swatch array
and more linear that their counterparts-based on resis- (latches+drivers+switches)
tors or capacitors ladders [4]. However, the combina-
tion of high data conversion rate, accuracy and
linearity is difficult to achieve. In this paper, dynamic
Cascode current source
and static limitations for the circuit linearity have been
investigated, resulting in the presented DAC and in the Current source array
development of a behavioural simulator which has
aided in its design. Details about this behavioural sim- Fig. 1: Block diagram of a segmented current steering DAC.
* ruiz@imse.cnm.es; phone +34955056666; fax +34955056686; www.imse.cnm.es
thermometer current sources are activated and the the layout as will be shown later.
topology of the current cell. Next subsections will • Switching sequence, i.e., the sequence in which the
focus in these issues. different current sources are switched on/off in the
unary current source array. An elaborated overview
A. Segmentation.
of different switching sequences is given in [10] and
It is a crucial parameter because there is a direct it is beyond the scope of this paper. The objective of
trade-off between the DAC linearity, area, Total Har- the switching sequences is to compensate for gradient
monic Distortion (THD), glitch energy and the seg- errors in the unary array of the DAC, both linear and
mentation level as shown in [6]. In particular, the quadratic gradients. These gradients can become very
Integral Non-Linearity (INL) and Differential significant when the unary array active area is large,
Non-Linearity (DNL) DAC depends on the segmenta- which is common in high-accuracy applications
tion as follows [7]: where random errors of current sources are reduced at
σi expense of increasing the active area of each current
σ DNL max = LSB
2 b + 1 – 1 ----------- in LSB units source. Therefore, an optimum switching sequence
i LSB
(1) has to be selected, so an extensive exploration of sev-
σi eral switching sequences has been done with the aid
σ INL max = LSB
2 N – 1 ----------- in LSB units of a dedicated behavioural simulator. In order to find
i LSB
out which of the switching sequences is the most
where i LSB is the current of the LSB current cell, i.e. appropriate, an unary current source array was
the ratio between the full-scale current ( I FS ) and the defined by considering the effect of gradient errors
total number of current cells ( i LSB = I FS ⁄ 2 N ) and and several switching sequences were applied. The
σi its standard deviation. From (1) it can be result of this analysis can be summarized in Fig.2,
LSB
deduced that, although INL is independent of the seg- where Q2 Random Walk and Q2 Random Walk
mentation, the more binary (b) bits are employed the (Cong) turn out to be the best switching sequences
higher DNL will be. Analogously, THD and glitch since they tolerate high gradient errors. Moreover,
energy increases too. Therefore, it is advisable to use these switching sequences present minimum resolu-
the maximum number of thermometer bits. However, tion deviations against the linear gradient error angle
the area increases seriously when a high number of ( θ ). Although all Q2 switching sequences show good
thermometer bits is selected. From [6][7][8] it can be properties, we choose Q2 Random Walk (Cong)
concluded that an optimum segmentation for a 12-bit sequence because it presents light advantages as
current steering DAC is 8 thermometer bits and 4 shown in [10].
binary bits. This has been the adopted solution in this
paper.
75
B. Switching scheme.
The static performance of a current steering DAC 70
SNDR(dB)
tion even although the switches were biased to operate where A V and A β are mismatch technology parame-
T
in saturation in order to increase the output impedance. ters and ( V gs – V th ) is the gate overdrive voltage of
An alternative to the simple current cell is the cas- the current source. On the other hand, the full scale cur-
code current cell showed in Fig.3(b). This circuit rent defines the i LSB = I FS ⁄ 2 N and set another con-
exhibits the output resistance of a double-cascode dition over the ( W ⁄ L ) ratio of the current source:
structure when the switches operate in saturation 1 W
which is enough for low-distortion applications. This i LSB = --- µ o C ox ----- ( V gs – V th ) 2 (3)
2 L
has been the topology employed in our current steering
Finally, only the gate overdrive voltage is a free-
DAC. In addition, p-MOS transistors have been used
dom degree. From (2) it can be deduced that by
because they are more robust against noise substrate.
increasing the ( V gs – V th ) , the minimum area required
Details about the design issues will be discussed in
can be decreased. For very large values, however, the
next section.
mismatch is mainly determined by the A β term. A con-
venient criterion to determine the gate overdrive volt-
III. BUILDING BLOCKS DESIGN age of the current source will be that one which
The basic building blocks in a segmented current minimizes systematic errors. Of several systematic
steering DAC can be identified in the block diagram in errors, the effects which contribute in most extent are
Fig.1, i.e., the current cell, the driver circuit, the latch the finite output impedance and others ones which are
and level shifter, the thermometer decoder and other
auxiliary blocks such as internal voltage generators 100
and current reference generators. Next, a detailed
description of these circuits is given. 99
A. Current cell.
Yield (%)
98
As shown in previous section, in order to mini- (a)
mize random errors, a minimum area is required for the 97
transistor which operates as current source (Mcs) so the
impact of the relative standard deviation of current 96
80
75
70
65
SNRD(dB)
Mcas 50
45
Mcs Mcs
40
0 2 4 6 8 10 12 14 16
(a) (b) Output impedance (MΩ)
Current source on
Taking into account the above-mentioned issues, 1
V = 0.9v
the electrical-level sizing of the cascode current cell in ref 10 12 14 16 18 20 22 24
t(ns)
Fig.3(b) was carried out by combining an statistical
(a) (b)
optimizer with an electrical simulator, considering the
following constraints: Fig. 5: Driver: (a) circuit implementation and (b) transient respons
5
SNDR = 74.29dB
σ SNDR = 0.07dB
CS ARRAY 4
Number of events
Bandgap Dec.
cap. 0
74.1 74.15 74.2 74.25 74.3 74.35 74.4 74.45
SNDR(dB)
Fig. 7: Current steering DAC layout. Fig. 8: Montecarlo analysis.
Finally, Table 2 summarizes the performance TABLE 2. Performance summary
results. Experimental results will be presented on the
Current Steering DAC 12bit@80MS/s
symposium.
Process 0.13µm CMOS
CONCLUSIONS Resolution 12 bits
A segmented 8 + 4 bits CMOS current steering Differential Input Range 1 Vp-p
DAC with a SFDR better than 58.5dB up to 80MS/s Power Supply 3.3V
and a MTPR higher than 59dB has been presented. It Power consumption 129mW
has been realized in 0.13µm CMOS, has an active area Active area 1.7mm2
of 1.7 mm2 and consumes 129mW for a 20mA MTPR > 59dB
full-swing output current. Systematic errors have been SFDR (38MHz@80MS/s) 67dB
analysed and reduced by using an improved 2-D cen- Output load 25Ω || 20pF
troid switching scheme [10] and by a careful layout
generation. The design has been computer-aided by a
behavioural simulator which runs under MAT-
[2] Anne Van den Bosch, Marc A. F. Borremans, Michel S.
LAB/SIMULINK. J. Steyaert, and Willy Sansen: “A 10-bit 1-GSample/s
Nyquist Current-Steering CMOS D/A Converter”,
ACKNOWLEDGMENTS
IEEE Journal of Solid-State Circuits, vol. 36, no. 3,
March 2001.
This work has been supported by the MEDEA+ [3] J. Vandenbussche, G. Van der Plas, A. Van den Bosch,
(A110 MIDAS) and TIC2003-02355RAICONIF W. Daems, G. Gielen, M. Steyaert, W. Sansen: “A 14 b
150 Msample/s update rate Q2 random walk CMOS
Projects. DAC”, IEEE Solid-State Circuits Conference (ISSCC),
pp. 146-147, February 1999.
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Fig. 9: Output spectra for (a) a single input tone at 38MHz and (b)
a DMT test signal.