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ICROS-SICE International Joint Conference 2009

August 18-21, 2009, Fukuoka International Congress Center, Japan

A PWM Motor Speed Control System based on the Dual-Loop PLL


Hidekazu Machida ,Michinobu Kambara ,Kohta Tanaka ,Taisuke Yamochi
and Fuminori Kobayashi
Maizuru College of Technology, Kyoto,Japan
(Tel : +81-773-62-8957; E-mail: machida@maizuru-ct.ac.jp)
Kyusyu Institute of Technology, Fukuoka, Japan

Abstract: PLL motor speed control systems can completely reject speed error and steady-state phase error for constant-
speed input signals. However, it is not usually applied to systems with inputs including acceleration, because they have
poor tracking speed and strange pull-in behavior.
In the field of radio communication, “dual-loop PLL” is very effective for such signals. It can not only enable high-speed
tracking, but also cancel phase error. This article shows that the principle can be applied, with some devices, to motor
speed control, and a prototype implementation using PWM is described.
Two supplemental techniques, called “active feedforward” and “active limiter”, are also incorporated, to achieve faster
tracking and speed limitation. The scheme was implemented by programming an FPGA, and satisfiable results were
obtained.

Keywords: PLL,motor,dual loop,PWM,FPGA

1. INTRODUCTION 2. PLL SYSTEM


2.1 Basic PLL system
PLL, phase locked loop, is a control system that gener-
ates a signal synchronizing to the phase of a ”reference” Block diagram of basic PLL is shown in Fig.1. It con-
signal . sists of Phase Detector, PD for short, Loop Filter, LF for
short, and VCO, voltage-controlled oscillator, as well as
PLL has been applied to motor speed control , Divider between the VCO and the feedback input to the
which features that systems can theoretically reject speed phase detector for frequency synthesizer applications.
error and steady-state phase error completely for input
signals with constant speed. However, for input signals
with acceleration, this is not the case.

In the field of radio communication, possible remedy


for this situation called “dual-loop PLL” has been used.
It has two PLL loops, where first one is the feedforward
component of the second one. As a result, it can not only Fig. 1 Basic PLL construction
enable high-speed tracking, but also cancel phase error.

However, direct application of this PLL to motor speed The input signal is normally constant frequency.
control poses a problem, because motor rotate direction PD detect the phase error , between
should follow the sign of the input. We solved this prob- input phase and feedback phase . The LF
lem by inserting loop filters into both feed back paths, and removes unnecessary high frequency component, for
employed a special adder in PWM to implement loop ad- enough phase margin. The VCO oscillates at a frequency
dition for the two phase detector outputs . proportional to the input voltage, and it output is fed-back
to PD as phase.
For effective operations in practical applications, sup-
When this feedback system is stable, it is called
plemental techniques, called “active feedforward” and
locked, and phase error is zero or very small, leading to
“active limiter,” are also incorporated, to achieve faster
synchronization between the input and output frequen-
tracking and speed limitation.
cies.
The scheme was implemented by programming an Divider, if present, allows N times higher the input fre-
FPGA, and satisfiable results were obtained. quency than the output frequency, .
From Sec. 2 on, a short introduction of PLL sys- 2.2 PLL dynamics
tems, including ther dynamics and dula-loop scheme, will
firstly be given. Sec. 3 reviews PLL motor control speed When LF, loop filter, is of PI-type, as
systems, followed by the dual-loop scheme in Sec. 4. Sec.
5 shows experimental results, and Sec. 6 concludes the
article. (1)

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transfer function , from input phase to feedback In this system, transfer function , from input
phase , can be obtained as follows, phase to feedback phase , can be obtained as fol-
lows,
(2)

where . Steady-state phase error can be ana-


lyzed from the following final value theorem: (6)

where and .
When input signal has the form of Eq. (4), steady
(3) phase error can be zero for frequency ramps with con-
stant acceleration in the input. It is for cases where
VCO gain and motor gain are equal, because:
When input phase signal has three components:
phase step , frequency step , and frequency ramp
,

(4) (7)

Steady-state phase error is zero for and , but


not zero for , because: 3. PLL MOTOR SPEED CONTROL
SYSTEM
(5) 3.1 Basic PLL motor speed control system
2.3 Dual-loop PLL system Block diagram of PLL motor speed control system
is shown in Fig.3, consisting of PD, LF, and the
Dual-loop PLL is intended to be used in fast-
motor with a rotary encoder instead of VCO. Therefore,
moving terminals such as satellites, to solve the problem
of Doppler effect. VCO transfer function alone in Fig.1 is changed to

motor + rotary encoder transfer function .

Fig. 3 Basic PLL motor speed control system

In this system, transfer function , from input


phase to feedback phase , can be obtained as fol-
lows,

(8)

Fig. 2 Dual-loop PLL construction


where .
When input signal has the form of Eq. (4), steady-
In the dual-loop PLL shown in Fig. 2, the first loop
state phase error is zero for and , but not zero for
does not have LF, but the second loop has a filter that
, because:
maintains phase margin. VCO of the second PLL is fed
both by the LF output of the second loop and by the PD
output of the first loop. PLL output is fed by the VCO (9)
of the second loop. It can reject phase error for input
acceleration and track to high speed input, because the
system forms a kind of feed-forward structure.

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3.2 PWM control with active limiter
We implement the PLL/PWM-motor speed control
system employing ’active limiter’ with an FPGA,
a programmable LSI. Fig.4 shows that it can be imple-
mented compactly all in digital.

Fig. 6 Step response of the limited active feed-forward

Fig. 4 PLL/PWM motor speed control employing the 3.3 Circuit implementation
active limiter Two output signals, lag and lead of the phase detec-
tor(PFD), are in PWM, whose duty ratio mean the phase
The circuit in the dashed box is called “active feedfor- error as shown in Fig.7.
ward ” . Fig.5 shows active feedforward scheme. Internal
up-down counter value is moved to the external up-down
counter through the window comparator with relatively
slow speed out enb. That is, external counter is up-
counted when internal counter value is larger than win-
dow range, is down-counted when it is smaller than win-
dow range, and is not counted when it is in window range.
As a result, the internal up-down counter holds AC com- Fig. 7 PFD, phase frequency detector
ponent alone, and the external counter holds DC compo-
nent. By setting the limit value to the internal counter, it The PWM signal can be demodulated, by using the
doesn’t relate to the external counter. It means that the up-down counter, to bit parallel with the integral opera-
limiter can be set to any speed. tion. And the proportional (P) operation is accomplished
by the comparator that switches the proportional gain ac-
cording to duty ratio of lag/lead signal.
For this reason, for very low speed input such as the
one less than proportional gain , only the integral op-
eration is effective. However, since PD is of PFD-type,
this system can be used for any speed (frequency) input
including very low one. It is because it outputs lag signal
only if input frequency is higher than feedback frequency,
and lead signal only if input is lower than feedback.
Fig.8 shows these PWM signal processing for the PI
filter. It shows that the proportional operation is executed
only when lag=1 or lead=1.

Fig. 5 Active limiter

Fig.6 shows step response behavior of this system. It


shows active feedforward effect in range [A], and limiter Fig. 8 PWM signal processing for the PI filter
operation to suppress overshoot.

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4. DUAL-LOOP PLL MOTOR SPEED 4.2 Simulation
CONTROL SYSTEM By MATLAB simulation, it is confirmed that steady-
4.1 Block rearrangement state phase error is going to zero for inputs with con-
stant acceleration (Fig.10). Here, note that those input
The PLL motor speed control system can completely
signals, or ramp phase, is equivalent to constant speed,
reject speed error and steady-state phase errorfor input
and squared ramp is equal to constant acceleration. It is
signals with constant speed. However, it is not usually
similar to motor speed control with acceleration because
applied for cases where input includes acceleration, be-
in both the cases frequency changes with time.
cause its low tracking speed and strange pull-in behavior.
However, to apply the dual-PLL system to motor speed
control system, simple replacement of VCO in the dual-
loop PLL by a motor with encoder (Fig.2) is not enough
for constructing a control system. It is because VCOs
in usual PLLs have input offset, unlike motors in control
systems.
Then, we moved LF to the and paths in feed-
back loop of both the first and second loops as shown in
Fig.9.

Fig. 10 Responses by MATLAB simulation

Another MATLAB simulation confirmed, by the open


loop Bode diagram, Fig.11, that dual loop PLL motor
speed control is derived by adding first and second PLL
together.

Fig. 9 Dual-loop PLL motor speed control

In this system, transfer function , from input


phase to feedback phase , can be obtained as fol-
lows,

(a) first PLL only (b) second PLL(MSC) only


(10)

where and .
When input signal has the form of Eq. (4), steady
phase error can be reduced zero for frequency ramps with
constant acceleration in the input. It is for cases where
VCO gain and motor gain are equal, because:

(c) dual loop PLL MSC


Fig. 11 Open loop Bode diagram of various PLL
(11)

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4.3 Dual-loop PWM control PLL needs capacity as low as 1.7 times more than the
We implement the dual-loop PLL/PWM-motor speed single PLL. Though the active feedforward circuit needs
control system employing ’active limiter’ with an more LEs, performance is not degraded much. Chip uti-
FPGA, a programmable LSI. Fig.12 shows that it can be lization is only 6% even for the most complex dual active
implemented compactly all in digital. case.
In the first loop, NCO, Numerical Controlled Oscilla- Table 1 Circuit performance of PLL motor speed
tor, is used instead of VCO, Voltage Controlled Oscilla- controllers by ALTERA CycloneII(EP2C8Q208C8)
tor. In the second loop, the comparator modulates out-
put of the PI filter to PWM again, and power MOS-FET total LEs VHDL lines Fmax
drives the motor according to its duty ratio. single 155 289 156MHz
dual 263 450 131MHz
single active 238 455 114MHz
dual active 520 679 101MHz

It was confirmed that lock is achieved by setting ro-


tational speed with the programmable divider for all the
possible speeds.
5.1 Phase error for inputs with acceleration
Oscilloscope observations revealed that steady-state
phase error goes to zero for input with constant accel-
eration (Fig.14) .

phase lag occurs

no phase lag occurs


Fig. 12 Dual loop PLL/PWM motor speed control sys-
tem employing the active limiter

The key component of this circuit is “loop adder,” op- Fig. 14 Waveforms (for input acceleration)
erating on PWM signals from digital PD(PFD). Fig.13
shows loop adder operation. It is a 4-input 1-bit adder. 5.2 Responses to step-like changes in input frequency
We will show frequency step responses obtained from
F/V-converted motor encoder output.
Performance of single loop system
As the basis for comparison, performance of the
single loop PLL motor speed control system was ob-
served. Fig.15 obviously shows that active feedfor-
ward circuit improves rise up time. Correct limiter
operation is also seen.

Fig. 13 Loop adder operation

5. EXPERIMENTAL RESULTS
The circuit of Fig.12 was programmed in a single-chip
FPGA and was experimented.
Table1 shows circuit performance implemented by
ALTERA CycloneII(EP2C8Q208C8). This FPGA,
though it is small-scale, uses only less than 10% LEs,
logic elements. Because PWM signal operation is very Fig. 15 Single-loop experiments
simple, it can be operated at 100MHz or higher. The dual

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Performance of dual loop system
Next, dual loop PLL motor speed control system
was observed. Fig.16 obviously shows that this sys-
tem improved rise up time of the single-loop one
with and without active feedforward.
Also, it maintains its property of canceling the
phase error in acceleration.
In addition, correct operation of limiter is seen
to suppress strange overshoot caused by excessive
feedforward. It is because the dual loop scheme is a
kind of feed-forward structure.

Fig. 18 Effect of the outside enable frequency and lim-


iter

loop PLL for satellite communication is applied.


Since motor rotate direction should follow the sign of
the input, we inserted loop filters into both feed back
paths, and employed a special adder in PWM to imple-
ment loop addition for the two phase detector outputs.
Supplemental techniques, called “active feedforward”
and “active limiter,” are also incorporated, to achieve
Fig. 16 Dual-loop experiments faster tracking and speed limitation.
Several experiments with an FPGA implementation
Influence of change in limit value confirm that steady-state phase error for accelerated and
When limit value is less than the upper limit line high-speed inputs can be rejected. It is because the sys-
of window comparator, Fig.17 shows no overshoot tem forms a kind of feed-forward structure.
at any speed. Of course, output motor+encoder In PLL motor speed control systems, PID-type loop
frequency doesn’t reach reference input frequency. filter can improve disturbance sensitivity . In the near
However, in this situation, the external counter can future we will investigate this in the dual-loop control.
make up offset DC component, because it can be
scheduled, if it is already known. REFERENCES
[1] R.E. Best:Phase-Locked Loops 6th.ed.,McGraw-
Hill (2007)
[2] J.X. Shen and S. Iwasaki; Sensorless control of
ultrahigh-speed PM brushless motor using PLL and
third harmonic back EMF, IEEE Trans., Vol. IE-53,
Issue 2, pp. 421–428 (2006)
[3] Yoon Yong-Ho et al.: PLL control algorithm for
precise speed control of the slotless PM brushless
DC motor Using 2 Hall-ICs, 35th IEEE PE Special.
Conf., Vol. 2, pp. 1315-1321 (2004)
[4] J. Deskur and A. Maciejuk: Application of digital
phase locked loop for control of SRM drive, IEEE
Fig. 17 Effect of change in limit value Europ. Conf. Power Electron. Appl., pp. 1-6 (2007)
[5] M. Kamata, et al.: Third-order phase locked loops
Influence of outside enable frequency and limiter using dual loops inserting an active filter in the
Fig.18 shows the effect of the outside enable fre- second loop with improved stability, IEICE-A,
quency and limiter. When outside enable frequency Vol. J82-A, No. 2, pp. 273–282 (1999)
increased, rise up time is improved, while hunting [6] H. Machida and F. Kobayashi: PLL/PID motor con-
behavior occurs when it is excessive. trol system by using time-domain differential op-
However, the limiter can improve this behavior, eration of PWM signal, IEEJ-C, Vol. 127, No. 5,
resuming normal behavior. pp. 801–802 (2007)
[7] H. Machida et al.: A realization of the dual loop
6. CONCLUSION PLL/PWM motor control system by employing the
In order to solve the steady-state phase error problem active feed-forward, IEEJ-D Ann. Conf., (to appear,
for accelerated inputs in PLL motor speed control, dual- 2009)

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