Canadian Journal on Electrical & Electronics Engineering Vol. 1, No.
7, December 2010
Device and Circuit Design Challenges for Low
Leakage SRAM for Ultra Low Power
Applications
Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik, R.K.Singh
Abstract - Ultra low-power applications have
gained a lot of attention in recent years. This is due
to the increase in battery operated devices and also
due to the scaling of CMOS devices. Various CMOS
circuits of low-leakage are in demand one of them is
the SRAM. So, at the present scenario various
technologies are used to design the low leakage
SRAM. The low leakage SRAM are of prime
concerned as 30% of the total chip consumption is
due to memory circuits. This paper deals with the
various device & circuit design challenges to
optimize the low leakage SRAM with various design
methodologies and circuit topologies for optimal low
power operations. This paper identifies the suitable
candidates for low leakage SRAM for ultra low
power applications at device and circuit levels and
provides an effective road-map for SRAM designers
to work with its ultra-low power applications.
Key Words – Ultra-Low Power, CMOS Scaling,
Leakage Power, Static Noise Margin.
I. INTRODUCTION
In recent years the demand for low power devices
has been increases tremendously. This demand may
be due to fast growth of battery operated portable
applications such as PDAs, cell phones, laptops &
other handheld devices. But also at the same time
problems arising from continuous technology scaling
have recently made power reduction an important
design issue for the digital circuits and applications.
The increased importance of power is even more
noticeable for a new class of energy constrained
systems. Recent interest is in operating the CMOS
circuits with power supply voltage below the
transistor threshold operation [33]. As sub-threshold
circuits can allow ultra low power designs to be
fabricated on modern process technology. Sub-
threshold operation is applicable to wide range of
applications ranging from wireless devices,
biomedical applications, spacecraft applications etc.
Lowering supply voltage to reduce power
consumption is one of the choice of the designers for
designing low leakage SRAM circuits. However ultra
low power design of high density SRAMs in which
the operating voltage is below the transistor sub-
threshold is extremely challenging. In modern SoCs
where total power and total area is dominated by
memory circuits reductions in Vdds for them
(memory circuits) can have low leakage power [26].
Also by the system integration point of view, SRAM
must be compatible with sub-threshold combinational
logic, operating at ultra low voltages. Ultra-Dynamic
Voltage Scaling (U-DVS) is another approach to
reduce energy consumption by adjusting the system
supply voltage over a large range, depending on the
performance requirement. U-DVS is suitable for
systems with time-varying throughput constraint.
This paper is organized as follows; the scope of
the low leakage SRAM for ultra low power
application is presented in section II. Various
challenging issues of the current and the future
SRAM cell is reviewed in section III. Section IV
present various device level optimization
methodologies for low leakage SRAM. Section V
shows the various circuit topologies for low leakage
SRAM cell for ultra low power applications. Finally
conclusion is drawn in section VI.
II. SCOPE OF LOW LEAKAGE SRAM FOR ULTRA
LOW POWER APPLICATIONS
Besides the quadratic dynamic power savings,
very low supply voltages promise greatly reduced
leakage power. For example, a 1-V reduction in the
supply voltage can reduce Ioff the transistor leakage
current, by over one decade due to the drain-induced
barrier-lowering (DIBL) effect. The gate oxide
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010

leakage can also be reduced more than 100x with the
same 1-V drop in supply voltage.
Various low leakage applications for ultra-low power
operations are,
A. Energy-constrained applications such as wireless
sensor nodes, RFID tags, medical equipments such as
hearing aids and pace-maker, wearable computing or
implants, Personal digital assistants, energy
scavenging applications, and Laptops, which are
dominated primarily by the need to minimize energy
consumption and increase battery life time, speed is a
secondary consideration for this class of applications,
so sub-threshold circuits offer a good solution [13].
B. Battery-powered handheld systems have been
faster than other integrated circuit applications such
as cell phones, MP3 players, and portable games. All
benefits from increased battery life, with lowering
integrated circuit (IC) power dissipation are provided.
In modern system-on-chip (SoC) devices, some
components, such as digital signal processors and
microprocessors, must operate at high frequencies, at
least intermittently. Many components do not need to
run as fast, but must be integrated on the same high-
performance silicon die. Additionally, some
applications require a small subset of the circuits to
operate continuously, e.g., real-time clocks and
wakeup circuitry.
The on-chip temperature gradients induced by
imbalanced switching activity are therefore typically
small across the die of a low-voltage integrated
circuit. Die temperature fluctuations due to the
variations in the ambient temperature however can
cause significant fluctuations in the speed and the
power characteristics of ultra low-voltage circuits.
B. Power Overhead associated with Change in
Supply Voltage:
Power overhead associated with changing the
supply voltage level should at least be compensated
by the energy savings in the low-voltage mode. So,
understanding the energy required to change the
supply voltage level is necessary as energy overhead
is a fundamental issue and cannot be avoided.
C. Effect of Transistor Mismatch:
The main challenge for low-voltage operation is
that relative sizing of transistors is a weak knob due
to the exponential dependence of drive current on
threshold voltage in sub-threshold region. The basic
and most important building block of a traditional
SRAM, 6T bit-cell is a ratioed structure and its
correct operation depends on relative strength of its
transistors. Fig.1 shows the effect of access transistor
drive strength on Write Margin (WM) distribution for
a 6T SRAM cell at different supply voltages.

III. CHALLENGING ISSUES FROM THE CURRENT

AND THE FUTURE LOW LEAKGE SRAM CELL

We have identified various device and circuit

design challenges which need to be addressed for
advancing the in sub-threshold circuit design,
emphasizing the need for co-design at all levels of
abstraction like device, circuit and architecture, and
so forth. This section provides an interesting insight
and challenges for designers interested to work with
energy-constrained applications.
A. Sensitive to Process and Temperature Variation:

Integrated circuits with ultra low-voltage power

supplies are highly sensitive to process and
Fig.1Effect on Write Margin
temperature variations. The absolute value of the
MOSFET threshold voltage degrades and the thermal
However, at low voltages, the effect of sizing is
voltage is enhanced as the temperature increases. A
negated by transistor mismatches. Hence, a solution
small increase in the die temperature exponentially
relying on only transistor sizing can be suitable for
enhances the sub-threshold leakage current. Contrary
high-voltage operation but is insufficient for low-
to the standard higher-voltage circuits designed for
voltage functionality.
high-speed, low-voltage circuits optimized for
minimum energy operate faster when the die
temperature increases [13].
D. Degradation of Ion/Ioff

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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
The degradation in Ion/Ioff from 107
approximately to 104 implies that, in sub-Vt , there is
a strong interaction between the “on” and the “off”
devices when it comes to setting the voltage level of
critical signals. This introduces a relevant failure
mechanism where SRAM density requirements call
for the integration of many devices on shared nodes
[13].
E. SER (Soft Error Rate)
An issue for deeply voltage scaled SRAM is soft
error rate (SER). Soft errors occur when an alpha
particle or cosmic ray strikes a memory node and
causes data loss. Since, bitcell storage capacitance
decreases with scaling and voltage scaling further
reduces the stored charge, SER is a concern for sub-
threshold memory [33].
F. Cell Stability
Static Noise Margin (SNM) is the maximum
amount of noise that is tolerated at the data storage
nodes of an SRAM cell. The voltage transfer
characteristics (VTC) of two cross-coupled inverters
are shown in Fig.2. The resulting curve is called the
‘‘butterfly curve’’. The SNM is the length of the
largest square that can be embedded inside the lobes
of a butterfly curve, as illustrated in Fig.2.
Fig.2 Butterfly Curve [20]
As described in [15, 16, 19, 20], for the memory
circuits operating in the super threshold (strong
inversion) region, the read static noise margin
increases with an increase in the memory cell ratio.
The memory cell ratio is the ratio of the pull-down
NMOS transistor width to the access transistor width
(WN1/WA1 or WN2/WA2 where W is the width of
the corresponding device in the 6T-SRAM bit-cell).
As the supply voltage is scaled to the sub-threshold
region, the dependence of the data stability on the
SRAM cell ratio becomes negligible.
158
The reason for the diminishing sensitivity of the
read static noise margin to the transistor sizes at
scaled supply voltages is identified. The switching
current at ultra-low voltage is the sub-threshold
leakage current. The sub-threshold leakage current
produced by a MOSFET is [7].
Where, Ileak, µ, Weff, COX, Leff, Vt, VT, VGS, VDS, and
n are the sub-threshold leakage current, carrier
mobility, effective transistor width, oxide capacitance
per unit area, effective channel length, threshold
voltage, thermal voltage, gate-to-source voltage,
drain-to-source voltage, and sub-threshold swing
coefficient, respectively. For devices operating in the
weak inversion region, the switching current is
exponentially dependent on the voltage levels [15,
16]. Alternatively, increasing the device width
produces only a linear increase in the switching
current. A linear change in the sub-threshold
switching current has a relatively small impact on the
voltage transfer characteristics. The sensitivity of the
read noise margin to the memory cell ratio is
therefore negligible in an ultra-low supply voltage,
i.e., sub-threshold memory circuit.
7. Device Scaling:
Device scaling offers a reduction in gate
capacitance and at super sub-threshold voltages, it
offers a reduction in switching energy and gate delay.
Scaling leads to increase in density but at the same
time device scaling brought many problems like
increased sub-threshold and gate leakage. Due to
exponential sensitivities to Vth and Vdd in sub
threshold regime, circuit may work properly under
device scaling.
IV. VARIOUS CIRCUIT OPTIMIZATION
METHODLOGIES FOR LOW LEAKAGE SRAM CELL
There are various methods by which we can
reduce the leakage current in order to optimize the
power reduction. One of them is the biasing schemes
which help in reducing the leakage currents in
SRAM.
1. Various Biasing Schemes
(a). Source Biasing Scheme
This leakage reduction technique increases the
line voltage in sleep mode operation to generate a
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010

negative Vgs in the access transistor and reduce the

bit line leakage, as shown in Fig.3. The reduced
signal rail, bit line leakage and the body effect in the
transistor lowers the sub-threshold leakage in the
SRAM cell. Gate leakage is also reduced as the
source voltage is reduced. But it imposes delay
penalty as an extra NMOS is required and also causes
the SER (soft error rate) to rise which directly has an
impact on stability [1-4].

Fig.5 Dynamic Voltage Supply [1]

(d). Floating Bit Line.

This technique has the bit lines, floating during

Fig.3 Source Biasing Scheme [10]
(b). Reverse Body Biasing Scheme
In this technique NMOS or PMOS reduces the
sub-threshold leakage in sleep mode via body effect
Fig.4. Due to zero body bias in active mode the
access time remains the same. This scheme is less
effective in deep sub-micrometer and it also increases
the junction band to band tunneling leakage current
[3, 5, 6].
the standby mode and reduces the bit line leakage via
DIBL. This scheme (Fig.6) cannot be applied to
individual cache lines, since the bit line is shared
across different cache lines. Normally, bit lines have
to be precharged and ready for the word line access.
Since the bit lines are floating for this technique, an
extra precharge cycle is required whenever a new
sub-array is accessed. No delay rise and no impact on
SER is observed [8].

Fig.6 Floating Bit Lines [1]

(e). Negative world line scheme

Fig.4 Reverse Body Biasing Scheme [10]
In this technique it has been propped to cut off the
(c). Dynamic Voltage Supply sub-threshold leakage through access transistors by
using a lower voltage in cells and bit lines (Fig.7).
In this scheme, the supply voltage is lowered to Although this technique has no impact on the
reduce the leakage; however, the bit line leakage performance or on SER but there is dynamic power
cannot be reduced in this, as the bias condition in the overhead for creating the negative voltage [9].
access transistor does not change Fig.5. This has a
larger transistor overhead and has substantial
increment in SER [3, 7].
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
Fig.7 Negative Word-line Scheme Lines [2]
(f). Forward Body Biasing
In this technique, the NMOS or PMOS transistors in
the selected sub array are dynamically switched from
zero body bias to forward body bias. Forward body-
biasing (FBB) has proven to effectively improve
performance, suppress short channel effects, and
reduce variations, roll-off. The drain-induced barrier
lowering (DIBL) which limits scalability of channel
length can also be relieved by FBB during the normal
operation of the device. As alone this technique does
not reduce the gate current but along with super high
Vt it is able to do so [10].
(i). Forward Body Biasing with Super High Vt
Here, the device optimization is achieved using
super halo 2-D doping profile. This profile uses a non
uniform P+ doping profile in the source body and
drain body boundaries to reduce the source drain
depletion width and effectively suppresses the body
punch through. The Vth roll and DIBL are also
controlled by 2D halo doping profile. The high Vt
doping profile is generated by raising the halo doping
concentration of the nominal Vt device.FBB is
dynamically applied to only the active portion of the
cache for fast read and write operation. The two-
dimensional (2-D) halo doping profile of a super high
device to achieve total leakage reduction, while
suppressing the gate leakage and junction band-to-
band tunneling (JBTBT) leakage. In this scheme
using a super high device and FBB is used to
dynamically reduce the active leakage in cache
memories.
The only limitation is that the technology where
higher halo doping is unacceptable, a super high Vt
device can be built using a gate material with a
higher flatband voltage. The simulation results shows
that a 32X 32 sub-array of SRAM is designed and
simulated at 70nm technology in which total 64%
160
reduction is shown as compared to source biasing and
16% as compared to conventional SRAM [10,21,28].
Fig.8.Forward Body Biasing [10]
(g). Active/Passive Clamped Transistor Scheme
(i). Passive clamped transistor scheme:
A passive clamped bias design uses digitally
programmable transistors which are used to set the
virtual ground voltage during standby. This
programming has to set for worst case, ie, maximum
SRAM leakage under process variation conditions.
As aging can change the device on and off
characteristics so this makes a passive clamp
transistor scheme less effective in reducing cache
leakage power [11].
(ii). Active Clamped Transistor Scheme
There are various actively clamped bias schemes
which minimize the standby power of the memory.
One of them is using replica cell bias generator to
derive the gate voltage of the bias device. This
scheme tracks the process variations in Vss value.
The other proposed scheme is a linear voltage
regulator which is used to derive the Vss to a given
programmable Vmin value. This results in excellent
PVT and aging tracking but if see the other side it
results in larger penalties of area and dynamic power
overhead to switch between active and standby
voltage levels [32].
A new scheme is proposed in which a combined
distributed sleep and active clamp scheme is used
which incurred less than 3 % are overhead and active
clamping has 14% less leakage than for passive bias
and sleep transistors. It helps in reducing the leakage
power of idle sub-arrays by 30-60% at 0.8-1.0 V
standby. A 256kb dual Vcc SRAM has been
simulated which operated between 2.3-4.2GHz with
16-29mw total power consumption at 85oC. It has
fixed 1.2 fixed Vlcc and 0.7-1.2 Vcore [15].
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Another approach is using the combination of
FBB with Vt using 2D super halo technique and
Active clamped transistor. This approach is used so
that FBB technique is used for fast operation and
clamped transistors with high Vt is used to reduce the
leakage [10].
(2). High-K Metal Gate Technology
In this proposed technology the “high-k" (Hi-k)
material is used to replace the transistor's silicon
dioxide gate dielectric, and new metals to replace the
polysilicon gate electrode of NMOS and PMOS
transistors. These new materials, along with the right
process recipe, reduce gate leakage more than 100-
fold, while delivering record transistor performance.
Along with this PMOS FBB technique is used for
lower voltages. The stronger PMOS under the FBB
can improve the minimum operating voltage up to 75
mV. This improvement is achieved without
increasing the overall SRAM leakage power, since
the Nwell is restored back to Vcc after the WL
(wordline) is turned off. The active power
consumption per access due to dynamically
discharging and charging the Nwell is less than 1% of
the total access power, where significant portion of
the active power during cache access is from signal
and clock distributions. The leakage current is
reduced by 10x. The operating frequency of 153 Mb
SRAM using this technology at 45nm is 2.7 GHz at
0.9V and 3.8 GHz at 1.1V.The limitation is that it
degraded the write margin [17].
(3). Dual Rail Mechanism
Several design solutions for Vdd minimum issues
were proposed for the single rail at 65 nm and 45 nm
SRAM. The suppressed word-line (WL) scheme was
reported to address the bit cell SNM issue caused by
the ever increasing device variations in the shrinking
devices. This scheme can improve the SNM, but it
causes an unacceptable cell current degradation in the
lower Vdd regime. The cell current degradation, in
turn, becomes the limiter of Vddmin. The area is
increased to maintain an acceptable cell current. To
avoid this area penalty, dual-rail SRAM designs in 65
nm were proposed. The dual-rail design with a
dedicated SRAM power source, Cell-Vdd (CVdd),
can achieve a lower Vddmin, but the challenge lies in
the large current consumption of the CVdd power
source. The large CVdd current implies large areas
which are needed to implement numerous CVdd
voltage regulators, and wider power lines to mitigate
the CVdd IR-drop issue. IR drop constraints as well
as the area penalty results from the power routing.
However, fixing the CVdd voltage level would limit
the Vddmin reduction because scaling down the Vdd
161
would cause a large voltage difference between the
CVdd and the Vdd [18].
In order to further improve the Vddmin, an
adaptive CVdd voltage regulator, which generates a
desired offset with respect to Vdd, is proposed. In
this mechanism a dual rail Vdd is used to generate
logic Vdd and cell Vdd, so that logic Vdd is reduced
to 0.6V. The Vddmin is lowered and also the area
required has been reduced. This technique is also
extendable to new process technologies upto 32nm.
But it degraded the SNM as when the Vdd is scaled
down ,the offset voltage is increased due to which the
SNM degrades [18].
Fig.9 Maximum Offset Voltage Limitation versus Different
Process Generations [18]
Fig.9 shows the maximum offset voltage
limitation versus different process generations. It
shows that the maximum offset voltage is getting
lower as the device shrinks from 65 nm to 32 nm
technology nodes. That is because the SNM is also
getting lower as the device scales down. This trend
will also make the proposed Vdd-tracking CVdd
concept more attractive in the future technology
nodes. 1 Mb SRAM is tested and the area has been
reduced to 5%. Vdd is 0.74V-0.9V and Vddmin of
0.6 V is achieved.
(4). Low Vdd Operation and Increase in the Vth
Scheme
For high speed applications and low Vdd
operation, a new scheme is used in which the Vth of
the has been increased. The supply voltage, ie, Vdd
has been reduced to 0.5V and the access time is also
reduced to 20ns when a 64 kb SRAM is simulated at
90nnm technology. But at lower voltages of Vdd
write operation cannot be performed and also leakage
current of PMOS transistors results in storage
destructions [20].
(5). Dual Boosting Scheme
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
In this scheme internally boosting of the voltage
level of the word line and cell power node is done
which increases the driving capability of the NMOS
access transistor during read operation and reduces
the bit line delay because of Icell increases during
this operation. It increases the Read SNM and write
SNM at low voltages. The operating frequency is 50
MHz but it has been observed that it results in
overhead of area and power. It has been observed that
during the simulation of 256kb SRAM the area
overhead is 4.5% due to cell boosting and reduction
in chip cycle by 26% at the expense of 14.6%
additional power. The cell ratio is also of prime
concern which is kept one. [23, 26].
(6). Novel Write Mechanism
In this scheme a write mechanism is proposed
which depends only on one of the 2 bit lines to
perform the write operation. Transistor sizing is also
of prime concerned in this mechanism for cell
stability. It also uses the sleep transistors but the
overall leakage power is slightly higher than
conventional SRAM and the cache are is also
increased by 12.25 % from the conventional SRAM.
A trade off is maintained between the SNM and the
leakage power. As high Vt PMOS are used which
helps in reducing the leakage but reduces the SNM
[21, 28, 32].
(7). Sense Amplifier Redundancy Mechanism
Here, a charge pump is used to resolve the zero
leakage read buffer footer. A high density 8T SRAM
is simulated with minimum operating voltage of
350mV. But speed is of concern in this technique
which decreases. Also the cell stability is decreased
[29].
(8). Dual Vth & Dual Tox Scheme
In this scheme different combinations of
transistors with dual Vth and dual Tox have been
used to design the various 6T SRAM cells. It reduces
both sub-threshold and gate tunneling leakage
current. This technique is useful in increasing the
SNM also. Various combinations have been observed
to have the best results [35].
(9). Self Write Back Sense Amplifier Scheme
Self write back sense amplifier is used with
capacitance separator. In it a cascaded bit line scheme
is used as the access time of the proposed scheme is
proportional to the number of sense amplifiers. It is
preferred for low SRAM macros. The proposed
scheme is advantageous for smaller macro, for bit
capacity is less than 256 kb the timing margin for
sense amplifier enable signal is unnecessary for
162
shorter BL arrays. The cascaded bit line scheme
minimizes the area penalty. It also realizes read and
write operation without global lines. It is useful for
low voltage operation [23].
(10). Uni-axial Si Strained Technology
In this technique, the uni-axial Si strained
technology, the nitride films are deposited on Si to
act as the contact etch stop layer (CESL). In this 65
nm process, strong uniaxial tensile strain is created
by the nitride layer in order to increase NMOS
mobility. The amount of strain increases with the
thickness of the nitride layer that can fill between the
gates and the amount of contact of the nitride film
with the source/drain region. The 65 nm strained
silicon technology improves transistor
performance/leakage tradeoff, which is essential to
achieve fast SRAM access speed at substantially low
operating voltage and standby leakage. The 1 Mb
SRAM macro features a 0.667 µm2 low-leakage
memory cell and can operate over a wide range of
supply voltages from 1.2 V to 0.5 V. It achieves
operating frequency of 1.1 GHz and 250 MHz at 1.2
V and 0.7 V, respectively. This technology has been
successful for future process technologies also [14].
The above techniques are used to reduce the
leakage and increase the stability of the cell. But
there are other technique which depends on the
number of transistors in a SRAM cell to increase the
stability and reduce the leakage.
(11). Gate Feedback Memory Cell
In this scheme a gate feedback memory cell is
used for SRAM in which the decoder circuits is
separated from read circuits. The power consumption
was low, 0.83µw dynamic power consumption and
0.197 µw static power consumption while simulating
a 512x13 bit SRAM memory cell at 130nm. The
limitation was that it has almost vanishing read
stability at low voltages and also speed was the
limitation [13].
(12). Stacking Effect
In this scheme half stacking and full stacking
effects is used to design a conventional 6T SRAM
cell for low leakage reduction. There is drastic
change in power consumption in full stack effect but
the main limitations are area overhead and SNM
degraded. At 130 nm the results are fine but as the
gate length is reduced power consumption also
increases. It has been shown that the stacking of two
off transistors can significantly reduce leakage power
than a single off transistor [37]. Increasing the source
voltage of NMOS transistor reduces sub-threshold
leakage current, exponentially due to negative Vgs,
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010

lowered signal rail, reduced DIBL and body effect. V2 remains large even when access MOS transistor
This effect is also called self-reverse biasing of N3 is turned on and Node V1 voltage increases.
transistor the self-reverse bias effect can be achieved
by turning off a stack of transistors. Turning off more
than one transistor in a stack raises the internal
voltage (source voltage) of the stack, which acts as
reverse biasing the source. The voltages at the
internal nodes depend on the input applied to the
stack [16].

Fig.11 7T SRAM Cell [20]

The worst normalized Read SNM and normalized

Icell values improve, respectively, to 1.24 and 0.54.
A minimum supply voltage (Vdd-min) of 440 mV
and a 20 ns access time are achieved with a 0.5 V
supply voltage. In this SRAM, Vdd-min is limited by
Fig.10.6T SRAM using Stacking Effect [16] the following two factors: 1) Write operations at low-
Vdd levels cannot be performed, since write margin
decreases with decreasing Vdd. 2) Read operations at
low-Vdd levels result in storage data destruction in
V. VARIOUS SRAM CELL TOPOLOGIES FOR LOW SRAM cells due to the leakage current of PMOS
LEAKAGE SRAM CELL transistor P2.[20]
Although the 6T SRAM cell with above
mentioned technologies have been implemented for a
better performance but it has some of the limitations.
The conventional SRAM fails at many aspects so,
various other topologies of SRAM are being
discussed here for low leakage SRAM.
(1) 7T SRAM Cell

Here a 7T SRAM cell (90nm technology) a data

protection NMOS transistor N5 has been added
between Node V2 and NMOS transistor N2. While
the SRAM cell is being accessed, /WL is in the
activated state, “0”, and N5 is OFF. Since N5
prevents the voltage at Node V2 from decreasing, the
data bit is not reversed even if Node V1 voltage Fig.12 Vdd-min Temperature Dependence [20]
greatly exceeds Fig.11.
Fig. 12 shows Vdd-min dependence on
During data retention period, when the SRAM cell is temperature. Below 85oC, Vdd-min decreases with
not being accessed, word line signal /WL is “1”, and increasing temperature. This occurs because Vdd-min
NMOS transistor N5 is ON. The use of two CMOS is determined by factor: (a). Write margin, unlike
inverters results in high cell stability. During Read Read SNM, improves with decreasing Vth levels in
operations, the logical threshold voltage of the NMOS transistors, and Vth decreases with increasing
CMOS inverter driving Node V2 increases greatly temperature. VDD-min, which will not improve even
when the data protection NMOS transistor N5 is if the temperature exceeds 85o C, will be determined
turned off. For this reason, the Read SNM value at by factor (b).The leakage current of PMOS transistor
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Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
P2 increases with increasing temperature. This
reverses the relationship between BL delay time and
retention time. Since, both Write margin and SRAM
cell current improve with decreasing Vth levels in
NMOS transistors; it will be possible to achieve even
higher speeds and lower-VDD operations by
reducing Vth levels below 0.32 V, the value currently
achieved.
(2). 7T dual Vt SRAM Cell
The circuit schematic of the 7T dual-Vt SRAM
cell with transistors sized for a 65nm CMOS
technology is shown in Fig.13. The cross-coupled
inverters formed by the transistors N1, P1, N2, and
P2 store a single bit of information. The write bitline
WBL and the pass transistor N3 are used for
transferring new data into the cell [36].
Alternatively, the read bitline RBL and the
transistor stack formed by N4 and N5 are used for
reading data from the cell. Two separate control
signals R and W are used for controlling the read and
the write operations, respectively, with the 7T SRAM
circuit as shown in Fig. 13.
Fig.13 7T Dual Vt SRAM [36]
(3). 8T SRAM Cell
The schematic of the 8T SRAM cell sized for a
65nm CMOS technology is shown in Fig. 14. The left
sub-circuit of the 8T memory cell is a conventional
6T SRAM cell with minimum sized devices
(composed of N1, N2, N3, N4, P1, and P2). Two data
access transistors (N3 and N4) and two bitlines
(WBL and WBLB) are used for writing to the SRAM
cell. An alternative communication channel
(composed of a separate read bitline RBL and the
transistor stack formed by N5 and N6) is used for
reading the data from the cell. Two separate control
signals R and W are used for controlling the read and
the write operations, respectively, with the 8T SRAM
circuit as shown in Fig. 14. During a read operation,
the read signal R transitions to Vdd while the write
signal W is maintained at Vgnd [36].
164
Fig.14 8T SRAM Cell [36]
The read bitline (RBL) is conditionally
discharged based on the data stored in the SRAM
cell. The storage nodes (Node1 and Node2) are
completely isolated from the bitlines during a read
operation. Data stability is thereby significantly
enhanced as compared to the standard 6T SRAM
cells [29].
(4). 9T SRAM Cell
The schematic of the 9T SRAM cell, with
transistors sized for a 65-nm CMOS technology, is
shown in Fig. 15. The upper sub-circuit of the 9T
memory circuit is essentially a conventional 6T
SRAM cell with minimum sized devices (composed
of N1, N2, N3, N4, P1, and P2).
Fig.15 9T SRAM cell [36]
The two write access transistors (N3 and N4) are
controlled by a write signal (WR). The data is stored
within this upper memory sub-circuit. The lower sub-
circuit of the new cell is composed of the bit-line
access transistors (N5 and N6) and the read access
transistor (N7). The operations of N5 and N6 are
controlled by the data stored in the cell. N7 is
controlled by a separate read signal (RD). During a
write operation, WR signal transitions high while RD
is maintained low. N7 is cutoff. The two write access
transistors N3 and N4 are turned on. In order to write
a “0” to Node1, BL and BLB are discharged and
charged, respectively. A “0” is forced into the SRAM
cell through N3. Alternatively, for writing a “0” to
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
Node2, BL and BLB are charged and discharged,
respectively. A “0” is forced onto Node2 through N4.
During a read operation, RD signal transitions high
while WR is maintained low. The read access
transistor N7 is activated. Provided that Node1 stores
“1”, BL is discharged through N5 and N7.
Alternatively, provided that Node2 stores “1”, the
complementary bitline (BLB) is discharged through
N6 and N7. Since N3 and N4 are cutoff, the storage
nodes Node1 and Node2 are completely isolated from
the bitlines during a read operation [36].
Leakage Power Comparison of the three Topologies
(7T, 8T, and 9T)
The leakage power consumption of the SRAM
circuits is shown in Fig. 16. The leakage power of an
SRAM cell is determined by the total effective
transistor width and the threshold voltages of the
transistors that produce the leakage current.
Transistor sizing for enhanced data stability comes at
a cost of significant additional leakage power with
the standard full-voltage-swing 6T SRAM circuits.
The leakage power is doubled when β is increased
from 1 to 3 with the standard 6T SRAM circuit, as
illustrated in Fig. 16.
The dual-Vt 7T SRAM cell consumes the lowest
leakage power by utilizing minimum sized high-Vt
transistors in the cross-coupled inverters. The leakage
power of the dynamic wordline voltage swing
technique, the 9T SRAM cell, the 8T SRAM cell, and
the dual-Vt 7T SRAM cell is reduced by 51%, 23%,
21%, and 57%, respectively, as compared to a
standard 6T SRAM cell sized for read stability
(β=3)[34].
Fig.16 Leakage Power Consumption [34]
(5). 10T SRAM cell
Fig. 17 shows the schematic of the 10T sub-
threshold bitcell. Transistors are identical to a 6T
bitcell except that the source of M3 and M6 tie to a
165
virtual supply voltage rail Vdd. Write access to the
bitcell occurs through the write access transistors, M2
and M5, Transistors from the write bitlines, BL and
BLB. Transistors M7 through M10 implement a
buffer used for reading. Read access is single-ended
and occurs on a separate bitline, RBL, which is
precharged to prior to read access. The wordline for
read also is distinct from the write wordline. One key
advantage to separating the read and write wordlines
and bitlines is that a memory using this bitcell can
have distinct read and write ports.
Fig.17 10T SRAM Cell [33]
At 27oC, the 10T memory saves 2.5X and 3.8X
in leakage power by scaling from 0.6 V to 0.4 V and
0.3 V, respectively and over 60X when scales from
1.2 V to 0.3 V, scaling also gives the expected
savings in active energy per read access.
(6). 11T SRAM Cell
The schematic diagram of the proposed 11T-
SRAM bitcell. Transistors M2, M4, M5, and M6 are
identical to 6T-SRAM, but two transistors M1 and
M3 are downsized to the same size as the PMOS
transistors.
The bitline and word line are distinct from the
write word line. In this case, memory can have
distinct read and write ports. During the hold time,
RDWL and WL are not selected. In the 6T-SRAM
part, suppose that node Y stores “0” and node X
stores “1” as was described for the 6T-SRAM part in
the previous section. For the added circuitry the
following behavior is observed when transistor M12
is turned off. Also, the M11 state is dependant of the
voltage in node Y. If node Y stores “1”, then M8
connects the gate of M11 to ground, so M11 is turned
off. However, if node Y stores “0”, M9 is turned off
and it starts to charge the gate of transistor M11.
Therefore there is a leakage path through M11
that connects the node YN to zero. Minimum size
transistors were used for the added 5T-circuitry,
except the access transistor that has a larger size. The
Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010
most important part of the 11T-SRAM is a boost
capacitor (CB) that connects source of M9 to RDWL.
Fig.18 11T SRAM Cell [25]
VI. CONCLUSION
As low leakage SRAM will continue be in
demand due to rise in battery operated portable
applications and also due to continuous scaling of
CMOS. So, new approach should be involved to
reduce the leakage application. Device optimization
is a must for low leakage SRAM to further reduce
power and enhance performance. Also area and cell
stability should be taken care while optimizing the
power reduction. Various optimization techniques
has been proposed which can be effective in recent
technologies .These techniques can be implemented
in various SRAM transistor cells which overall
increase the performance. As higher order transistors
are able to solve the problems of conventional 6T so
we can go forward and also the area overhead will be
at the same time is minimized as the scaling of
CMOS is continued. The leakage reduction can be
done by the various optimization techniques
suggested in the papers and for stability enhancement
we can choose the SRAM cell topology. The Dual
rail mechanism techniques discussed in this paper
will also work for lower technology till 32nm.The
recent technologies like High K metal gate
technology is efficient for the lower CMOS
technologies till 22nm.So we can implement the
these techniques in context of present and future
technologies and can enhance the stability and reduce
the leakage current.
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BIOGRAPHIES
Shilpi Birla, a Ph.D. Scholar at the UK Technical University,
Dehradun (Uttarakhand) India. She is an Asst. Professor in the
Department of Electronics & Communication Engineering, Sir
Padampat Singhania University, Udaipur (Rajasthan) India. She
has received her M.Tech. (VLSI Design) and B.E. (Electronics &
Communication Engineering) Degrees from the University of
Rajasthan, Jaipur (Rajasthan) India and MITS University,
Laxmangarh, (Rajasthan) India, respectively. Her main research
interests are in Low-Power VLSI Design and its Multimedia
Applications, RF-SiP, and Low-Power CMOS Circuit Design.
Neeraj Kr. Shukla (IEEE, IACSIT,IAENG, IETE, IE, CSI,
ISTE), a Ph.D. Scholar at the UK Technical University, Dehradun
(Uttarakhand) India.He is an Asst. Professor in the Department of
Electrical, Electronics & Communication Engineering, ITM
University, Gurgaon, (Haryana) India. He has received his
M.Tech. (Electronics Engineering) and B.Tech. (Electronics &
Telecommunication Engineering) Degrees from the J.K. Institute
of Applied Physics & Technology, University of Allahabad,
Allahabad (Uttar Pradesh) India in the year of 1998 and 2000,
respectively. His main research interests are in Low-Power Digital
VLSI Design and its Multimedia Applications, Open Source EDA,
and RTL Design.
R.K. Singh (IAENG, ACEEE, IE, ISTE), Professor in the
Department of Electronics & Communication Engineering, VCT-
Kumaon Engineering College, Dwarahat, Almora (UK) India. He
is being honored with the Ph.D. in Electronics Engineering in the
Year 2003 from the University of Allahabad, Allahabad (Uttar
Pradesh), India. He has received his M.E. (Electronics & Control
Engineering) in 1992 from BITS, Pilani and B.E. (Electronics &
Communication Engineering) in 1990 from Marathawada
University, India. He has authored several text-books in the field of
VLSI Design, Basic Electronics, and Opto-Electronics. He has
worked at various capacities as, the Principle, Kumaon
Engineering College, Dwarahat in the year 2003-04, Director (O),
Directorate of Technical Education, Uttaranchal in the year 2005,
and Joint Director, State Project Facilitation Unit, Dehradun for the
World Bank TEQIP Project. He is also the recipient of couple of
prestigious awards, e.g., Rastriya Samman Puruskar, Jewel of India
Award, Rastriya Ekta Award, Life Time Achievement Award, and
Arch of Excellence Award. His current areas of interest are VLSI
Design, Opto-Electronics and its applications.
Manisha Pattanaik (WSEAS, IE, ISTE) has been honored the
Ph.D. from Indian Institute of Technology (IIT) Kharagpur, (West
Bengal) India in the field of VLSI Design from the Department of
Electronics and Electrical Communication Engineering in the year
2004. Currently she is an Assistant Professor (VLSI Group) at
ABV-India Institute of Information Technology & Management
(ABV-IIITM), Gwalior, (Madhya Pradesh), India. She has been
awarded various scholarships, e.g., National Scholarships, Merit
Scholarships and MHRD Fellowships. She shared the
responsibility in the capacity of referee for IEEE International
Conferences on VLSI Design for two consecutive years, 2003-04.
Her areas of interest are Leakage Power Reduction of Nano-Scale
CMOS Circuits, Characterization of Logic Circuit Techniques for
Low-Power/Low-Voltage and High performance analog & digital
VLSI applications and CAD of VLSI Design.