Shift Registers

Shift Registers
In general, a shift register is characterized by the following control and data signals,
which are fully recognized by XST.

● clock
● serial input
● asynchronous set/reset
● synchronous set/reset
● synchronous/asynchronous parallel load
● clock enable
● serial or parallel output. The shift register output mode may be:
❍ serial: only the contents of the last flip-flop are accessed by the rest of

the circuit
❍ parallel: the contents of one or several flip-flops, other than the last

one, are accessed

● shift modes: left, right, etc.

There are different ways to describe shift registers. For example, in VHDL you can
use:

● concatenation operator
shreg <= shreg (6 downto 0) & SI;
● "for loop" construct
for i in 0 to 6 loop
shreg(i+1) <= shreg(i);
end loop;
shreg(0) <= SI;
● predefined shift operators; for example, SLL or SRL

Consult the VHDL/Verilog language reference manuals for more information.

FPGAs:

Virtex™/-E/-II/-II Pro/-II Pro X/4 and Spartan™-II/-IIE/-3 have specific hardware

resources to implement shift registers: SRL16 for Virtex™ /-E/-II/-II Pro/-II Pro X
and Spartan™-II/-IIE/-3 and SRLC16 for Virtex™-II/-II Pro/-II Pro X/4 and Spartan-
3™. Both are available with or without a clock enable. The following figure shows

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Shift Registers

the pin layout of SRL16E.

The following figure shows the pin layout of SRLC16.

Note: Synchronous and asynchronous control signals are not available in the SLRC16x
primitives.

SRL16 and SRLC16 support only LEFT shift operation for a limited number of IO
signals.

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Shift Registers

● clock
● clock enable
● serial data in
● serial data out

This means that if your shift register does have, for instance, a synchronous
parallel load, no SRL16 is implemented. XST uses specific internal processing
which enables it to produce the best final results.

The XST log file reports recognized shift registers when it can be implemented
using SRL16.

Log File
The XST log file reports the type and size of recognized shift registers during the
Macro Recognition step.

...
Synthesizing Unit <shift>.
Related source file is shift_registers_1.vhd.
Found 8-bit shift register for signal
<tmp<7>>.
Summary:
inferred 1 Shift register(s).
Unit <shift> synthesized.
==============================
HDL Synthesis Report
Macro Statistics
# Shift Registers : 1
8-bit shift register : 1
==============================
...

Related Constraints
A related constraint is SHREG_EXTRACT.

8-bit Shift-Left Register with Positive-Edge Clock, Serial In

and Serial Out
Note: For this example, XST infers an SRL16.

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Shift Registers

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, a serial in and a serial out.

IO
Description
Pins

Positive-Edge
C
Clock

SI Serial In

SO Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
a serial in and a serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end process;
SO <= tmp(7);
end archi;

Verilog Code

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Shift Registers

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, serial in and serial out.

module shift (C, SI, SO);

input C,SI;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp <= tmp << 1;
tmp[0] <= SI;
end
assign SO = tmp[7];
endmodule

8-bit Shift-Left Register with Negative-Edge Clock, Clock

Enable, Serial In and Serial Out
Note: For this example, XST infers an SRL16E_1.

The following table shows pin definitions for an 8-bit shift-left register with a
negative-edge clock, a clock enable, a serial in and a serial out.

IO
Description
Pins

C Negative-Edge Clock

SI Serial In

Clock Enable (active

CE
High)

SO Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a negative-edge
clock, a clock enable, a serial in and a serial out.

library ieee;

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Shift Registers

use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, CE : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='0') then
if (CE='1') then
for i in 0 to 6 loop
tmp(i+1) <= tmp(i);
end loop;
tmp(0) <= SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a negative-edge
clock, a clock enable, a serial in and a serial out.

module shift (C, CE, SI, SO);

input C, SI, CE;
output SO;
reg [7:0] tmp;
always @(negedge C)
begin
if (CE)
begin
tmp <= tmp << 1;
tmp[0] <= SI;
end
end
assign SO = tmp[7];
endmodule

8-bit Shift-Left Register with Positive-Edge Clock,

Asynchronous Clear, Serial In and Serial Out
Note: Because this example includes an asynchronous clear, XST does not infer an

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Shift Registers

SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, an asynchronous clear, a serial in and a serial out.

IO
Description
Pins

C Positive-Edge Clock

SI Serial In

Asynchronous Clear (active

CLR
High)

SO Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
an asynchronous clear, a serial in and a serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, CLR : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= (others => '0');
elsif (C'event and C='1') then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
SO <= tmp(7);
end archi;

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Shift Registers

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, asynchronous clear, serial in and serial out.

module shift (C, CLR, SI, SO);

input C, SI, CLR;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge CLR)
begin
if (CLR)
tmp <= 8'b00000000;
else
begin
tmp <= {tmp[6:0], SI};
end
end
assign SO = tmp[7];
endmodule

8-bit Shift-Left Register with Positive-Edge Clock,

Synchronous Set, Serial In and Serial Out
Note: For this example, XST does not infer an SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, a synchronous set, a serial in and a serial out.

IO
Description
Pins

C Positive-Edge Clock

SI Serial In

Synchronous Set (active

S
High)

SO Serial Output

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Shift Registers

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
a synchronous set, a serial in and a serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, S : in std_logic;
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C, S)
begin
if (C'event and C='1') then
if (S='1') then
tmp <= (others => '1');
else
tmp <= tmp(6 downto 0) & SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, a synchronous set, a serial in and a serial out.

module shift (C, S, SI, SO);

input C, SI, S;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
if (S)
tmp <= 8'b11111111;
else
begin
tmp <= {tmp[6:0], SI};
end
end

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Shift Registers

assign SO = tmp[7];
endmodule

8-bit Shift-Left Register with Positive-Edge Clock, Serial In

and Parallel Out
Note: For this example, XST does not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, a serial in and a parallel out.

IO
Description
Pins

Positive-Edge
C
Clock

SI Serial In

PO[7:0] Parallel Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
a serial in and a parallel out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;

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Shift Registers

PO <= tmp;
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, a serial in and a parallel out.

module shift (C, SI, PO);

input C, SI;
output [7:0] PO;
reg [7:0] tmp;
always @(posedge C)
begin
tmp <= {tmp[6:0], SI};
end
assign PO = tmp;
endmodule

8-bit Shift-Left Register with Positive-Edge Clock,

Asynchronous Parallel Load, Serial In and Serial Out
Note: For this example, XST does not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, an asynchronous parallel load, a serial in and a serial out.

IO
Description
Pins

C Positive-Edge Clock

SI Serial In

Asynchronous Parallel Load (active

ALOAD
High)

D[7:0] Data Input

SO Serial Output

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Shift Registers

VHDL Code

Following is VHDL code for an 8-bit shift-left register with a positive-edge clock, an
asynchronous parallel load, a serial in and a serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, ALOAD : in std_logic;
D : in std_logic_vector(7 downto 0);
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp : std_logic_vector(7 downto 0);
begin
process (C, ALOAD, D)
begin
if (ALOAD='1') then
tmp <= D;
elsif (C'event and C='1') then
tmp <= tmp(6 downto 0) & SI;
end if;
end process;
SO <= tmp(7);
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, an asynchronous parallel load, a serial in and a serial out.

module shift (C, ALOAD, SI, D, SO);

input C, SI, ALOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C or posedge ALOAD)
begin
if (ALOAD)
tmp <= D;
else
tmp <= {tmp[6:0], SI};
end
assign SO = tmp[7];
endmodule

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Shift Registers

8-bit Shift-Left Register with Positive-Edge Clock,

Synchronous Parallel Load, Serial In and Serial Out
Note: For this example, XST does not infer SRL16.

The following table shows pin definitions for an 8-bit shift-left register with a positive-
edge clock, a synchronous parallel load, a serial in and a serial out.

IO
Description
Pins

C Positive-Edge Clock

SI Serial In

Synchronous Parallel Load (active

SLOAD
High)

D[7:0] Data Input

SO Serial Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left register with a positive-edge clock,
synchronous parallel load, serial in and serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, SLOAD : in std_logic;
D : in std_logic_vector(7 downto 0);
SO : out std_logic);
end shift;
architecture archi of shift is
signal tmp: std_logic_vector(7 downto 0);
begin
process (C)
begin

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Shift Registers

if (C'event and C='1') then

if (SLOAD='1') then
tmp <= D;
else
tmp <= tmp(6 downto 0) & SI;
end if;
end if;
end process;
SO <= tmp(7);
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left register with a positive-edge
clock, a synchronous parallel load, a serial in and a serial out.

module shift (C, SLOAD, SI, D, SO);

input C, SI, SLOAD;
input [7:0] D;
output SO;
reg [7:0] tmp;
always @(posedge C)
begin
if (SLOAD)
tmp <= D;
else
tmp <= {tmp[6:0], SI};
end
assign SO = tmp[7];
endmodule

8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock,

Serial In and Parallel Out
Note: For this example, XST does not infer an SRL16.

The following table shows pin definitions for an 8-bit shift-left/shift-right register with
a positive-edge clock, a serial in and a serial out.

IO Pins Description

C Positive-Edge Clock

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Shift Registers

SI Serial In

Left/right shift mode

LEFT_RIGHT
selector

PO[7:0] Parallel Output

VHDL Code

Following is the VHDL code for an 8-bit shift-left/shift-right register with a positive-
edge clock, a serial in and a serial out.

library ieee;
use ieee.std_logic_1164.all;
entity shift is
port(
C, SI, LEFT_RIGHT : in std_logic;
PO : out std_logic_vector(7 downto 0));
end shift;
architecture archi of shift is
signal tmp : std_logic_vector(7 downto 0);
begin
process (C)
begin
if (C'event and C='1') then
if (LEFT_RIGHT='0') then
tmp <= tmp(6 downto 0) & SI;
else
tmp <= SI & tmp(7 downto 1);
end if;
end if;
end process;
PO <= tmp;
end archi;

Verilog Code

Following is the Verilog code for an 8-bit shift-left/shift-right register with a positive-
edge clock, a serial in and a serial out.

module shift (C, SI, LEFT_RIGHT, PO);

input C, SI, LEFT_RIGHT;
output PO;

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Shift Registers

reg [7:0] tmp;

always @(posedge C)
begin
if (LEFT_RIGHT == 1'b0)
tmp <= {tmp[6:0], SI};
else
tmp <= {SI, tmp[7:1]};
end
assign PO = tmp;
endmodule

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Best matches for 8 bit serial in serial out shift register

verilog code

Following is the Verilog code for an 8-bit shift-left register

with a... Jump to text »

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