CMOS Design Rules

S. Tewksbury

1. Design Rules: Introductory Comments

These notes provide some background on the topic of design rules, namely minimum widths and
separations related to structures drawn in a layout. The design rules originate from the need to use
multiple layers of patterns, each layer defined by a mask and applied to the evolving CMOS fabrication
in sequence. The pattern on the mask is projected onto the surface of the silicon wafer where it exposes
a photosensitive material. This projection step impresses the mask pattern on the photoresist layer.
Upon development of this photoresist film on the silicon wafer, the pattern on the mask appears as
regions of the photoresist film where the photoresist has been removed, exposing the underlying surface
of the silicon wafer passing through the fabrication steps. These steps are reviewed in the course
textbook, CMOS Circuit Design, Layout and Simulation by Baker, Li, and Boyce.

2. Representative Effects Requiring Rules on Widths and Spacings

Three general effects lead to these design rules, illustrated by the examples below.
(b)
(a)
Drain-Substrate
Via
Substrate
Interconnect
Silicon
Drain
Metal
As-drawn
Alignment
mask (layout)
error
Short
leading
due
Diffusion
Dioxide
to to
mask
shifted
Metalvia
Overlap

Figure 1
a. Deviations in alignment of a given mask exposure with previously defined patterns. Such
“misalignments” place patterns at positions displaced from the expected positions. Figure 1
illustrates the case of a mask pattern defining the metal interconnection and the mask pattern
defining the via cut allowing the metal interconnection to contact the source and drain regions.
 Figure 1a shows the expected structure if no alignment errors occur whereas Figure 1b shows an
example of an alignment error. By imposing requirements on minimum widths (for
interconnection mask) and minimum spacing (edge of via to edge of interconnection mask), the
fault illustrated can be avoided and correct operation achieved despite alignment errors
representative of the fabrication process.
b. Variations in shape of pattern. An example is seen in metal interconnections. If a metal
interconnection line is to narrow, the etching process that defines the line may “over-etch” in
some locations, leading to gaps in the interconnection line. If two metal interconnection lines
are too close together, the etching process may fail to remove some of the metal between the
two lines, leading to a short between the lines. These two effects are illustrated in Figure 2,
where Figure 2a illustrates the “drawn” pattern on the masks and Figure 2b illustrates the effects
of etching variations. Increasing line width removes the open. Increasing line spacing removes
the short.
Interconnect Open
Short
mask

(a) As-drawn (layout mask) (b) Over-etching leading to

open in line and under-etching
leading to short between lines.
Figure 2
c. Deviations in the final shape of a patterned structure relative to the shape of the mask pattern.
An example is seen in the diffusions used to create the source-drain regions. The “diffusion”
mask creates the cut in the silicon dioxide defining the region in which the transistor is placed.
After defining the gate region, dopants (e.g., N-type for NMOS transistors) are implanted in the
substrate (P-type substrate for NMOS transistors). However, these dopant atoms must be
“driven” into the substrate using a high temperature diffusion step. During this step, dopant
atoms diffuse deeper into the substrate (the desired effect) but also diffuse laterally under the
silicon dioxide layer adjacent to the diffusion layer cut in the oxide. The result is that the width
of the diffusion layer exceeds the width of the diffusion layer pattern in the mask.
If two diffusion layers are placed too close to one another, then the dopants from these two
layers may diffuse under the oxide and connect the two regions, even though the original masks
indicate that there is a gap between the two diffused regions. Figure 3 illustrates the effect.
Figure 3a shows a single diffusion layer, having expanded under the oxide during the “drive-in”
annealing step. Figure 3b shows the effect of spacing the diffusion layers too closely - leading
to a shorting of the presumed separate diffusion layers.
 (b)
(a)
Diffusion
Substrate
Drain
Oxide
Single
Shorting
Shorteddiffusion
diffusion
of adjacent
layer
layers
diffusion layers due
with
to
Diffusion
lateral
Mask
lateral
diffusion
diffusion.
of dopants.

Figure 3

3. Design Rules as “Lambda Rules”

For any specific fabrication process (e.g., a Motorola 0.25 micron process), it would be possible to
specify the minimum pattern widths and separations using specific distances in microns. However, this
would lead to difficulties later if the same circuit is to be fabricated in a new fabrication process (e.g.,
0.17 micron process). Such a change in the fabrication process from current size features/devices to a
smaller size features/devices would require that new masks be designed. Given the complexity of VLSI
mask designs, it would be far more convenient to retain the current mask design and simply generate
new physical masks with a smaller size. It is for this purpose that the design rules are specified as a
multiple of some baseline number, represented by “lambda.” I won’t use the greek letter for lambda
here since some computers do not recognize my symbol fonts. For this reason, I’ll use L to indicate the
greek letter lambda. By using this base size L and representing all design requirements as n*L where
“n” is typically an integer, the design can be “scaled” to the “shrunk” fabrication process. If the
dimensions of structures in the shrunk technology are reduced by a factor of two, then the value of
lambda used is simply reduced by a factor of two.
Appendix A of the course textbook, CMOS Circuit Design, Layout and Simulation by Baker, Li,
and Boyce, presents the design rules for the Orbit 2 micron process. In this case, the design rules are
given directly in microns (not in lambda). For example, Figure A.8 of Appendix 8 gives the minimum
width of the N-well as 3 microns and the minimum separation between N-wells as 9 microns. Figure
A.10 of that appendix gives the minimum width and spacing of poly lines (forming the gate) as 2
microns (the reasons why the technology is called a 2 micron technology).
 Appendix B of the course textbook, CMOS Circuit Design, Layout and Simulation by Baker, Li,
and Boyce, presents the design rules for the MOSIS fabrication technology in terms of lambda. Figure
B.4 of Appendix B gives the minimum width and spacing of the poly lines (forming the gate) as 2*L,
with lambda therefore being 1/2 the poly line width and spacing. If the MOSIS fabrication technology
being used were a 2 micron technology (named according to the width of the poly line), then L = 1
micron. You will be using the MOSIS technology in your designs so you should follow the design rules
given in Appendix B. This will all be rather confusing at first but once you have designed a basic logic
cell (e.g., an AND gate) and applied the design rules, it will become clearer.
To maximize the number of transistors on an IC, it would be appropriate to design all transistors
and interconnections at the smallest design rule (unless some other requirement such as current drive
capability for drivers requires a larger sized transistor - for example a wider than minimum gate region).
The LASI design tools provide a grid that can be used during layout to “see” the sizes of the patterns
being made. The grid spacing is 1 lambda. If having problems during the design rule check, you can
use larger widths and spacings to avoid errors. However, even if taking this safe approach you will still
need to run the design rule checker to ensure that no design rule errors appear in your design. Note:
when completing the tutorial, you should check my notes related to that tutorial since there is a step
given that will lead to unavoidable design errors being tagged by the design rule checker no matter what
you do.
When applying the design rules, you will quickly see that devices and interconnects require
significantly more area than the polysilicon gate width. This is natural. While going through the design
rules for the MOSIS scalable design rules, you will encounter mask layers that may not be needed in
your simple designs. Follow the tutorial and worry only about those mask layers used in the tutorial.
One approach that you may find helpful is to design a generic NMOS transistor and a generic
PMOS transistor, satisfying the design rules for each. Given these designs, they can be used to build up
the digital circuits without having to worry about the details within each transistor (i.e., you will only
need to worry about their arrangements and connections).

4. Why Do They Use Multiple Vias (2 x 2 lambda in size)

As you go through the various circuit designs, you may begin to wonder why the designs use many
small (actually minimum size) vias rather than a single large via. This relates to current flow from the
metal layer on top of the oxide to the silicon or polysilicon. Figure 4 shows the reason for this style.
Figure 4a shows a single wide via. In this case current flows from the metal layer on top of the oxide to
the metal layer covering the diffusion area only through the thin layers of metal along the oxide walls.
Figure 4b shows the case of an array of minimum size and spacing vias. In this case, metal fills the vias
and (i) the resistance of the via is reduced and, more importantly, (ii) the current density is reduced. If
the current density becomes too large, electromigration can lead to early failure of the connection. Still
further increases in the current density can lead to the via connection burning out.
 (b)
(a)Single
Via
Substrate
Drain
Oxide
Array
Masklarge
of minimum
via opening.
size via openings.
Diffusion

Figure 4