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Advanced Mixed Signal Design using CMOS Current Mode Logic
Gates
1
Lokesh.B , P. Jayakrishnan, and S. Chatterjee
School of Electrical Sciences, VIT University, 632014, TN, India
1
lokeshb@vit.ac.in
1. Introduction
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the effective value of RL, which is usually a PMOS
transistor. The voltage swing is in the range of a few
hundred mV and is a crucial leverage factor in high-speed
MCML gate design. Every MCML gate has two bias
voltages, RFP and RFN. The value of RFP is set to achieve
the desired load resistance. The value of the load resistance
can also be controlled by the dimensions of the PMOS
transistor. RFN biases the current source transistor and
helps in fixing the desired current. The width of the current
source transistor is usually large to make the transistor
robust, to decrease the mismatch effects, and to enable a
future reduction in VDD [16].
The equations for the total propagation delay, power
dissipation, and the power delay product of a CCML logic
circuit and its CMOS counter part are shown in Table 1.
Power (b)
Dissipated PDMCML=VDD ISC PDCMOS=N CL Fig 2: Basic logic gates: (a) Conventional NOR (b) CCML
VDD2 f AND/NAND/OR/NOR logic gate
3. CCML CIRCUITS
The operation of CCML logic circuits is based on the
steering of constant current similar to the “differential pair”
used in the analog circuit’s fig: 2 show the structure of
conventional NOR and a CCML AND/NAND/OR/NOR
gate. Device scaling is typically selected as small as possible
with the constraint that sufficient swing noise and noise
margins are produced by the circuit.
Fig. 3: CCML Inverter
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4. SIMULATION AND RESULTS frequency detector. Since D-input is logically connected
high, it was possible to remove the input and incorporate the
The design is based on TSMC 0.18 and 0.25µm CMOS logic into the circuit. The resulting flip-flop, initially
technology node using cadence Virtuoso spectre because suggested by Razavi [17], is comprised of a series of
CADENCE tool has been widely used and good cross -coupled OR gates.
experimental correlation for gate delays have been achieved
the confidence level in the simulation is high. The
propagation delay can be improved using the proposed
CCML design with both 0.18 and 0.25 µm technology
4
propagation delay compared to that of CCML the
conventional logic doesn’t have the dynamic symmetry in
AND gate because of one connection is dynamically faster
than the other connection due to the asymmetric circuit
configuration shown in Fig. 2(a). As shown in Table 3, the
resolution widths of the conventional logic phase detector in
the situation when Fr e f is ahead or behind of Fv c o are
Unbalanced. On the other hand, the CCML phase detector has
the dynamic symmetry because of the balanced architecture of
the basic NOR /NAND/AND/OR cell as shown in Fig. 2(b).
V. References
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