Structural Modeling Component Declaration

• What is the purpose of structural modeling? • The component that we want to use for
• Structural VHDL is simply the interconnection of the bigger design must to available.
number of components constraint with structural • For
F structurall modeling
d li off Half
H lf adder,
dd theh
modeling is that block diagram for the complete model for XOR and basic AND gate must
system must be known. be available to you.
• The following steps are involved for structural • While writing structural program for Half
modeling
modeling. adder,
dd the h components must be b declared
d l d
1. Component declaration between architecture and begin
2. Component specification
3. Interconnection between components

Architecture t1 of halfadder is • It’s to be noted that port name can be same in

component xor1 different components. In the above example we can
Port (a, b: in std_logic; have the same name for ports x, y, z as used below.
c: out std_logic); Architecture t1 of halfadder is
end component; component xor1
component and1 Port (a, b: in std_logic;
Port (x, y: in std_logic; c: out std_logic);
z: out std_logic); end component;
end component; component and1
b
begin Port (a,
( b:b in std_logic;
d l
c: out std_logic);
end component;
begin
It’s to be noted that the order of the signal in the port
command must be same as that in the entity declaration Component Specification
otherwise it will give syntax error.
• If XOR1 entity declaration is like as given below and its
t be
to b • If the VHDL simulator is to find the declared
used for half adder as shown above then the component component, the component must be
declared below will give syntax error. specified.
Entity xor1 This is done with the use of the following
Port (a, b: in std_logic; command.
c: out std_logic); Syntax:
end xor1;
and during component declaration its written as
for: <component_name>use entity library.
component xor1 <entity name> (architecture name)
Port ( b,
b a : in std_logic;
std logic; For u1: xor1 use entity work.xor1 (t1);
c: out std_logic);
end component;
‐‐ error as in the entity a is declared before b.
Interconnection between components Half Adder Designing using XOR and basic AND gate
• Before doing interconnection between different
• After component declaration, the main job is to
components and the original design, first find which signal
interconnect the different component to get the from the outside world is to be connected with which port
complete system. of
• This
Thi is
i known
k as componentt instantiation
i t ti ti and d the component used.
different component are “linked” to other • In the above example its clear that a, b and c ports of
components using port map command. XOR
• The port map command does the job of gate is to be connected with X,Y and S ,respectively, of the
main block.
connection.
ti Th format
The f t for
f the
th same is
i being
b i
• This connection between the main block and the ports
shown below. of
Label: entity name Port map (port association list) the component used is known as association list as
• Label is indicating only the component label. indicated on the port map format.
Entity half is Important tips about port map:
Port (X, Y: in std_logic;
S, C: out std_logic);
1. Unconnected inputs:
End half; • Some times it may happen that some input
A hit t
Architecture t1 off half
h lf is
i ports of the component used may not utilized
component xor1 by the main block during interconnection. Then
Port (a, b: in std_logic; how to handle it?
c: out std_logic); • As no silicon supplier will accept an input to a
end component; hierarchical block which is “floating”
floating or
component and1
Port (a, b: in std_logic;
unconnected.
c: out std_logic); • If an input on a component is not in use, the
end component; signal should be connected to Vcc or Gnd such
begin that overall functionality should not change.
change
U1: xor1 port map (X, Y, S);
U2: and1 port map (X, Y, C);
End t1;
Port Association:
U1: xor1 port map (a=>X, b=> Y, c=> S); Unconnected outputs:
• Suppose we have taken three input AND gate as a • Some time it may happen that some output
component and only two of its inputs are required for   ports of the component declared may not be
some application utilized by the main block during interconnection.
Component and1 d Then how to handle it?
Port (a, b, c: in std_logic; ‐‐ 3 input AND gate. • This can be done by using the VHDL
F : out std_logic); command “open”.
End component;
u1: Ha port map (A, B, F, open);
Signal high : std logic ; ‐‐
Signal high : std_logic ; this is representing logic high
this is representing logic high
If the last port declared in the component is to be
Begin
High<= ‘1’; kept open, then we need not to write open since
U1: and1 port map ( x ,y ,high ,z ); by default it will be connected to open.
 Generic command • Similarly we can introduce generic delay
• Generic can be used to introduce information into a information in any vhdl model. Let’s see the
model. program given below.
• This information can be timing information, vector length • Example: entity generic2 is
p yg
etc. the generic must be declared in the entity before the Generic (delay: time: =3 ns);
port declaration command. Port (a, b: in std_logic;
• A generic can have any data type i.e. it can have data
type like time, real, integer.
C: out std_logic);
• The following example illustrate the used of generic End generic2;
g ;
command. Architecture t1 of generic2 is
Example: entity generic1 is Begin
Generic ( N : integer:=3); C<= a and b after delay;
Port (a : in std_logic_vector(0 to N); End t1;;
C: out std_logic_vector (0 to N));
End generic1;
Entity or1 is
Generic (n: integer: =5);
Generic Map Port ( a : in std_logic_vector( 0 to N);
f
f : out std_logic);
t td l i )
• If generic component have been specified end or1;
architecture t1 of or1 is
in the component to be instanced, there begin
generic parameter can be changed during process (a)
variable temp : std logic;
variable temp : std_logic;
instantiation using generic map. begin
• Let’s write generic program for N input OR temp:= ‘0’;
for i in 0 to N loop
gate. if (a (i)=’1’) then
temp:= ‘1’;
end if;
end loop;
f<= temp;
end process;
end t1;
• We want to use the above component in other Generate command
design using structural modeling.
component or1
Sometimes, during structural modeling, it may
Generic (n: integer: =5); happen that the same component is to be used
P t ( i td l i
Port ( a : in std_logic_vector( 0 to N);
t ( 0 t N) more then once.once
f : out std_logic); • Simple method is to use port map command for
end component ; each component. But if the number of components
begin is very large then this method will be very lengthy.
u1: or1 generic map (n=>1) • If the same component has to be instanced
port map( a(0)=> X1, a(1)=>X2, f=>f1);
u2: or1 generic map (n=>2)
several times in the architecture, it may be
port map( a(0)=> X3, a(1)=>X4, a(2)=> X5, f=>f1); effective to include port map command in a loop.
end t1; This can be done by using generate command. The
format for using the same is being given
below.
Label: for < loop index> range generate Entity t1 is
Label: entity name port map (port association  Port ( x: in bit_vector (9 downto 0 );
list); q: out bit vector( 9 downto 0));
q: out bit_vector( 9 downto
End generate <label>; end t1;
Suppose we want to instanced a component, architecture behave of t1 is
Entity test is component test
Port (a: in bit;
( ;
Port (a: in bit;
Port (a: in bit;
f : out bit);
f : out bit);
end test;
10 times in other entity whose entity is as shown  end component ;
below begin
Entity t1 is l1: for i in 0 to 9 generate
l1: for i in 0 to 9 generate
Port ( x: in bit_vector (9 downto 0 ); u1: test port map( x (i) , q (i));
q: out bit_vector( 9 downto 0)); end generate l1;
end t1; end behave;
 Example Schematic Example Structural VHDL Interface
A
A1 Z -- Define the Interface
B INT1

A_IN entity
tit MAJORITY is i
A port
A INT2
B_IN A2 Z B O1 Z Z_OUT (A_IN, B_IN, C_IN: in BIT;
B C Z_OUT : out BIT);
C IN
C_IN end MAJORITY;;

A A3 Z
INT3
B

Example VHDL Body Example VHDL Statement Part

begin
architecture STRUCTURE of MAJORITY is
-- Define the component connections
-- Declaration of components and local signals
A1: AND2_OP port map (A_IN, B_IN, INT1);
component AND2_OP A2: AND2_OP port map (A_IN, C_IN, INT2);
port ((A, B : in BIT; Z : out BIT);
p ) A3: AND2
AND2_OP
OP port map (B_IN,
(B IN CC_IN,
IN INT3);
end component; O1: OR3_OP port map (INT1, INT2, INT3,
component OR3_OP Z_OUT);
port (A, B, C : in BIT; Z : out BIT);
end component; end STRUCTURE;

signal INT1, INT2, INT3 : BIT;