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5 4 3 2 1

YONAH-CALISTOGA Fab 5
Capell
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CUSTOMER REFERENCE REV 1.502
Valley
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BOARD IPN: C75289-501

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D D
Calistoga

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Fan Clocking VCCP VR
Header IMVP-6 VR
Yonah 478 PG 30,31

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PG 5 PG 51, 52 PG 48
uFCPGA
XDP

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CPU
LVDS/ALS/BLI CRT PG 3,4
Thermal PG 37 DDR VR
(DVI-I)
PG 19 Sensor

SODIMM0
PG 18 PG 5 PG 46
FSB Dual Channel

SODIMM1
DDR2
VGA

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TVOUT
Calistoga PG SYSTEM VR
PG 20 LVDS
21,22,23
1466 PG 49
FCBGA

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PEG/ SDVO PG
C SLEEP CONTROL C
SDVO 6,7,8,9,10,11,12 PG 25

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PG 13 PCI SLOT3 PG 55

PG 25

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PCI SLOT4 BATTERY CHARGER VR
X4 DMI 33 Mhz PCI

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PG 26 PG 50
interface PCI
SATA EDGE-CONN

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CC SATA PORT 0
PG 43 PG 28
ICH7M PCIEx1 PG 28 MOBILE POWER
SATA PCIe SLOT0 PCIe SLOT2 ON SEQUENCE
SATA PORT 2
DC 652 PCIEx1 PG 28

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PG 44 BGA PCIe SLOT1
PATA PCIEx1

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PG
B PG 39 B

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14-17 PCIEx1
BACK PANEL FPIO/DB BACK PANEL FPIO/DB
USB 2.0 PCIEx1
2.0 2.0 2.0 2.0
PCIE

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PCIEx1
8 USB ports total
USB6

USB5
USB7

USB4

SPI DOCKING

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HD AUDIO/ AC97
DOCKING BACK PANEL FPIO/DB BACK PANEL LPC, 33MHz

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RJ45
2.0 2.0 2.0 2.0 Tekoa/EkronR LAN
HD AUDIO / PORT PG 33, 34
USB0

USB1

USB2

TPM SIO
USB3

MDC 1.5 80-83

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HEADER PG 41 PG 35 PG 42
SPI
PG 27 IR/ SERIAL Flash
BACK PANEL USB FPIO/DB USB
PG 45 PG 33
PG 40 PG 29

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A LPC A
SMC/KSC SLOT LPC Capell Valley Intel Confidential

FWH PG 35 DOCK Title

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8 Mbit PG 32 PG 57 TITLE PAGE
PG 24
Size Document Number Rev
A D15378
EMA 1.501
SCN KB/ PS2
PG 36 PG 38 Date: Wednesday, July 20, 2005 Sheet 1 of 60
5 4 3 2 1
5 4 3 2 1

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CALISTOGA CUSTOMER REFERENCE
PLATFORM

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SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

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D D

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Default Jumper Settings For Stuffed Jumpers
2
I C / SMB Addresses Jumper Default Description Page

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J3B1 1-2 H_THERMDA 5
Voltage Rails Device Address Hex Bus J3B1 3-4 H_THERMDC 5
Clock Generator 1101 001x D2/D3* SMB_ICH_S3 J6H1 1-X CMOS CLEAR 14
POWER PLANE VOLTAGE S3COLD ACTIVE DESCRIPTION Spread Spectrum Clock 1101 010x D4/D5* SMB_ICH_S3 J8H1 1-X BIOS RECOVERY 16
+VBATA 9V-12.5V S0, S3, S4, S5 Battery Rail in Mobile Power Mode PCI Express Clock 1101 110x DC/DD* SMB_ICH_S3 J2J10 2-3 CRB/SV DETECT 16

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+VBAT 9V-12.5V S0, S3, S4, S5 Battery Rail in Mobile Power Mode SO-DIMM0 1010 010x A4 SMB_ICH_S2 J9J8 MFG/TEST 16
SO-DIMM1 1010 000x A0 SMB_ICH_S2 J1F4 1-2 BSEL2 30
+VBATS 9V-12.5V S0 Battery Rail in Mobile Power Mode DDR Thermal Sensor 0100 1100 4C SMB_ICH_S2 J1G1 1-2 BSEL1 30
+V12S 12V S0 Only on in DT Power Mode IC2 Buss Expander 0011 xxxx 3x J1G2 1-2 BSEL0 30
-V12A -12V S0, S3,S4,S5 Only on in DT Power Mode Ambient Light Sensor 0111 0010 72 AON_ALS J9J2 1-2 MDO 32
-V12S -12V S0 Only on in DT Power Mode Always ON Display 011 110x 3C SMB_ICH J9J6 1-2 MD1 32
+V5A 5V S0, S3,S4,S5 Thermal Diode 1001 100B 4C SMB_THRM J9J4 1-X MD2 32
Battery A 0001 0110 16 SMB_BS J9J1 1-X KSC DISABLE 32
+V5 5V S0, S3 Battery B 11110 1E SMB_BS J9J7 1-X VB JMPR 32
+V5S 5V S0 LAN 1100 1000 1E SMB_BS J9J5 1-X LID JMPR 32

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+V3.3A 3.3V S0, S3,S4,S5 PCI Express Docking TBD TBD SMB_ICH_A1 J8G1 1-2 SMC RST# 32
+V3.3 3.3V S0, S3 Trusted Platform Module TBD TBD J8A1 1-X LAN PROTECT 33
+V3.3S 3.3V S0 J9G3 1-2 BOOT BLOCK PROG 38
+V1.5S 1.5V S0 J9H1 1-X NMI JMPR 38
1.8V
J7J3 1-2 PATA HotSwap 39
+V1.8 S0, S3 DDR core J7E1 1-X PORT80 SEL 41
+V0.9 0.9V S0, S3 DDR command & control pull up. * First address is for a write command and second is for a read command. J7E3 1-2 SIO RST# 42

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+V2.5S 2.5V S0 J9J3 1-2 SATA DET 44
+V2.5_LAN 2.5V S0, S3 LAN Rail Buses labeled SMB_ICH_xx come out of ICH, via an I2C expander. The J5H2 1-2 SATA HotSwap 44
+V1.2 1.2V S0, S3 LAN Rail rest come out of EC.
J7A3 1-2 H8 PROG# 45
+1.05S 1.05V S0 GMCH, ICH core, and FSB rail
J7A4 1-2 H8 PROG# 45
C J3H1 1-X SHUTDOWN 54 C
+VCC_CORE 0.700V-1.77V S0 CPU core rail

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LEDs and Switches

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LED Page Reference
ATA Activity LED 14 CR7J1
SMC/KBC Num Lock 32 CR9G1
SMC/KBC Scroll Lock 32 CR9G2

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SMC/KBC Caps Lock 32 CR9G3
VID0 45 CR1B1
VID1 45 CR1B2
VID2 45 CR1B3
VID3 45 CR1B4

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VID4 45 CR1B5
VID5 45 CR1B5
VID6 45 CR1C1

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S0 State 55 CR3G1
S3 State 55 CR3G2
S4 State 55 CR3G3
S5 State 55 CR2G1

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Switch Page Reference
Power On/Off 54 SW1C1
Reset 54 SW1C2
LID 32 SW9J2
Virtual battery 32 SW9J1

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PCI Devices
B B

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Device IDSEL # REQ/GNT # Interrupts
Slot 3 AD18 2 2 C, D, B, A
Slot 4 AD19 3 3 D, C, F, G
Wake Events

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LAN (AD24 internal)

Wake Events State Supported


RI# from serial port S3
PME# from PCI, mini PCI slot/device, LPC S3
Net Naming Conventions PCB Footprints

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slot/device S3
PCI Express, mini PCI Express, Newcard wake event S3
Suffix Wake on LAN S3
# = Active Low Signal SOT-23 SOT23-5 LID switch attached to SMC S3

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1 1 5 USB S3
Prefix
AC97/Azalia wake on ring S3
H = Host
3 As seen from top 2 SmLink for AOLII S3
M = DDR Memory
TP = Test Point (does not connect anywhere else) Hot Key from Scan matrix keyboard S3
PS/2 Keyboard/mouse S3
2 3 4 PWRBTN# S3, S4, S5

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Power States

SIGNAL SLP SLP +V*A +V* +V*S Clocks

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S4# S5#
STATE
A A
HIGH HIGH ON ON ON ON Capell Valley Intel Confidential
Full ON
Title

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HIGH HIGH ON ON OFF OFF
S3 (Suspend to RAM) NOTES
LOW HIGH ON OFF OFF OFF
S4 (Suspend To Disk)
Size Document Number Rev
S5 / Soft OFF
LOW LOW ON OFF OFF OFF A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 2 of 60
5 4 3 2 1
5 4 3 2 1

4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S

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6 H_A#[31:3]
U2E1A

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H_A#3 J4 H1 R3T5
A[3]# ADS# H_ADS# 6 56
H_A#4 L4 E2
A[4]# BNR# H_BNR# 6
H_A#5 M3 G5
A[5]# BPRI# H_BPRI# 6
H_A#6 K5 A[6]#

ADDR GROUP 0
H_A#7 M1 H5

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A[7]# DEFER# H_DEFER# 6
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# 6
D H_A#9 J1 A[9]# DBSY# E1 H_DBSY# 6 Place testpoint on D

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H_A#10 N3
H_A#11 P5
A[10]#
F1
H_IERR# with a GND
A[11]# BR0# H_BREQ#0 6
H_A#12 P2 A[12]#
0.1" away

CONTROL
H_A#13 L1 D20 H_IERR#
H_A#14 A[13]# IERR#
P4 INIT# B3 H_INIT# 14

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H_A#15 A[14]#
P1 A[15]#
H_A#16 R1 H4
A[16]# LOCK# H_LOCK# 6
6 H_ADSTB#0 L2 ADSTB[0]# H_CPURST# 6,37
6 H_REQ#[4:0] RESET# B1 H_RS#[2:0] 6
H_REQ#0 K3 F3 H_RS#0

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H_REQ#1 REQ[0]# RS[0]# H_RS#1
H2 REQ[1]# RS[1]# F4
H_REQ#2 K2 G3 H_RS#2
H_REQ#3 REQ[2]# RS[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 6
H_REQ#4 L5 REQ[4]#
6 H_A#[31:3] HIT# G6 H_HIT# 6
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 6
H_A#18 U5
H_A#19 A[18]#
R3 A[19]# BPM[0]# AD4 XDP_BPM#0 37

ADDR GROUP 1
H_A#20 W6 AD3
A[20]# BPM[1]# XDP_BPM#1 30
H_A#21

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U4 A[21]# BPM[2]# AD1 XDP_BPM#2 30

XDP/ITP SIGNALS
H_A#22 Y5 AC4
A[22]# BPM[3]# XDP_BPM#3 30,58
H_A#23 U2 AC2
A[23]# PRDY# XDP_BPM#4 37
H_A#24 R4 AC1 +V1.05S 4,6,9,10,14,17,30,37,45,48,53,56,58
A[24]# PREQ# XDP_BPM#5 37
H_A#25 T5 AC5
A[25]# TCK XDP_TCK 37
H_A#26 T3 AA6
A[26]# TDI XDP_TDI 37
H_A#27 W3 AB3
A[27]# TDO XDP_TDO 37 6 H_D#[63:0] H_D#[63:0] 6
H_A#28 W5 AB5 R3R1 U2E1B
A[28]# TMS XDP_TMS 37

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H_A#29 Y4 AB6 75 H_D#0 E22 AA23 H_D#32
A[29]# TRST# XDP_TRST# 37 D[0]# D[32]#
Layout note: no stub H_A#30 W2 C20 H_D#1 F24 AB24 H_D#33
A[30]# DBR# XDP_DBRESET# 37,54,58 D[1]# D[33]#
H_A#31 Y1 H_D#2 E26 V24 H_D#34
on H_STPCLK TP A[31]# H_D#3 D[2]# D[34]# H_D#35
6 H_ADSTB#1 V4 D21 H_PROCHOT# 51 H22 V26
THERM

ADSTB[1]# PROCHOT# D[3]# D[35]#


C THERMDA A24 H_THERMDA 5
H_D#4 F23 D[4]# D[36]# W25 H_D#36 C

DATA GRP 0

DATA GRP 2
H_D#5 H_D#37

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H_STPCLK#_R 14 H_A20M# A6 A20M# THERMDC A25 H_THERMDC 5 G25 D[5]# D[37]# U23
A5 PM_THRMTRIP# should connect H_D#6 E25 U25 H_D#38
14 H_FERR# FERR# PM_THRMTRIP# 7,14 D[6]# D[38]#
NO_STUFF C4 C7 H_D#7 E23 U22 H_D#39
TP2F1
14 H_IGNNE# IGNNE# THERMTRIP# to ICH7 and GMCH without H_D#8 D[7]# D[39]# H_D#40
PM_THRMTRIP# 7,14 K24 D[8]# D[40]# AB25
R2F2 D5 T-ing (No stub) H_D#9 G24 W22 H_D#41
14 H_STPCLK# STPCLK# D[9]# D[41]#
0 C6 H_D#10 J24 Y23 H_D#42
H CLK

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14 H_INTR LINT0 D[10]# D[42]#
B4 A22 H_D#11 J23 AA26 H_D#43
14,35 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 30 D[11]# D[43]#
A3 A21 H_D#12 H26 Y26 H_D#44
14,35,58 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 30 D[12]# D[44]#
H_D#13 F26 Y22 H_D#45
TP_A32# H_D#14 D[13]# D[45]# H_D#46
AA1 RSVD[01] K22 D[14]# D[46]# AC26

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TP_A33# AA4 T22 TP_EXTBREF H_D#15 H25 AA24 H_D#47
TP_A34# RSVD[02] RSVD[12] D[15]# D[47]#
AB2 RSVD[03] 6 H_DSTBN#0 H23 DSTBN[0]# DSTBN[2]# W24 H_DSTBN#2 6
A#[32-39], APM#[0-1]: TP_A35# AA3 G22 Y25
RSVD[04] 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
TP_A36# M4 D2 TP_SPARE0 J26 V23
RESERVED

Leave escape routing on TP_A37# RSVD[05] RSVD[13] TP_SPARE1


6 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 6
N5 RSVD[06] RSVD[14] F6 6 H_D#[63:0] H_D#[63:0] 6

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for future functionality TP_A38# T2 D3 TP_SPARE2
TP_A39# RSVD[07] RSVD[15] TP_SPARE3 H_D#16 H_D#48
V3 RSVD[08] RSVD[16] C1 N22 D[16]# D[48]# AC22
TP_APM0# B2 AF1 TP_SPARE4 H_D#17 K25 AC23 H_D#49
TP_APM1# RSVD[09] RSVD[17] TP_SPARE5 H_D#18 D[17]# D[49]# H_D#50
C3 RSVD[10] RSVD[18] D22 P26 D[18]# D[50]# AB22
C23 TP_SPARE6 H_D#19 R23 AA21 H_D#51
TP_HFPLL RSVD[19] TP_SPARE7 H_D#20 D[19]# D[51]# H_D#52
B25 RSVD[11] RSVD[20] C24 L25 D[20]# D[52]# AB21
H_D#21 L22 AC25 H_D#53

DATA GRP 1
D[21]# D[53]#

DATA GRP 3
Yonah Ball-out Rev 1.0 H_D#22 L23 AD20 H_D#54
D[22]# D[54]#

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H_D#23 M23 AE22 H_D#55
H_D#24 D[23]# D[55]# H_D#56
P25 D[24]# D[56]# AF23
H_D#25 P22 AD24 H_D#57
H_D#26 D[25]# D[57]# H_D#58 Layout note:
P23 D[26]# D[58]# AE21
H_D#27 T24 AD21 H_D#59 Comp0,2 connect with Zo=27.4ohm, make
4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#28 D[27]# D[59]# H_D#60

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R24 D[28]# D[60]# AE25 trace length shorter than 0.5".
H_D#29 L26 AF25 H_D#61
H_D#30 D[29]# D[61]# H_D#62 Comp1,3 connect with Zo=55ohm, make
T25 D[30]# D[62]# AF22
B B

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4,6,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#31 N24 AF26 H_D#63 trace length shorter than 0.5".
R3T1 D[31]# D[63]#
6 H_DSTBN#1 M24 DSTBN[1]# DSTBN[3]# AD23 H_DSTBN#3 6
1K N25 AE24
6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
XDP_TMS R1R4 54.9 1% 1% M26 AC20
6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6

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AD26 R26 COMP0 R3T3 27.4 1%
58 H_GTLREF GTLREF COMP[0]
XDP_TDI R2R3 54.9 1% MISC U26 COMP1 R3T2 54.9 1%
COMP[1] COMP2 R2T2 27.4 1%
COMP[2] U1
Layout note: Zo=55 ohm, R3R3 NO_STUFF R3U2 1K ACLKPH C26 V1 COMP3 R2T1 54.9 1%
XDP_BPM#5 R1R3 54.9 1% 2K TEST1 COMP[3]
0.5" max for GTLREF. 1% R3U1 51DCLKPH

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D25 TEST2 DPRSTP# E5 H_DPRSTP# 14,35
J2G1 B5
DPSLP# H_DPSLP# 14,35
DPWR# D24 H_DPWR# 6
XDP_TCK R2R4 54.9 1% B22 D6
30 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD 14,35
B23 BSEL[1] SLP# D7 H_CPUSLP# 6,35
30 CPU_BSEL1

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C21 AE6 R2U4 1K
30 CPU_BSEL2 BSEL[2] PSI# PSI# H_PWRGD_XDP 37
Yonah Ball-out Rev 1.0
Layout: Connect Place Series
test point TP3F1 TP3F1 Resistor on
with no stub
NO_STUFF H_PWRGD_XDP

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Without Stub

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NO_STUFF TP3D1 TP_CPN_L1 NO_STUFF TP3D2
A A
NO_STUFF TP3D3 TP_CPN_L3 NO_STUFF TP3D4 Capell Valley Intel Confidential
NO_STUFF TP3D5 TP_CPN_L6 NO_STUFF TP3D6 Title

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NO_STUFF TP3D7 TP_CPN_L8 NO_STUFF TP3D8 CPU (1 of 2)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 3 of 60
5 4 3 2 1
5 4 3 2 1

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U2E1D
A4 VSS[001] VSS[082] P6
53,56,58 +VCC_CORE 53,56,58 +VCC_CORE A8 P21
U2E1C VSS[002] VSS[083]
A11 P24

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VSS[003] VSS[084]
A7 VCC[001] VCC[068] AB20 A14 VSS[004] VSS[085] R2
D A9 VCC[002] VCC[069] AB7 A16 VSS[005] VSS[086] R5 D

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A10 VCC[003] VCC[070] AC7 A19 VSS[006] VSS[087] R22
A12 VCC[004] VCC[071] AC9 A23 VSS[007] VSS[088] R25
A13 VCC[005] VCC[072] AC12 A26 VSS[008] VSS[089] T1
A15 VCC[006] VCC[073] AC13 B6 VSS[009] VSS[090] T4
A17 VCC[074] AC15 B8 VSS[091] T23

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VCC[007] VSS[010]
A18 VCC[008] VCC[075] AC17 B11 VSS[011] VSS[092] T26
A20 VCC[009] VCC[076] AC18 B13 VSS[012] VSS[093] U3
B7 VCC[010] VCC[077] AD7 B16 VSS[013] VSS[094] U6
B9 VCC[011] VCC[078] AD9 B19 VSS[014] VSS[095] U21
B10 AD10 B21 U24

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VCC[012] VCC[079] VSS[015] VSS[096]
B12 VCC[013] VCC[080] AD12 B24 VSS[016] VSS[097] V2
B14 VCC[014] VCC[081] AD14 C5 VSS[017] VSS[098] V5
B15 VCC[015] VCC[082] AD15 C8 VSS[018] VSS[099] V22
B17 VCC[016] VCC[083] AD17 C11 VSS[019] VSS[100] V25
B18 VCC[017] VCC[084] AD18 C14 VSS[020] VSS[101] W1
B20 VCC[018] VCC[085] AE9 C16 VSS[021] VSS[102] W4
C9 VCC[019] VCC[086] AE10 C19 VSS[022] VSS[103] W23
C10 VCC[020] VCC[087] AE12 C2 VSS[023] VSS[104] W26
C12 VCC[021] VCC[088] AE13 C22 VSS[024] VSS[105] Y3

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C13 VCC[022] VCC[089] AE15 C25 VSS[025] VSS[106] Y6
C15 VCC[023] VCC[090] AE17 D1 VSS[026] VSS[107] Y21
C17 VCC[024] VCC[091] AE18 D4 VSS[027] VSS[108] Y24
C18 VCC[025] VCC[092] AE20 D8 VSS[028] VSS[109] AA2
D9 VCC[026] VCC[093] AF9 D11 VSS[029] VSS[110] AA5
D10 VCC[027] VCC[094] AF10 D13 VSS[030] VSS[111] AA8
D12 VCC[028] VCC[095] AF12 D16 VSS[031] VSS[112] AA11
D14 VCC[029] VCC[096] AF14 D19 VSS[032] VSS[113] AA14

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D15 VCC[030] VCC[097] AF15 D23 VSS[033] VSS[114] AA16
D17 VCC[031] VCC[098] AF17 D26 VSS[034] VSS[115] AA19
D18 VCC[032] VCC[099] AF18 E3 VSS[035] VSS[116] AA22
E7 AF20 +V1.05S 3,6,9,10,14,17,30,37,45,48,53,56,58 E6 AA25
VCC[033] VCC[100] VSS[036] VSS[117]
C E9 VCC[034] E8 VSS[037] VSS[118] AB1 C

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E10 VCC[035] VCCP[01] V6 E11 VSS[038] VSS[119] AB4
E12 VCC[036] VCCP[02] G21 E14 VSS[039] VSS[120] AB8
E13 J6 C3T1 E16 AB11
VCC[037] VCCP[03] 270uF VSS[040] VSS[121]
E15 VCC[038] VCCP[04] K6 20% E19 VSS[041] VSS[122] AB13
E17 VCC[039] VCCP[05] M6 E21 VSS[042] VSS[123] AB16
E18 J21 E24 AB19

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VCC[040] VCCP[06] VSS[043] VSS[124]
E20 VCC[041] VCCP[07] K21 F5 VSS[044] VSS[125] AB23
F7 VCC[042] VCCP[08] M21 F8 VSS[045] VSS[126] AB26
F9 VCC[043] VCCP[09] N21 F11 VSS[046] VSS[127] AC3
F10 N6 10,17,27,48,56,58 +V1.5S F13 AC6
VCC[044] VCCP[10] VSS[047] VSS[128]

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F12 VCC[045] VCCP[11] R21 F16 VSS[048] VSS[129] AC8
F14 R6 +V1.5S 10,17,27,48,56,58 F19 AC11
VCC[046] VCCP[12] VSS[049] VSS[130]
F15 VCC[047] VCCP[13] T21 F2 VSS[050] VSS[131] AC14
F17 T6 C3T4 C3T3 LAYOUT NOTE: PLACE C3T4 F22 AC16
VCC[048] VCCP[14] VSS[051] VSS[132]
F18 VCCP[15] V21 F25 VSS[133] AC19
VCC[049] NEAR PIN B26 VSS[052]

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F20 W21 0.01uF 10uF G4 AC21
VCC[050] VCCP[16] VSS[053] VSS[134]
AA7 VCC[051] G1 VSS[054] VSS[135] AC24
AA9 VCC[052] VCCA B26 G23 VSS[055] VSS[136] AD2

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AA10 VCC[053] G26 VSS[056] VSS[137] AD5
AA12 53,56,58 +VCC_CORE H3 AD8
VCC[054] VSS[057] VSS[138]
AA13 VCC[055] VID[0] AD6 H_VID0 51 H6 VSS[058] VSS[139] AD11
AA15 VCC[056] VID[1] AF5 H_VID1 51 H21 VSS[059] VSS[140] AD13
AA17 VCC[057] VID[2] AE5 H_VID2 51 H24 VSS[060] VSS[141] AD16

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AA18 VCC[058] VID[3] AF4 H_VID3 51 J2 VSS[061] VSS[142] AD19
AA20 VCC[059] VID[4] AE3 H_VID4 51 J5 VSS[062] VSS[143] AD22
AB9 VCC[060] VID[5] AF2 H_VID5 51 J22 VSS[063] VSS[144] AD25
AC10 AE2 R2R1 J25 AE1
VCC[061] VID[6] H_VID6 51 100 VSS[064] VSS[145]
AB10 VCC[062] 1% K1 VSS[065] VSS[146] AE4

o
AB12 VCC[063] K4 VSS[066] VSS[147] AE8
AB14 AF7 Layout Note: K23 AE11
VCC[064] VCCSENSE VCCSENSE VSS[067] VSS[148]
AB15 VCC[065] Route VCCSENSE and VSSSENSE traces at K26 VSS[068] VSS[149] AE14
B B

t
AB17 VCC[066] 27.4 Ohms with 50 mil spacing. L3 VSS[069] VSS[150] AE16
AB18 VCC[067] VSSSENSE AE7 VSSSENSE Place PU and PD within 1 inch of CPU. L6 VSS[070] VSS[151] AE19
L21 VSS[071] VSS[152] AE23
Yonah Ball-out Rev 1.0 R2R2 L24 AE26
100 VSS[072] VSS[153]
1% M2 VSS[073] VSS[154] AF3

p
M5 VSS[074] VSS[155] AF6
M22 VSS[075] VSS[156] AF8
M25 VSS[076] VSS[157] AF11
N1 VSS[077] VSS[158] AF13
N4 VSS[078] VSS[159] AF16

la
N23 VSS[079] VSS[160] AF19
N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] AF24

Yonah Ball-out Rev 1.0

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A A
Capell Valley Intel Confidential
Title

w
CPU (2 of 2)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

o m
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
CPU Thermal Sensor
7,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S

c
D Layout Note: R3N4
10K
R3N6
10K
D

.
Route H_THERMDA and C3N2
H_THERMDC on same layer 0.1uF
J3B1
w/ 10 mil trace & 10 mil R3N7
Default Stuffing: 1-2 3-4
spacing. Route away from 10K U3B2
Option Stuffing: 1-X 3-X SMB_THRM_CLK 32,35

s
noise sources with ground 1 VDD 8
SCLK
guard tracks on each side.
J3B1 THERM_DXP R3N3 499 1% ADT_THERM_DXP
2 D+ 7
C3N3 SDATA
3 H_THERMDA 1 2 SMB_THRM_DATA 32,35
3 4 ADT_THERM_DXN
3 D- 6 THRM_ALERT#

it c
3 H_THERMDC THERM_DXN R3N8 499 1% 1000pF ALRT#/THM2#
2X2HDR ADT_THM# 4 5
THM# GND PM_THRM# 16,32,35
R3N5 0
ADT7461A-TEMP MON NO_STUFF

Note: No-Stuff R3N5 for normal


operation. No Stuff R9G18 if
R3N5 is stuffed
3Pin_Recepticle
J4A1

a
2 1
THERMDP THERMDN

GND0 GND2
GND1 3 4 5 6 GND3

m
NO_STUFF

C Thermal Diode Conn C

h e
s c
p -
o
B Fan Power Control B

t
Place fan connector near CPU

p
Q2B3

SI7458DP J3C1
10,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S 3
V5S_FAN

la
2 5 1
1 2
3

C3D1 C3B2
R2B4 C2B4 CR3D1 CONN2_HDR

.
1M 0.1uF 22uF 1N4148
4

1000pF
1
3 FAN_ON_Q

FAN_ON_D#

R2B3

w
100K

Q2B2
1 BSS138
32,35 FAN_ON

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2

A A
Capell Valley Intel Confidential
Title

w
CPU THERMAL SENSOR AND FAN

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 5 of 60
5 4 3 2 1
5 4 3 2 1

H_XRCOMP

m
R4T3
24.9
1%

o
U5E1A
3 H_D#[63:0] H_D#0 H_A#[31:3] 3
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S F1 H9 H_A#3
H_D#1 H_D#_0 H_A#_3 H_A#4
J1 C9

c
H_D#2 H_D#_1 H_A#_4 H_A#5
H1 H_D#_2 H_A#_5 E11
D H_D#3 J6 G11 H_A#6 D
H_D#4 H_D#_3 H_A#_6

.
R4E3 H3 F11 H_A#7
54.9 H_D#5 H_D#_4 H_A#_7 H_A#8
K2 H_D#_5 H_A#_8 G12
1% H_D#6 G1 F9 H_A#9
H_D#7 H_D#_6 H_A#_9 H_A#10
G2 H_D#_7 H_A#_10 H11
H_XSCOMP H_D#8 K9 J12 H_A#11
H_D#_8

s
H_D#9 H_A#_11 H_A#12
K1 H_D#_9 H_A#_12 G14
H_D#10 K7 D9 H_A#13
H_D#11 H_D#_10 H_A#_13 H_A#14
J8 H_D#_11 H_A#_14 J14
H_D#12 H4 H13 H_A#15
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#13 H_D#_12 H_A#_15 H_A#16
J3 J15

it c
H_D#14 H_D#_13 H_A#_16 H_A#17
K11 H_D#_14 H_A#_17 F14
H_D#15 G4 D12 H_A#18
H_D#16 H_D#_15 H_A#_18 H_A#19
T10 H_D#_16 H_A#_19 A11
R4E8 H_D#17 W11 C11 H_A#20
221 H_D#18 H_D#_17 H_A#_20 H_A#21
1% T3 H_D#_18 H_A#_21 A12
H_D#19 U7 A13 H_A#22
H_D#20 H_D#_19 H_A#_22 H_A#23
U9 H_D#_20 H_A#_23 E13
H_D#21 U11 G13 H_A#24
H_XSWING 58 H_D#22 H_D#_21 H_A#_24 H_A#25
T11 H_D#_22 H_A#_25 F12 Note: H_CPURST#
H_D#23 H_A#26

a
W9 B12
H_D#24 T1
H_D#_23 H_A#_26
B14 H_A#27 has T topology
H_D#25 H_D#_24 H_A#_27 H_A#28
T8 H_D#_25 H_A#_28 C12
R4T4 C4T8 H_D#26 T4 A14 H_A#29 3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S
100 H_D#27 H_D#_26 H_A#_29 H_A#30
1% W7 H_D#_27 H_A#_30 C14
0.1uF H_D#28 U5 D14 H_A#31
H_D#29 H_D#_28 H_A#_31 R4E5
T9 H_D#_29
H_D#30 100
W6 H_D#_30 H_ADS# E8 H_ADS# 3 1%
H_D#31

m
T5 H_D#_31 H_ADSTB#_0 B9 H_ADSTB#0 3
H_D#32 AB7 C13
H_D#33 H_D#_32 H_ADSTB#_1 H_ADSTB#1 3
AA9 H_D#_33 H_VREF J13 H_VREF

HOST
H_D#34 W4 C6
H_D#_34 H_BNR# H_BNR# 3
C H_D#35 W3 H_D#_35 H_BPRI# F6 H_BPRI# 3
C5T10 C
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#36 0.1uF R4E4

e
Y3 H_D#_36 H_BREQ#0 C7 H_BREQ#0 3
H_D#37 Y7 B7 200
H_D#38 H_D#_37 H_CPURST# H_CPURST# 3,37 1%
W5 H_D#_38 H_DBSY# A7 H_DBSY# 3
H_D#39 Y10 C3
H_D#_39 H_DEFER# H_DEFER# 3
R4T2 H_D#40 AB8 J9
H_D#41 H_D#_40 H_DPWR# H_DPWR# 3
54.9 W2 H8

h
H_D#42 H_D#_41 H_DRDY# H_DRDY# 3
1% AA4 K13
H_D#43 H_D#_42 H_VREF
AA7 H_D#_43 H_DINV#[3:0] 3
H_D#44 AA2 J7 H_DINV#0
H_YSCOMP H_D#45 H_D#_44 H_DINV#_0 H_DINV#1
AA6 H_D#_45 H_DINV#_1 W8
H_D#46 H_DINV#2

c
AA10 H_D#_46 H_DINV#_2 U3
H_D#47 Y8 AB10 H_DINV#3
H_D#48 H_D#_47 H_DINV#_3
AA1 H_D#_48 H_DSTBN#[3:0] 3
H_D#49 AB4 K4 H_DSTBN#0
H_D#50 H_D#_49 H_DSTBN#_0 H_DSTBN#1
AC9 H_D#_50 H_DSTBN#_1 T7

s
3,4,9,10,14,17,30,37,45,48,53,56,58 +V1.05S H_D#51 AB11 Y5 H_DSTBN#2
H_D#52 H_D#_51 H_DSTBN#_2 H_DSTBN#3
AC11 H_D#_52 H_DSTBN#_3 AC4
H_D#53 AB3 H_D#_53 H_DSTBP#[3:0] 3

-
H_D#54 AC2 K3 H_DSTBP#0
R4E2 H_D#55 H_D#_54 H_DSTBP#_0
AD1 T6 H_DSTBP#1
221 H_D#56 H_D#_55 H_DSTBP#_1
AD9 AA5 H_DSTBP#2
1% H_D#57 H_D#_56 H_DSTBP#_2
AC1 AC5 H_DSTBP#3
H_D#58 H_D#_57 H_DSTBP#_3
AD7 H_D#_58
H_D#59

p
H_YSWING 58 AC6 H_D#_59
H_D#60 AB5 D3
H_D#61 H_D#_60 H_HIT# H_HIT# 3
AD10 H_D#_61 H_HITM# D4 H_HITM# 3
H_D#62 AD4 B3
H_D#63 H_D#_62 H_LOCK# H_LOCK# 3
AC8 H_D#_63
R4E1 C4T5

o
100 H_XRCOMP
1% E1 H_XRCOMP H_REQ#[4:0] 3
0.1uF H_XSCOMP E2 D8 H_REQ#0
B H_XSCOMP H_REQ#_0 B

t
H_XSWING E4 G8 H_REQ#1
H_XSWING H_REQ#_1
B8 H_REQ#2
H_YRCOMP H_REQ#_2
Y1 F8 H_REQ#3
H_YSCOMP H_YRCOMP H_REQ#_3
U1 A8 H_REQ#4
H_YSWING H_YSCOMP H_REQ#_4
W1 H_YSWING H_RS#[2:0] 3

p
B4 H_RS#0
H_RS#_0
AG2 E6 H_RS#1
30 CLK_MCH_BCLK H_CLKIN H_RS#_1
H_YRCOMP AG1 D6 H_RS#2
30 CLK_MCH_BCLK# H_CLKIN# H_RS#_2

H_SLPCPU# E3 H_CPUSLP# 3,35


R4T1

la
H_TRDY# E7 H_TRDY# 3
24.9
1% CALISTOGA_1p0

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A A
Capell Valley Intel Confidential
Title

w
CALISTOGA (1 OF 6)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

m
10,58 +V1.5S_PCIE

U5E1C R5E1 24.9 1%


D32 L_BKLTCTL EXP_A_COMPI D40 PEG_COMP
U5E1B 19 L_BKLTCTL
J30 L_BKLTEN EXP_A_COMPO D38

o
MCH_RSVD_[2:1] MCH_RSVD_0 19 L_BKLTEN
H32 RSVD_0 H30 L_CLKCTLA PEG_RXN[15:0] 13
MCH_RSVD_1 19,37 L_CLKCTLA PEG_RXN0
T32 RSVD_1 SM_CK_0 AY35 M_CLK_DDR0 21 H29 L_CLKCTLB EXP_A_RXN_0 F34
MCH_RSVD_2 19,37 L_CLKCTLB PEG_RXN1
R32 RSVD_2 SM_CK_1 AR1 M_CLK_DDR1 21 19 L_DDC_CLK G26 L_DDC_CLK EXP_A_RXN_1 G38
TP_MCH_RSVD_3 F3 RSVD_3 AW7 G25 H34 PEG_RXN2
TP_MCH_RSVD_4 SM_CK_2 M_CLK_DDR2 22 19 L_DDC_DATA L_IBG L_DDC_DATA EXP_A_RXN_2
F7 RSVD_4 AW40 B38 J38 PEG_RXN3

c
SM_CK_3 M_CLK_DDR3 22 L_IBG EXP_A_RXN_3

RSVD
MCH_RSVD_5 AG11 RSVD_5 TP5E1 NO_STUFF L_LVBG C35 L34 PEG_RXN4
MCH_RSVD_6 L_VBG EXP_A_RXN_4
D AF11 RSVD_6 SM_CK#_0 AW35 M_CLK_DDR#0 21 19 L_VDDEN F32 L_VDDEN EXP_A_RXN_5 M38 PEG_RXN5 D
MCH_RSVD_7

.
H7 RSVD_7 AT1 C33 N34 PEG_RXN6
MCH_RSVD_8 SM_CK#_1 M_CLK_DDR#1 21 L_VREFH EXP_A_RXN_6
J19 RSVD_8 AY7 C32 P38 PEG_RXN7
MCH_RSVD_9 SM_CK#_2 M_CLK_DDR#2 22 L_VREFL EXP_A_RXN_7
A41 RSVD_9 AY40 R34 PEG_RXN8
MCH_RSVD_10 SM_CK#_3 M_CLK_DDR#3 22 EXP_A_RXN_8
A35 RSVD_10 A33 T38 PEG_RXN9
MCH_RSVD_11 19 LA_CLKN LA_CLK# EXP_A_RXN_9
A34 RSVD_11 AU20 A32 V34 PEG_RXN10
SM_CKE_0 M_CKE0 21,23 19 LA_CLKP LA_CLK

s
MCH_RSVD_12 EXP_A_RXN_10 PEG_RXN11
D28 RSVD_12 SM_CKE_1 AT20 M_CKE1 21,23 19 LB_CLKN E27 LB_CLK# EXP_A_RXN_11 W38
MCH_RSVD_13 D27 RSVD_13 BA29 E26 Y34 PEG_RXN12
SM_CKE_2 M_CKE2 22,23 19 LB_CLKP LB_CLK EXP_A_RXN_12
AY29 AA38 PEG_RXN13
SM_CKE_3 M_CKE3 22,23 EXP_A_RXN_13

LVDS
C37 AB34 PEG_RXN14
19 LA_DATAN0 LA_DATA#_0 EXP_A_RXN_14
AW13 B35 AC38 PEG_RXN15

it c
SM_CS#_0 M_CS#0 21,23 19 LA_DATAN1 LA_DATA#_1 EXP_A_RXN_15
30 MCH_BSEL0 SM_CS#_1 AW12 M_CS#1 21,23 19 LA_DATAN2 A37 LA_DATA#_2 PEG_RXP[15:0] 13

MUXING
K16 AY21 D34 PEG_RXP0
30 MCH_BSEL1 CFG_0 SM_CS#_2 M_CS#2 22,23 EXP_A_RXP_0

GRAPHICS
K18 AW21 F38 PEG_RXP1
30 MCH_BSEL2 CFG_1 SM_CS#_3 M_CS#3 22,23 EXP_A_RXP_1
J18 G34 PEG_RXP2
12,13 MCH_CFG_[20:3] MCH_CFG_3 CFG_2 TP_M_OCDCOMP_0 EXP_A_RXP_2 PEG_RXP3
F18 CFG_3 SM_OCDCOMP_0 AL20 19 LA_DATAP0 B37 LA_DATA_0 EXP_A_RXP_3 H38
MCH_CFG_4 E15 AF10 TP_M_OCDCOMP_1 B34 J34 PEG_RXP4
MCH_CFG_5 CFG_4 SM_OCDCOMP_1 19 LA_DATAP1 LA_DATA_1 EXP_A_RXP_4
F15 A36 L38 PEG_RXP5
MCH_CFG_6 CFG_5 19 LA_DATAP2 LA_DATA_2 EXP_A_RXP_5
E18 BA13 M34 PEG_RXP6
MCH_CFG_7 CFG_6 SM_ODT_0 M_ODT0 21,23 EXP_A_RXP_6
D19 BA12 N38 PEG_RXP7
MCH_CFG_8 CFG_7 SM_ODT_1 M_ODT1 21,23 EXP_A_RXP_7 PEG_RXP8

a
D16 CFG_8 SM_ODT_2 AY20 M_ODT2 22,23 19 LB_DATAN0 G30 LB_DATA#_0 EXP_A_RXP_8 P34

CFG
MCH_CFG_9 G16 AU21 D30 R38 PEG_RXP9
MCH_CFG_10 CFG_9 SM_ODT_3 M_ODT3 22,23 19 LB_DATAN1 LB_DATA#_1 EXP_A_RXP_9

DDR
E16 F29 T34 PEG_RXP10
MCH_CFG_11 CFG_10 M_RCOMP# 19 LB_DATAN2 LB_DATA#_2 EXP_A_RXP_10
D15 AV9 V38 PEG_RXP11
MCH_CFG_12 CFG_11 SM_RCOMP# M_RCOMP EXP_A_RXP_11 PEG_RXP12
G15 CFG_12 SM_RCOMP AT9 EXP_A_RXP_12 W34
MCH_CFG_13 K15 Y38 PEG_RXP13
MCH_CFG_14 CFG_13 EXP_A_RXP_13 PEG_RXP14
C15 CFG_14 SM_VREF_0 AK1 M_VREF_MCH 47,58 19 LB_DATAP0 F30 LB_DATA_0 EXP_A_RXP_14 AA34

PCI-EXPRESS
MCH_CFG_15 H16 AK41 D29 AB38 PEG_RXP15
MCH_CFG_16 CFG_15 SM_VREF_1 19 LB_DATAP1 LB_DATA_1 EXP_A_RXP_15

m
G18 CFG_16 19 LB_DATAP2 F28 LB_DATA_2 PEG_TXN[15:0] 13
MCH_CFG_17 H15 Layout Note: F36 PEG_TXN0
MCH_CFG_18 CFG_17 EXP_A_TXN_0 PEG_TXN1
J25 CFG_18 G_CLKIN# AF33 CLK_PCIE_3GPLL# 31 Place 150 Ohm termination
EXP_A_TXN_1 G40
MCH_CFG_19 K27 AG33 resistors close to GMCH H36 PEG_TXN2
CFG_19 G_CLKIN CLK_PCIE_3GPLL 31 EXP_A_TXN_2
C MCH_CFG_20 PEG_TXN3 C
CLK
J26 CFG_20 D_REFCLKIN# A27 DREFCLK# 30 EXP_A_TXN_3 J40
PEG_TXN4

e
D_REFCLKIN A26 DREFCLK 30 18,20 TV_DACA_OUT A16 TV_DACA_OUT EXP_A_TXN_4 L36
G28 C40 C18 M40 PEG_TXN5
16 PM_BMBUSY# PM_BMBUSY# D_REFSSCLKIN# DREFSSCLK# 30 18,20 TV_DACB_OUT TV_DACB_OUT EXP_A_TXN_5
F25 D41 A19 N36 PEG_TXN6
21,23 PM_EXTTS#0 PM_EXTTS#_0 D_REFSSCLKIN DREFSSCLK 30 18,20 TV_DACC_OUT TV_DACC_OUT EXP_A_TXN_6
PM

TV
PM_EXTTS#1_R
H26 P40 PEG_TXN7
R6E4 0 PM_EXTTS#_1 R5T3 150 1% R4T5 TVIREF J20 EXP_A_TXN_7 PEG_TXN8
22,23 PM_EXTTS#1 G6 PM_THRMTRIP# DMI_TXN[3:0] 15 TV_IREF EXP_A_TXN_8 R36
AH33 AE35 DMI_TXN0 R4T7 150 1% 4.99k B16 T40 PEG_TXN9

h
3,14 PM_THRMTRIP# PWROK DMI_RXN_0 DMI_TXN1 R4T6 150 1% 1% TV_IRTNA EXP_A_TXN_9 PEG_TXN10
16 DELAY_VR_PWRGOOD AH34 RSTIN# DMI_RXN_1 AF39 B18 TV_IRTNB EXP_A_TXN_10 V36
AG35 DMI_TXN2 B19 W40 PEG_TXN11
13,15,24,28,32,41,42,57 DMI_RXN_2 DMI_TXN3 TV_IRTNC EXP_A_TXN_11
R5R1 100 RST_IN#_MCH AH39 Y36 PEG_TXN12
PLT_RST# DMI_RXN_3 EXP_A_TXN_12
MISC

H28 K30 AA40 PEG_TXN13


13 SDVO_CTRLCLK SDVO_CTRLCLK 20 TV_DCONSEL0 TV_DCONSEL0 EXP_A_TXN_13

c
H27 J29 AB36 PEG_TXN14
13 SDVO_CTRLDATA SDVO_CTRLDATA DMI_TXP0 DMI_TXP[3:0] 15 20 TV_DCONSEL1 TV_DCONSEL1 EXP_A_TXN_14
K28 AC35 AC40 PEG_TXN15
15 MCH_ICH_SYNC# LT_RESET# DMI_RXP_0 DMI_TXP1 EXP_A_TXN_15
DMI_RXP_1 AE39 PEG_TXP[15:0] 13
31 CLK_MCH_OE# DMI_TXP2 PEG_TXP0
DMI_RXP_2 AF35 18 CRT_BLUE E23 CRT_BLUE EXP_A_TXP_0 D36
TP_MCH_NC0 D1 AG39 DMI_TXP3 Layout Note: D23 F40 PEG_TXP1
NC0 DMI_RXP_3 CRT_BLUE# EXP_A_TXP_1

-s
TP_MCH_NC1 C41 Place 150 Ohm termination C22 G36 PEG_TXP2
NC1 18 CRT_GREEN CRT_GREEN EXP_A_TXP_2

VGA
TP_MCH_NC2 C1 resistors close to GMCH B22 H40 PEG_TXP3
TP_MCH_NC3 NC2 DMI_RXN[3:0] 15 CRT_GREEN# EXP_A_TXP_3
BA41 NC3 DMI_TXN_0 AE37 DMI_RXN0 18 CRT_RED A21 CRT_RED EXP_A_TXP_4 J36 PEG_TXP4
TP_MCH_NC4 BA40 AF41 DMI_RXN1 R5T4 150 1% B21 L40 PEG_TXP5
NC4 DMI_TXN_1 CRT_RED# EXP_A_TXP_5
NC

TP_MCH_NC5 BA39 NC5 DMI_TXN_2 AG37DMI_RXN2 R5T5 150 1%


EXP_A_TXP_6 M36 PEG_TXP6
TP_MCH_NC6 BA3 AH41DMI_RXN3 R5T6 150 1% N40 PEG_TXP7
TP_MCH_NC7 NC6 DMI_TXN_3 EXP_A_TXP_7
DMI

BA2 C26 P36 PEG_TXP8


TP_MCH_NC8 NC7 18 CRT_DDC_CLK CRT_DDC_CLK EXP_A_TXP_8
BA1 C25 R40 PEG_TXP9
TP_MCH_NC9 NC8 DMI_RXP0 DMI_RXP[3:0] 15 18 CRT_DDC_DATA CRT_DDC_DATA EXP_A_TXP_9

p
B41 AC37 G23 T36 PEG_TXP10
TP_MCH_NC10 NC9 DMI_TXP_0 CRT_HSYNC EXP_A_TXP_10
B2 NC10 DMI_TXP_1 AE41 DMI_RXP1 J22 CRT_IREF EXP_A_TXP_11 V40 PEG_TXP11
TP_MCH_NC11 AY41 AF37 DMI_RXP2 H23 W36 PEG_TXP12
TP_MCH_NC12 NC11 DMI_TXP_2 CRT_VSYNC EXP_A_TXP_12
AY1 NC12 DMI_TXP_3 AG41DMI_RXP3 18 CRT_HSYNC
R5E7 39 HSYNC
EXP_A_TXP_13 Y40 PEG_TXP13
TP_MCH_NC13 AW41 AA36 PEG_TXP14
NC13 EXP_A_TXP_14

VSYNC
TP_MCH_NC14 R5E5 255 1% CRTIREF PEG_TXP15

o
AW1 NC14 EXP_A_TXP_15 AB40
TP_MCH_NC15 A40
TP_MCH_NC16 NC15 CALISTOGA_1p0
A4 NC16
B B

t
TP_MCH_NC17 A39 R5E6 39
TP_MCH_NC18 NC17 18 CRT_VSYNC
A3 NC18

CALISTOGA_1p0

p
PM_EXTTS#1_R R6E5 0 R7N3 0
NO_STUFF PM_DPRSLPVR 16,35,51 L_IBG

la
58 EPOT_WIPER
NO_STUFF
R7N4
1.5K

.
1%

+V3.3S 5,10,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

R5P2 10K PM_EXTTS#0

w
R5P3 10K PM_EXTTS#1

+V1.8 9,21,22,34,46,47,56,58

w
R4R1
80.6
1%
A M_RCOMP# A
Capell Valley Intel Confidential
M_RCOMP
Title

w
R4R2
80.6 CALISTOGA (2 OF 6)
1%

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 7 of 60
5 4 3 2 1
5 4 3 2 1

o m
c
21 M_A_DQ[63:0] 22 M_B_DQ[63:0]
U5E1D U5E1E
D M_A_DQ0 AJ35 AU12 M_B_DQ0 AK39 D
M_A_DQ1 SA_DQ0 SA_BS_0 M_A_BS0 21,23 M_B_DQ1 SB_DQ0

.
AJ34 SA_DQ1 SA_BS_1 AV14 M_A_BS1 21,23 AJ37 SB_DQ1 SB_BS_0 AT24 M_B_BS0 22,23
M_A_DQ2 AM31 BA20 M_B_DQ2 AP39 AV23
M_A_DQ3 SA_DQ2 SA_BS_2 M_A_BS2 21,23 M_B_DQ3 SB_DQ2 SB_BS_1 M_B_BS1 22,23
AM33 SA_DQ3 M_A_CAS# 21,23 AR41 SB_DQ3 SB_BS_2 AY28 M_B_BS2 22,23
M_A_DQ4 AJ36 AY13 M_B_DQ4 AJ38
M_A_DQ5 SA_DQ4 SA_CAS# M_A_DM0 M_A_DM[7:0] 21 M_B_DQ5 SB_DQ4 M_B_CAS# 22,23
AK35 SA_DM_0 AJ33 AK38 SB_CAS# AR24 M_B_DM[7:0] 22

s
M_A_DQ6 SA_DQ5 M_A_DM1 M_B_DQ6 SB_DQ5 M_B_DM0
AJ32 SA_DQ6 SA_DM_1 AM35 AN41 SB_DQ6 SB_DM_0 AK36
M_A_DQ7 AH31 AL26 M_A_DM2 M_B_DQ7 AP41 AR38 M_B_DM1
M_A_DQ8 SA_DQ7 SA_DM_2 M_A_DM3 M_B_DQ8 SB_DQ7 SB_DM_1 M_B_DM2
AN35 SA_DQ8 SA_DM_3 AN22 AT40 SB_DQ8 SB_DM_2 AT36
M_A_DQ9 AP33 AM14 M_A_DM4 M_B_DQ9 AV41 BA31 M_B_DM3
M_A_DQ10 SA_DQ9 SA_DM_4 M_A_DM5 M_B_DQ10 SB_DQ9 SB_DM_3 M_B_DM4
AR31 AL9 AU38 AL17

it c
M_A_DQ11 SA_DQ10 SA_DM_5 M_A_DM6 M_B_DQ11 SB_DQ10 SB_DM_4 M_B_DM5
AP31 SA_DQ11 SA_DM_6 AR3 AV38 SB_DQ11 SB_DM_5 AH8
M_A_DQ12 AN38 AH4 M_A_DM7 M_B_DQ12 AP38 BA5 M_B_DM6
M_A_DQ13 SA_DQ12 SA_DM_7 M_B_DQ13 SB_DQ12 SB_DM_6 M_B_DM7
AM36 SA_DQ13 M_A_DQS[7:0] 21 AR40 SB_DQ13 SB_DM_7 AN4

A
M_A_DQ14 AM34 AK33 M_A_DQS0 M_B_DQ14 AW38
SA_DQ14 SA_DQS_0 SB_DQ14 M_B_DQS[7:0] 22

B
M_A_DQ15 AN33 AT33 M_A_DQS1 M_B_DQ15 AY38 AM39 M_B_DQS0
M_A_DQ16 SA_DQ15 SA_DQS_1 M_A_DQS2 M_B_DQ16 SB_DQ15 SB_DQS_0 M_B_DQS1
AK26 SA_DQ16 SA_DQS_2 AN28 BA38 SB_DQ16 SB_DQS_1 AT39
M_A_DQ17 AL27 AM22 M_A_DQS3 M_B_DQ17 AV36 AU35 M_B_DQS2
M_A_DQ18 SA_DQ17 SA_DQS_3 M_A_DQS4 M_B_DQ18 SB_DQ17 SB_DQS_2 M_B_DQS3
AM26 AN12 AR36 AR29

MEMORY
M_A_DQ19 SA_DQ18 SA_DQS_4 M_A_DQS5 M_B_DQ19 SB_DQ18 SB_DQS_3 M_B_DQS4
AN24 AN8 AP36 AR16

MEMORY
M_A_DQ20 SA_DQ19 SA_DQS_5 M_A_DQS6 M_B_DQ20 SB_DQ19 SB_DQS_4 M_B_DQS5

a
AK28 SA_DQ20 SA_DQS_6 AP3 BA36 SB_DQ20 SB_DQS_5 AR10
M_A_DQ21 AL28 AG5 M_A_DQS7 M_B_DQ21 AU36 AR7 M_B_DQS6
M_A_DQ22 SA_DQ21 SA_DQS_7 M_A_DQS#0 M_A_DQS#[7:0] 21 M_B_DQ22 SB_DQ21 SB_DQS_6 M_B_DQS7
AM24 SA_DQ22 SA_DQS#_0 AK32 AP35 SB_DQ22 SB_DQS_7 AN5 M_B_DQS#[7:0] 22
M_A_DQ23 AP26 AU33 M_A_DQS#1 M_B_DQ23 AP34 AM40 M_B_DQS#0
M_A_DQ24 SA_DQ23 SA_DQS#_1 M_A_DQS#2 M_B_DQ24 SB_DQ23 SB_DQS#_0 M_B_DQS#1
AP23 SA_DQ24 SA_DQS#_2 AN27 AY33 SB_DQ24 SB_DQS#_1 AU39
M_A_DQ25 AL22 AM21 M_A_DQS#3 M_B_DQ25 BA33 AT35 M_B_DQS#2
M_A_DQ26 SA_DQ25 SA_DQS#_3 M_A_DQS#4 M_B_DQ26 SB_DQ25 SB_DQS#_2 M_B_DQS#3
AP21 SA_DQ26 SA_DQS#_4 AM12 AT31 SB_DQ26 SB_DQS#_3 AP29
M_A_DQ27 AN20 AL8 M_A_DQS#5 M_B_DQ27 AU29 AP16 M_B_DQS#4
M_A_DQ28 SA_DQ27 SA_DQS#_5 M_A_DQS#6 M_B_DQ28 SB_DQ27 SB_DQS#_4 M_B_DQS#5

m
AL23 SA_DQ28 SA_DQS#_6 AN3 AU31 SB_DQ28 SB_DQS#_5 AT10
M_A_DQ29 AP24 AH5 M_A_DQS#7 M_B_DQ29 AW31 AT7 M_B_DQS#6
M_A_DQ30 SA_DQ29 SA_DQS#_7 M_B_DQ30 SB_DQ29 SB_DQS#_6 M_B_DQS#7
AP20 SA_DQ30 M_A_A[13:0] 21,23 AV29 SB_DQ30 SB_DQS#_7 AP5
M_A_DQ31 AT21 AY16 M_A_A0 M_B_DQ31 AW29
SYSTEM

SA_DQ31 SA_MA_0 SB_DQ31 M_B_A[13:0] 22,23


C M_A_DQ32 AR12 AU14 M_A_A1 M_B_DQ32 AM19 AY23 M_B_A0 C

SYSTEM
M_A_DQ33 SA_DQ32 SA_MA_1 M_A_A2 M_B_DQ33 SB_DQ32 SB_MA_0 M_B_A1

e
AR14 SA_DQ33 SA_MA_2 AW16 AL19 SB_DQ33 SB_MA_1 AW24
M_A_DQ34 AP13 BA16 M_A_A3 M_B_DQ34 AP14 AY24 M_B_A2
M_A_DQ35 SA_DQ34 SA_MA_3 M_A_A4 M_B_DQ35 SB_DQ34 SB_MA_2 M_B_A3
AP12 SA_DQ35 SA_MA_4 BA17 AN14 SB_DQ35 SB_MA_3 AR28
M_A_DQ36 AT13 AU16 M_A_A5 M_B_DQ36 AN17 AT27 M_B_A4
M_A_DQ37 SA_DQ36 SA_MA_5 M_A_A6 M_B_DQ37 SB_DQ36 SB_MA_4 M_B_A5
AT12 SA_DQ37 SA_MA_6 AV17 AM16 SB_DQ37 SB_MA_5 AT28
M_A_DQ38 AL14 AU17 M_A_A7 M_B_DQ38 AP15 AU27 M_B_A6

h
M_A_DQ39 SA_DQ38 SA_MA_7 M_A_A8 M_B_DQ39 SB_DQ38 SB_MA_6 M_B_A7
AL12 SA_DQ39 SA_MA_8 AW17 AL15 SB_DQ39 SB_MA_7 AV28
M_A_DQ40 AK9 AT16 M_A_A9 M_B_DQ40 AJ11 AV27 M_B_A8
M_A_DQ41 SA_DQ40 SA_MA_9 M_A_A10 M_B_DQ41 SB_DQ40 SB_MA_8 M_B_A9
AN7 SA_DQ41 SA_MA_10 AU13 AH10 SB_DQ41 SB_MA_9 AW27
M_A_DQ42 AK8 AT17 M_A_A11 M_B_DQ42 AJ9 AV24 M_B_A10
M_A_DQ43 SA_DQ42 SA_MA_11 M_A_A12 M_B_DQ43 SB_DQ42 SB_MA_10 M_B_A11

c
AK7 SA_DQ43 SA_MA_12 AV20 AN10 SB_DQ43 SB_MA_11 BA27
M_A_DQ44 M_A_A13 M_B_DQ44 M_B_A12
DDR

AP9 SA_DQ44 SA_MA_13 AV12 AK13 SB_DQ44 SB_MA_12 AY27


M_A_DQ45 M_B_DQ45 M_B_A13

DDR
AN9 SA_DQ45 AH11 SB_DQ45 SB_MA_13 AR23
M_A_DQ46 AT5 AW14 M_B_DQ46 AK10
M_A_DQ47 SA_DQ46 SA_RAS# M_A_RAS# 21,23 M_B_DQ47 SB_DQ46
AL5 SA_DQ47 SA_RCVENIN# AK23 TP_MA_RCVENIN# AJ8 SB_DQ47 SB_RAS# AU23 M_B_RAS# 22,23

s
M_A_DQ48 AY2 AK24 TP_MA_RCVENOUT# M_B_DQ48 BA10 AK16 TP_MB_RCVENIN#
M_A_DQ49 SA_DQ48 SA_RCVENOUT# M_B_DQ49 SB_DQ48 SB_RCVENIN#
AW2 SA_DQ49 SA_WE# AY14 M_A_WE# 21,23 AW10 SB_DQ49 SB_RCVENOUT# AK18 TP_MB_RCVENOUT#
M_A_DQ50 AP1 M_B_DQ50 BA4 AR27
SA_DQ50 SB_DQ50 SB_WE# M_B_WE# 22,23

-
M_A_DQ51 AN2 M_B_DQ51 AW4
M_A_DQ52 SA_DQ51 M_B_DQ52 SB_DQ51
AV2 SA_DQ52 AY10 SB_DQ52
M_A_DQ53 AT3 M_B_DQ53 AY9
M_A_DQ54 SA_DQ53 M_B_DQ54 SB_DQ53
AN1 SA_DQ54 AW5 SB_DQ54
M_A_DQ55 AL2 M_B_DQ55 AY5
M_A_DQ56 SA_DQ55 M_B_DQ56 SB_DQ55

p
AG7 SA_DQ56 AV4 SB_DQ56
M_A_DQ57 AF9 M_B_DQ57 AR5
M_A_DQ58 SA_DQ57 M_B_DQ58 SB_DQ57
AG4 SA_DQ58 AK4 SB_DQ58
M_A_DQ59 AF6 M_B_DQ59 AK3
M_A_DQ60 SA_DQ59 M_B_DQ60 SB_DQ59
AG9 SA_DQ60 AT4 SB_DQ60
M_A_DQ61 M_B_DQ61

o
AH6 SA_DQ61 AK5 SB_DQ61
M_A_DQ62 AF4 M_B_DQ62 AJ5
M_A_DQ63 SA_DQ62 M_B_DQ63 SB_DQ62
AF8 SA_DQ63 AJ3 SB_DQ63
B B

t
CALISTOGA_1p0 CALISTOGA_1p0

la p
w .
w
A A
Capell Valley Intel Confidential
Title

w
CALISTOGA (3 OF 6)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 8 of 60
5 4 3 2 1
5 4 3 2 1
+V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58
U5E1G
AA33 VCC_0
W33 VCC_1

m
P33 VCC_2
N33 VCC_3
L33 VCC_4 VCC_SM_0 AU41
J33 VCC_5 VCC_SM_1 AT41 VCCSM_LF4
AA32 VCC_6 VCC_SM_2 AM41 VCCSM_LF5 C5D2 +V1.05S 3,4,6,10,14,17,30,37,45,48,53,56,58

o
Y32 VCC_7 AU40 C5D4
VCC_SM_3 0.47uF
W32 VCC_8 VCC_SM_4 BA34
V32 VCC_9 AY34 0.47uF
VCC_SM_5
P32 VCC_10 VCC_SM_6 AW34
N32 VCC_11 AV34 U5E1F

c
VCC_SM_7 C4T7 C4T6 C5T6 C5T2 C5T7 C5T4 C5T5 C5T3
M32 VCC_12 VCC_SM_8 AU34 AD27 VCC_NCTF0
D L32 VCC_13 AT34 270uF 270uF 10uF 1uF 10uF 0.22uF 0.22uF 0.22uF AC27 AE27 D
VCC_SM_9 20% VCC_NCTF1 VSS_NCTF0

.
J32 VCC_14 AR34 2.0V, 3.3Arms 20% AB27 AE26
VCC_SM_10 VCC_NCTF2 VSS_NCTF1
AA31 VCC_15 VCC_SM_11 BA30 AA27 VCC_NCTF3 VSS_NCTF2 AE25
W31 VCC_16 VCC_SM_12 AY30 Y27 VCC_NCTF4 VSS_NCTF3 AE24
V31 VCC_17 VCC_SM_13 AW30 W27 VCC_NCTF5 VSS_NCTF4 AE23
T31 VCC_18 VCC_SM_14 AV30 V27 VSS_NCTF5 AE22

s
VCC_NCTF6
R31 VCC_19 VCC_SM_15 AU30 U27 VCC_NCTF7 VSS_NCTF6 AE21
P31 VCC_20 VCC_SM_16 AT30 T27 VCC_NCTF8 VSS_NCTF7 AE20
N31 VCC_21 VCC_SM_17 AR30 R27 VCC_NCTF9 VSS_NCTF8 AE19
M31 VCC_22 VCC_SM_18 AP30 AD26 VCC_NCTF10 VSS_NCTF9 AE18
AA30 VCC_23 AN30 AC26 AC17

it c
VCC_SM_19 VCC_NCTF11 VSS_NCTF10
Y30 VCC_24 VCC_SM_20 AM30 AB26 VCC_NCTF12 VSS_NCTF11 Y17
W30 VCC_25 VCC_SM_21 AM29 AA26 VCC_NCTF13 VSS_NCTF12 U17
V30 VCC_26 VCC_SM_22 AL29 Y26 VCC_NCTF14
U30 VCC_27 VCC_SM_23 AK29 W26 VCC_NCTF15
T30 VCC_28 VCC_SM_24 AJ29 V26 VCC_NCTF16
R30 VCC_29 AH29 U26 10,58 +V1.5S_AUX
VCC_SM_25 VCC_NCTF17
P30 VCC_30 VCC_SM_26 AJ28 T26 VCC_NCTF18
N30 VCC_31 VCC_SM_27 AH28 R26 VCC_NCTF19 VCCAUX_NCTF0 AG27
M30 VCC_32 VCC_SM_28 AJ27 AD25 VCC_NCTF20 VCCAUX_NCTF1 AF27

a
L30 VCC_33 VCC_SM_29 AH27 AC25 VCC_NCTF21 VCCAUX_NCTF2 AG26
AA29 VCC_34 VCC_SM_30 BA26 AB25 VCC_NCTF22 VCCAUX_NCTF3 AF26
Y29 VCC_35 VCC_SM_31 AY26 AA25 VCC_NCTF23 VCCAUX_NCTF4 AG25
W29 VCC_36 VCC_SM_32 AW26 Y25 VCC_NCTF24 VCCAUX_NCTF5 AF25
V29 VCC_37 VCC_SM_33 AV26 W25 VCC_NCTF25 VCCAUX_NCTF6 AG24
U29 VCC_38 VCC_SM_34 AU26 V25 VCC_NCTF26 VCCAUX_NCTF7 AF24
R29 VCC_39 VCC_SM_35 AT26 U25 VCC_NCTF27 VCCAUX_NCTF8 AG23
P29 VCC_40 VCC_SM_36 AR26 T25 VCC_NCTF28 VCCAUX_NCTF9 AF23

m
M29 VCC_41 VCC_SM_37 AJ26 R25 VCC_NCTF29 VCCAUX_NCTF10 AG22
L29 VCC_42 VCC_SM_38 AH26 AD24 VCC_NCTF30 VCCAUX_NCTF11 AF22
AB28 VCC_43 VCC_SM_39 AJ25 AC24 VCC_NCTF31 VCCAUX_NCTF12 AG21
AA28 VCC_44 VCC_SM_40 AH25 AB24 VCC_NCTF32 VCCAUX_NCTF13 AF21
C Y28 VCC_45 VCC_SM_41 AJ24 AA24 VCC_NCTF33 VCCAUX_NCTF14 AG20 C

e
V28 VCC_46 VCC_SM_42 AH24 Y24 VCC_NCTF34 VCCAUX_NCTF15 AF20
U28 VCC_47 VCC_SM_43 BA23 W24 VCC_NCTF35 VCCAUX_NCTF16 AG19
T28 VCC_48 AJ23 C5D3 V24 AF19
VCC_SM_44 VCC_NCTF36 VCCAUX_NCTF17
R28 VCC_49 VCC_SM_45 BA22 U24 VCC_NCTF37 VCCAUX_NCTF18 R19
P28 VCC_50 AY22 0.47uF T24 AG18
VCC_SM_46 VCC_NCTF38 VCCAUX_NCTF19
N28 VCC_51 AW22 R24 AF18

h
VCC_SM_47 VCC_NCTF39 VCCAUX_NCTF20
M28 VCC_52 VCC_SM_48 AV22 AD23 VCC_NCTF40 VCCAUX_NCTF21 R18
L28 VCC_53 VCC_SM_49 AU22 V23 VCC_NCTF41 VCCAUX_NCTF22 AG17
P27 VCC_54 VCC_SM_50 AT22 U23 VCC_NCTF42 VCCAUX_NCTF23 AF17
N27 VCC_55 VCC_SM_51 AR22 T23 VCC_NCTF43 VCCAUX_NCTF24 AE17

c
M27 VCC_56 VCC_SM_52 AP22 R23 VCC_NCTF44 VCCAUX_NCTF25 AD17
L27 VCC_57 VCC_SM_53 AK22 AD22 VCC_NCTF45 VCCAUX_NCTF26 AB17
P26 VCC_58 VCC_SM_54 AJ22 V22 VCC_NCTF46 VCCAUX_NCTF27 AA17
N26 VCC_59 VCC_SM_55 AK21 U22 VCC_NCTF47 VCCAUX_NCTF28 W17
L26 VCC_60 VCC_SM_56 AK20 T22 VCC_NCTF48 VCCAUX_NCTF29 V17

s
N25 VCC_61 VCC_SM_57 BA19 R22 VCC_NCTF49 VCCAUX_NCTF30 T17
M25 VCC_62 AY19 AD21 R17
L25 VCC_63
VCC_SM_58
VCC_SM_59 AW19 V21
VCC_NCTF50
VCC_NCTF51 NCTF VCCAUX_NCTF31
VCCAUX_NCTF32 AG16

-
P24 VCC_64 VCC_SM_60 AV19 U21 VCC_NCTF52 VCCAUX_NCTF33 AF16
N24 VCC_65 VCC_SM_61 AU19 T21 VCC_NCTF53 VCCAUX_NCTF34 AE16
M24 VCC_66 VCC_SM_62 AT19 R21 VCC_NCTF54 VCCAUX_NCTF35 AD16
AB23 VCC_67 VCC_SM_63 AR19 AD20 VCC_NCTF55 VCCAUX_NCTF36 AC16
AA23 VCC_68 AP19 V20 AB16
VCC VCC_SM_64 VCC_NCTF56 VCCAUX_NCTF37

p
Y23 VCC_69 VCC_SM_65 AK19 U20 VCC_NCTF57 VCCAUX_NCTF38 AA16
P23 VCC_70 VCC_SM_66 AJ19 T20 VCC_NCTF58 VCCAUX_NCTF39 Y16
N23 VCC_71 VCC_SM_67 AJ18 R20 VCC_NCTF59 VCCAUX_NCTF40 W16
M23 VCC_72 VCC_SM_68 AJ17 AD19 VCC_NCTF60 VCCAUX_NCTF41 V16
L23 VCC_73 VCC_SM_69 AH17 V19 VCC_NCTF61 VCCAUX_NCTF42 U16

o
AC22 VCC_74 VCC_SM_70 AJ16 U19 VCC_NCTF62 VCCAUX_NCTF43 T16
AB22 VCC_75 VCC_SM_71 AH16 T19 VCC_NCTF63 VCCAUX_NCTF44 R16
Y22 VCC_76 VCC_SM_72 BA15 AD18 VCC_NCTF64 VCCAUX_NCTF45 AG15
B B

t
W22 VCC_77 VCC_SM_73 AY15 AC18 VCC_NCTF65 VCCAUX_NCTF46 AF15
P22 VCC_78 VCC_SM_74 AW15 AB18 VCC_NCTF66 VCCAUX_NCTF47 AE15
N22 VCC_79 VCC_SM_75 AV15 AA18 VCC_NCTF67 VCCAUX_NCTF48 AD15
M22 VCC_80 VCC_SM_76 AU15 Y18 VCC_NCTF68 VCCAUX_NCTF49 AC15
L22 VCC_81 VCC_SM_77 AT15 W18 VCC_NCTF69 VCCAUX_NCTF50 AB15

p
AC21 VCC_82 VCC_SM_78 AR15 V18 VCC_NCTF70 VCCAUX_NCTF51 AA15
AA21 VCC_83 VCC_SM_79 AJ15 U18 VCC_NCTF71 VCCAUX_NCTF52 Y15
W21 VCC_84 VCC_SM_80 AJ14 T18 VCC_NCTF72 VCCAUX_NCTF53 W15
N21 VCC_85 VCC_SM_81 AJ13 VCCAUX_NCTF54 V15
M21 VCC_86 VCC_SM_82 AH13 VCCAUX_NCTF55 U15

la
L21 VCC_87 VCC_SM_83 AK12 VCCAUX_NCTF56 T15
AC20 VCC_88 VCC_SM_84 AJ12 VCCAUX_NCTF57 R15
AB20 VCC_89 VCC_SM_85 AH12
Y20 VCC_90 VCC_SM_86 AG12 CALISTOGA_1p0
W20 VCC_91 VCC_SM_87 AK11

.
P20 VCC_92 VCC_SM_88 BA8
N20 VCC_93 VCC_SM_89 AY8
M20 VCC_94 VCC_SM_90 AW8
L20 VCC_95 VCC_SM_91 AV8
AB19 VCC_96 VCC_SM_92 AT8
AA19 VCC_97 VCC_SM_93 AR8
Y19 VCC_98 AP8 +V1.8 7,21,22,34,46,47,56,58
VCC_SM_94

w
N19 VCC_99 VCC_SM_95 BA6
M19 VCC_100 VCC_SM_96 AY6
L19 VCC_101 VCC_SM_97 AW6
N18 VCC_102 VCC_SM_98 AV6
M18 VCC_103 VCC_SM_99 AT6
L18 VCC_104 AR6 C5R4 C5R3 C5D1
VCC_SM_100
P17 VCC_105 AP6

w
VCC_SM_101
N17 VCC_106 AN6 10uF 10uF 0.47uF
VCC_SM_102
M17 VCC_107 VCC_SM_103 AL6
N16 VCC_108 AK6 Place C5D1 near
A VCC_SM_104
PLACE IN CAVITY A
M16 VCC_109
L16 VCC_110
VCC_SM_105 AJ6
AV1 VCCSM_LF2
pin BA15 on Capell Valley Intel Confidential
VCC_SM_106 Layer1
VCC_SM_107 AJ1 VCCSM_LF1
C4D1 C4D2 Title

w
CALISTOGA_1p0
0.47uF 0.47uF CALISTOGA (4 OF 6)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 9 of 60
5 4 3 2 1
5 4 3 2 1
18,20,49,56,58 +V2.5S 4,17,27,48,56,58 +V1.5S
+V1.5S 4,17,27,48,56,58 NOTE: CAPS USED IN
NOTE: 0.1uF caps +V3.3_TVDAC should be

m
within 250mils of C5T14 C5T17
in 1.5SxPLL need C5T8 0.1uF
to be located as edge of MCH 3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S 0.1uF 10uF
U5E1H
edge caps within H22 VCCSYNC

o
47,56 +V3.3S_TVDAC +VCCA_TVDAC C4E5 +V3.3S_TVDACA 18,20,49,56,58 +V2.5S AC14
200mils FB4F1 VTT_0
22nF C30 VCC_TXLVDS0 VTT_1 AB14
+V1.5S_DPLLA 3 1 B30 W14
L5F1 C4F6 VCC_TXLVDS1 VTT_2
A30 VCC_TXLVDS2 VTT_3 V14
1 2 180ohm@100MHz 10uF C4F3 7,58 +V1.5S_PCIE T14

c
10uH 10% +80-20% VTT_4

2
0.1uF AJ41 VCC3G0 VTT_5 R14
C5U1
D C5U2
+V3.3S_TVDACB
AB41 VCC3G1 VTT_6 P14 D

.
470uF C4E4 Y41 N14
20% +V1.5S_3GPLL VCC3G2 VTT_7
0.1uF V41 M14
18,20,49,56,58 +V2.5S VCC3G3 VTT_8
22nF R41 VCC3G4 VTT_9 L14
3 1 N41 VCC3G5 VTT_10 AD13
C5R6 C5T1 L41 AC13
VCC3G6 VTT_11

s
+V1.5S_DPLLB C4F2 AC33 AB13
L6F1 0.1uF 10uF VCCA_3GPLL VTT_12

2
0.1uF G41 VCCA_3GBG VTT_13 AA13
1 2 H41 VSSA_3GBG VTT_14 Y13
10uH 10% C4E3 W13
C6F1 C5T13 +V3.3S_TVDACC 58 +V2.5S_CRTDAC VTT_15 18,20,49,56,58 +V2.5S
F21 V13

it c
22nF VCCA_CRTDAC0 VTT_16
470uF 3 1 1 3 VCCA_CRTDAC E21 U13
20% VCCA_CRTDAC1 VTT_17
0.1uF G21 VSSA_CRTDAC T13
C4F1 C5F2 C5F1 +V1.5S_DPLLA VTT_18
VTT_19 R13
22nF +V1.5S_DPLLB C5T15 C5F6

2
0.1uF B26 VCCA_DPLLA VTT_20 N13
0.1uF +V1.5S_HPLL C39 M13 4.7uF
+V1.5S_HPLL VCCA_DPLLB VTT_21 0.1uF
AF1 VCCA_HPLL VTT_22 L13
18,20,49,56,58 +V2.5S AB12
FB4D2 VTT_23
1 2 A38 VCCA_LVDS VTT_24 AA12
B39 VSSA_LVDS VTT_25 Y12
120ohm@100MHz C4T1 C4R5 C5T11 C5T12 +V1.5S_MPLL

a
VTT_26 W12
22uF AF2 V12
20% C5E6 0.01uF 0.1uF VCCA_MPLL VTT_27
0.1uF U12
+V3.3S_ATVBG VTT_28 18,20,49,56,58 +V2.5S
22nF H20 VCCA_TVBG VTT_29 T12
3 1 G20 VSSA_TVBG VTT_30 R12
+V1.5S_MPLL P12
VTT_31
VTT_32 N12
C5F5

2
VTT_33 M12
+V3.3S_TVDACA

m
FB4D1
1 2 E19 L12 C5E3
0.1uF +V3.3S_TVDACB VCCA_TVDACA0 VTT_34
F19 VCCA_TVDACA1 VTT_35 R11 0.1uF
120ohm@100MHz C4R3 C4R4
C20 VCCA_TVDACB0 VTT_36 P11
22uF D20 N11
+V3.3S_TVDACC VCCA_TVDACB1 VTT_37
C 20% 0.1uF E20 M11 C
VCCA_TVDACC0
POWER VTT_38

e
F20 VCCA_TVDACC1 VTT_39 R10
4,17,27,48,56,58 +V1.5S P10
VTT_40
AH1 VCCD_HMPLL0 VTT_41 N10
AH2 VCCD_HMPLL1 VTT_42 M10
3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S 4,17,27,48,56,58 +V1.5S P9
VTT_43
A28 N9 NOTE: .1uF CAPS USED IN

h
+V2.5S 18,20,49,56,58 VCCD_LVDS0 VTT_44
NOTE: CAPS USED IN B28 VCCD_LVDS1 VTT_45 M9
+V1.5S_DLVDS, +V2.5S_ALVDS,
C28 VCCD_LVDS2 VTT_46 R8
+V2.5_CRTDAC should 58 +V1.5S_TVDAC P8 +V2.5S_TXLVDS, +V2.5S_3GBG
R5U5 CR5F1 BAT54 VTT_47
be5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
within 250mils of +V3.3S
D21 VCCD_TVDAC VTT_48 N8
should be placed within
2 VCCGFOLLOW 3

c
1 1 VTT_49 M8
10 edge of MCH A23 P7 200mils of edge
58 +V2.5S_CRTDAC VCC_HV0 VTT_50
B23 VCC_HV1 VTT_51 N7
FB5E1 B25 M7
+V1.5S_QTVDAC VCC_HV2 VTT_52
VTT_53 R6

s
180ohm@100MHz H19 P6
+V1.5S_AUX 9,58 VCCD_QTVDAC VTT_54
VTT_55 M6
AK31 A6 VTTLF_CAP3
VCCAUX0 VTT_56

-
AF31 R5 C4T10
VCCAUX1 VTT_57
NOTE: CAPS AE31 VCCAUX2 VTT_58 P5
AC31 N5 0.47uF
USED IN VCCAUX3 VTT_59
AL30 VCCAUX4 VTT_60 M5
4,17,27,48,56,58 +V1.5S +V1.5_PCIE AK30 P4
VCCAUX5 VTT_61

p
7,58 +V1.5S_PCIE AJ30 N4
L5E1 should be on VCCAUX6 VTT_62
AH30 VCCAUX7 VTT_63 M4
PCIE_LR5E2 AG30 R3
0.002 1%
top layer VCCAUX8 VTT_64
AF30 VCCAUX9 VTT_65 P3
C5E2 C5D5 C5E1 91nH 20% AE30 N3
220uF VCCAUX10 VTT_66

o
AD30 VCCAUX11 VTT_67 M3
10uF 10uF AC30 R2
VCCAUX12 VTT_68
AG29 VCCAUX13 VTT_69 P2
B B

t
NOTE: 10uF CAPS AF29 VCCAUX14 VTT_70 M2
4,17,27,48,56,58 +V1.5S AE29 D2 VTTLF_CAP2
+V1.5S_3GPLL USED IN VCCAUX15 VTT_71 VTTLF_CAP1
AD29 VCCAUX16 VTT_72 AB1
L5D1 R6D8
+V1.5_3GPLL AC29 VCCAUX17 VTT_73 R1
R5D1 0.5 1% 3GPLL_R_L1 23GPLL_FB_L AG28 P1 C4T3 C4T9
should be placed VCCAUX18 VTT_74

p
1uH 20% 0.002 1% AF28 N1 NOTE: CAPS USED IN
VCCAUX19 VTT_75
in cavity AE28 M1 0.22uF
VCCAUX20 VTT_76 +V1.5_TVDAC and
AH22 0.47uF
VCCAUX21
AJ21 VCCAUX22 +V1.5_QTVDAC should be
AH21 VCCAUX23 within 250mils of edge

la
AJ20 VCCAUX24
3,4,6,9,14,17,30,37,45,48,53,56,58 +V1.05S AH20 VCCAUX25 4,17,27,48,56,58 +V1.5S
4,17,27,48,56,58 +V1.5S AH19 58 +V1.5S_TVDAC
VCCAUX26
+V1.5S_AUX 9,58 P19
R6D6 VCCAUX27 TVDAC_FB
C4T2 C4T4 C4E2 C4E1 P16 1 3 R5F3
VCCAUX28

.
AH15 C5F3 0.002 1%
0.22uF VCCAUX29
C5R5 0.002 1% 4.7uF 2.2uF 270uF P15 C5E4 0.1uF
VCCAUX30
20% 22nF

2
AH14 VCCAUX31
0.1uF PLACE IN AG14 VCCAUX32
5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S PLACE ON AF14
CAVITY AE14
VCCAUX33 +V1.5S_QTVDAC
THE EDGE Y14
VCCAUX34 FB5F1

w
+V3.3S 5,7,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 VCCAUX35 QTVDAC_FB
AF13 VCCAUX36 1 3
R4U3 AE13
10K VCCAUX37
AF12 C5E5 180ohm@100MHz
PM_SLP_S3_SHDN2

VCCAUX38
5,17,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S 22nF C5F4

2
AE12 VCCAUX39
AD12 0.1uF
VCCAUX40
U4F1 SC1563 +V3.3S_TVDAC_LDO
C5F7 C5T16 5

w
IN CALISTOGA_1p0
10uF 0.1uF OUT 4
C4F5 1
1.0uF SHDN
A GND ADJ R4U1 C4F7 C4F4 Capell Valley Intel Confidential A
+V3.3S_TVDAC_LDO 17.8K
2 3 1%
4,17,27,48,56,58 +V1.5S
22uF 0.1uF Title

w
CR4F1 TVDAC_ADJ2 CALISTOGA (5 OF 6)
3

V1_5SFOLLOW3 1 R4U4
1

BAT54 Q4U1 100


R4F3 BSS138 R4U2
47,56 +V3.3S_TVDAC 10
32,35,47,48,49,55,56 PM_SLP_S3# 1
NO_STUFF 10K Size Document Number Rev
1%
A D15378 1.501
2

R4F2 0.002 1%
Date: Wednesday, July 20, 2005 Sheet 10 of 60
5 4 3 2 1
5 4 3 2 1

U5E1I U5E1J

m
AC41 VSS_0 AK34 AT23 VSS_180 VSS_273 J11
VSS_97
AA41 VSS_1 AG34 AN23 VSS_181 VSS_274 D11
VSS_98
W41 VSS_2 VSS_99 AF34 AM23 VSS_182 VSS_275 B11
T41 VSS_3 VSS_100 AE34 AH23 VSS_183 VSS_276 AV10
P41 VSS_4 VSS_101 AC34 AC23 VSS_184 AP10
VSS_277

o
M41 VSS_5 VSS_102 C34 W23 VSS_185 AL10
VSS_278
J41 VSS_6 VSS_103 AW33 K23 VSS_186 AJ10
VSS_279
F41 VSS_7 VSS_104 AV33 J23 VSS_187 AG10
VSS_280
AV40 VSS_8 VSS_105 AR33 F23 VSS_188 AC10
VSS_281

c
AP40 VSS_9 VSS_106 AE33 C23 VSS_189 W10
VSS_282
AN40 VSS_10 AB33 AA22 VSS_190 U10
D AK40
VSS_107
Y33 K22
VSS_283
BA9 D

.
VSS_11 VSS_108 VSS_191 VSS_284
AJ40 VSS_12 VSS_109 V33 G22 VSS_192 VSS_285 AW9
AH40 VSS_13 T33 F22 VSS_193 AR9
VSS_110 VSS_286
AG40 VSS_14 R33 E22 VSS_194 AH9
VSS_111 VSS_287
AF40 VSS_15 M33 D22 VSS_195 AB9
VSS_112 VSS_288

s
AE40 VSS_16 H33 A22 VSS_196 Y9
VSS_113 VSS_289
B40 VSS_17 G33 BA21 VSS_197 R9
VSS_114 VSS_290
AY39 VSS_18 F33 AV21 VSS_198 G9
VSS_115 VSS_291
AW39 VSS_19 D33 AR21 VSS_199 E9
VSS_116 VSS_292

it c
AV39 VSS_20 B33 AN21 VSS_200 A9
VSS_117 VSS_293
AR39 VSS_21 AH32 AL21 VSS_201 AG8
VSS_118 VSS_294
AN39 VSS_22 AG32 AB21 VSS_202 AD8
VSS_119 VSS_295
AJ39 VSS_23 AF32 Y21 VSS_203 AA8
VSS_120 VSS_296
AC39 VSS_24 AE32 P21 VSS_204 U8
VSS_121 VSS_297
AB39 VSS_25 AC32 K21 VSS_205 K8
VSS_122 VSS_298
AA39 VSS_26 AB32 J21 VSS_206 C8
VSS_123 VSS_299
Y39 VSS_27 G32 H21 VSS_207 BA7
VSS_124 VSS_300
W39 VSS_28 B32 C21 VSS_208 AV7
VSS_125 VSS_301

a
V39 VSS_29 AY31 AW20 VSS_209 AP7
VSS_126 VSS_302
T39 AV31 AR20 AL7
R39
P39
VSS_30
VSS_31
VSS_32
VSS_127
VSS_128
VSS_129
AN31
AJ31
AM20
AA20
VSS_210
VSS_211
VSS_212
VSS VSS_303
VSS_304
VSS_305
AJ7
AH7
N39 AG31 K20 AF7
M39
L39
VSS_33
VSS_34
VSS_35
VSS VSS_130
VSS_131
VSS_132
AB31
Y31
B20
A20
VSS_213
VSS_214
VSS_215
VSS_306
VSS_307
VSS_308
AC7
R7
J39 AB30 AN19 G7

m
VSS_36 VSS_133 VSS_216 VSS_309
H39 VSS_37 E30 AC19 VSS_217 D7
VSS_134 VSS_310
G39 VSS_38 AT29 W19 VSS_218 AG6
VSS_135 VSS_311
F39 VSS_39 AN29 K19 VSS_219 AD6
C VSS_136 VSS_312 C
D39 VSS_40 AB29 G19 VSS_220 AB6
VSS_137 VSS_313

e
AT38 VSS_41 T29 C19 VSS_221 Y6
VSS_138 VSS_314
AM38 VSS_42 N29 AH18 VSS_222 U6
VSS_139 VSS_315
AH38 VSS_43 K29 P18 VSS_223 N6
VSS_140 VSS_316
AG38 VSS_44 G29 H18 VSS_224 K6
VSS_141 VSS_317
AF38 VSS_45 E29 D18 VSS_225 H6
VSS_142 VSS_318

h
AE38 VSS_46 C29 A18 VSS_226 B6
VSS_143 VSS_319
C38 VSS_47 B29 AY17 VSS_227 AV5
VSS_144 VSS_320
AK37 VSS_48 A29 AR17 VSS_228 AF5
VSS_145 VSS_321
AH37 VSS_49 BA28 AP17 VSS_229 AD5
VSS_146 VSS_322

c
AB37 VSS_50 AW28 AM17 VSS_230 AY4
VSS_147 VSS_323
AA37 VSS_51 AU28 AK17 VSS_231 AR4
VSS_148 VSS_324
Y37 VSS_52 AP28 AV16 VSS_232 AP4
VSS_149 VSS_325
W37 VSS_53 AM28 AN16 VSS_233 AL4
VSS_150 VSS_326
V37 AD28 AL16 AJ4

s
VSS_54 VSS_151 VSS_234 VSS_327
T37 VSS_55 AC28 J16 VSS_235 Y4
VSS_152 VSS_328
R37 VSS_56 W28 F16 VSS_236 U4
VSS_153 VSS_329
P37 J28 C16 R4

-
VSS_57 VSS_154 VSS_237 VSS_330
N37 VSS_58 E28 AN15 VSS_238 J4
VSS_155 VSS_331
M37 VSS_59 AP27 AM15 VSS_239 F4
VSS_156 VSS_332
L37 VSS_60 AM27 AK15 VSS_240 C4
VSS_157 VSS_333
J37 VSS_61 AK27 N15 VSS_241 AY3
VSS_158 VSS_334

p
H37 VSS_62 J27 M15 VSS_242 AW3
VSS_159 VSS_335
G37 VSS_63 G27 L15 VSS_243 AV3
VSS_160 VSS_336
F37 VSS_64 F27 B15 VSS_244 AL3
VSS_161 VSS_337
D37 VSS_65 C27 A15 VSS_245 AH3
VSS_162 VSS_338
AY36 VSS_66 B27 BA14 VSS_246 AG3
VSS_163 VSS_339

o
AW36 VSS_67 AN26 AT14 VSS_247 AF3
VSS_164 VSS_340
AN36 VSS_68 M26 AK14 VSS_248 AD3
VSS_165 VSS_341
B B

t
AH36 VSS_69 K26 AD14 VSS_249 AC3
VSS_166 VSS_342
AG36 VSS_70 F26 AA14 VSS_250 AA3
VSS_167 VSS_343
AF36 VSS_71 D26 U14 VSS_251 G3
VSS_168 VSS_344
AE36 VSS_72 AK25 K14 VSS_252 AT2
VSS_169 VSS_345
AC36 VSS_73 P25 H14 VSS_253 AR2
VSS_170 VSS_346

p
C36 VSS_74 K25 E14 VSS_254 AP2
VSS_171 VSS_347
B36 VSS_75 H25 AV13 VSS_255 AK2
VSS_172 VSS_348
BA35 VSS_76 E25 AR13 VSS_256 AJ2
VSS_173 VSS_349
AV35 VSS_77 D25 AN13 VSS_257 AD2
VSS_174 VSS_350
AR35 VSS_78 A25 AM13 VSS_258 AB2
VSS_175 VSS_351

la
AH35 VSS_79 BA24 AL13 VSS_259 Y2
VSS_176 VSS_352
AB35 VSS_80 AU24 AG13 VSS_260 U2
VSS_177 VSS_353
AA35 VSS_81 AL24 P13 VSS_261 T2
VSS_178 VSS_354
Y35 VSS_82 AW23 F13 VSS_262 N2
VSS_179 VSS_355

.
W35 VSS_83 D13 VSS_263 J2
VSS_356
V35 VSS_84 B13 VSS_264 H2
VSS_357
T35 VSS_85 AY12 VSS_265 F2
VSS_358
R35 VSS_86 AC12 VSS_266 C2
VSS_359
P35 VSS_87 K12 VSS_267 AL1
VSS_360
N35 H12 VSS_268
VSS_88

w
M35 E12 VSS_269
VSS_89
L35 AD11 VSS_270
VSS_90
J35 AA11 VSS_271
VSS_91
H35 Y11 VSS_272
VSS_92
G35
VSS_93
F35 CALISTOGA_1p0
VSS_94
D35

w
VSS_95
AN34
VSS_96
A A
CALISTOGA_1p0
Capell Valley Intel Confidential
Title

w
CALISTOGA (6 OF 6)

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 11 of 60
5 4 3 2 1
5 4 3 2 1

m
Layout Note:
Location of all MCH_CFG strap resistors
7 MCH_CFG_5

o
needs to be close to trace to minimize stub
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S

c
D MCH_CFG_5 Low = DMIx2 R1D3 D
2.2K

.
High = DMIx4
NO_STUFF MCH_CFG_18 R6F1
7 MCH_CFG_12 Low = 1.05V
(VCC 1K
Select) High = 1.5V NO_STUFF
7 MCH_CFG_13

s
R1E12
2.2K 7 MCH_CFG_18

it c
NO_STUFF
7 MCH_CFG_6 R1E11
NO_STUFF
2.2K

LOW = Moby Dick 5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58


MCH_CFG_6
HIGH = Calistoga R1D4 +V3.3S
(DDR) 2.2K

a
NO_STUFF
MCH_CFG_19 Low = Normal
(DMI LANE REVERSAL) High = LANES REVERSED
R5U3
1K
NO_STUFF

m
7 MCH_CFG_7 7 MCH_CFG_16 7 MCH_CFG_19
C C

e
Low = Dynamic ODT
MCH_CFG_7 Low = RSVD R1E3 MCH_CFG_16 Disabled R1E1
(CPU Strap) High = Mobile CPU 2.2K (FSB Dynamic 2.2K

h
High = Dynamic ODT
NO_STUFF ODT) NO_STUFF
Enabled
5,7,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S

c
MCH_CFG_20 Low = Only SDVO or PCIE x1 is
(PCIe Backward operational (defaults)
Interpoerability High = SDVO and PCIE x1 are operating
R5F1
mode) simultaneously via the PEG port

s
1K
NO_STUFF

-
7 MCH_CFG_9
7,13 MCH_CFG_20

p
MCH_CFG_9 Low = Reverse Lane
PCIE Graphics High = Normal R1E8
2.2K
Lane operation

o
B B

pt
7 MCH_CFG_10

la
MCH_CFG_10
HOST PLL VCO Low = RESERVED R1E2
High = MOBILITY 2.2K
SELECT

.
NO_STUFF

w
7 MCH_CFG_11

w
MHC_CFG_11 Low = Reserved
A R1D5 A
PSB 4x CLK
ENABLE
High = Calistoga
2.2K Capell Valley Intel Confidential
NO_STUFF
Title

w
CALISTOGA STRAPPING

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 12 of 60
5 4 3 2 1
5 4 3 2 1

o m
+V12S_PEG

+V12S_PEG +V3.3S_PEG

c
+V3.3S_PEG J6C1
D B1 +12V1 PRSNT1# A1 D

.
B2 +12V2 +12V4 A2
B3 +12V3 +12V5 A3
B4 GND1 GND6 A4
14,35 SMB_CLK_S4 B5 SMCLK JTAG2 A5
B6 A6 R6C4 0
14,35 SMB_DATA_S4 JTAG3 PLT_GATED_RST# 32,33,36

s
SMDAT NO_STUFF
B7 GND2 JTAG4 A7
14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A B8 A8
+3.3V1 JTAG5
B9 JTAG1 +3.3V2 A9
B10 3.3VAUX +3.3V3 A10
B11 A11 PEG_SLT_RST# R6C5 0

it c
16,28,33 PCIE_WAKE# WAKE# PWRGD PLT_RST# 7,15,24,28,32,41,42,57
Key
B12 RSVD2 GND7 A12
7 PEG_TXP[15:0] B13 GND3 REFCLK+ A13 CLK_PCIE_PEG 30
PEG_TXP15 C6C6 0.1uF PEG_C_TXP15 B14 A14
7 PEG_TXN[15:0] PEG_TXN15 PEG_C_TXN15 HSOP_0 REFCLK- CLK_PCIE_PEG# 30
C6C7 B15 A15
HSON_0 GND8 PEG_RXP15 PEG_RXP[15:0] 7
0.1uF B16 A16
GND4 HSIP_0 PEG_RXN15 PEG_RXN[15:0] 7
7 SDVO_CTRLCLK B17 PRSNT2# HSIN_0 A17
B18 GND5 GND9 A18
PEG_TXP14 C6C8 0.1uF PEG_C_TXP14

a
B19 HSOP_1 RSVD5 A19
PEG_TXN14 PEG_C_TXN14 B20 A20
C6C9 0.1uF HSON_1 GND16 PEG_RXP14
B21 GND10 HSIP_1 A21
B22 A22 PEG_RXN14
PEG_TXP13 C6C10 0.1uF PEG_C_TXP13 GND11 HSIN_1
B23 HSOP_2 GND17 A23
PEG_TXN13 PEG_C_TXN13 B24 A24
C6C11 0.1uF HSON_2 GND18 PEG_RXP13
B25 GND12 HSIP_2 A25
B26 A26 PEG_RXN13
PEG_TXP12 PEG_C_TXP12 GND13 HSIN_2

m
C6C12 0.1uF B27 A27
PEG_TXN12 PEG_C_TXN12 HSOP_3 GND19
B28 HSON_3 GND20 A28
C6C13 0.1uF B29 A29 PEG_RXP12
GND14 HSIP_3 PEG_RXN12
B30 RSVD3 HSIN_3 A30
C 7 SDVO_CTRLDATA B31 PRSNT2#1 GND21 A31 C

e
B32 GND15 RSVD6 A32
PEG_TXP11 C6D3 0.1uF PEG_C_TXP11 B33 A33
PEG_TXN11 PEG_C_TXN11 HSOP_4 RSVD7
B34 HSON_4 GND30 A34
C6D4 0.1uF B35 A35 PEG_RXP11
GND22 HSIP_4 PEG_RXN11
B36 GND23 HSIN_4 A36
PEG_TXP10 C6D6 0.1uF PEG_C_TXP10 B37 A37 55,56 +VBAT_S4

h
PEG_TXN10 PEG_C_TXN10 HSOP_5 GND31
B38 HSON_5 GND32 A38
C6D7 0.1uF B39 A39 PEG_RXP10 18,19,27,55,56 +VBATS
GND24 HSIP_5 PEG_RXN10
B40 GND25 HSIN_5 A40
PEG_TXP9 C6D8 0.1uF PEG_C_TXP9 B41 A41
PEG_TXN9 PEG_C_TXN9 HSOP_6 GND33

c
B42 HSON_6 GND34 A42
C6D9 0.1uF B43 A43 PEG_RXP9 R6N6 R6N7
GND26 HSIP_6 PEG_RXN9 0.002 0.002
B44 GND27 HSIN_6 A44
PEG_TXP8 C6D10 0.1uF PEG_C_TXP8 B45 A45 +V12S_PEG 1% 1%
PEG_TXN8 PEG_C_TXN8 HSOP_7 GND35 NO_STUFF
B46 HSON_7 GND36 A46

-s
C6D11 0.1uF B47 A47 PEG_RXP8
GND28 HSIP_7 PEG_RXN8
7,12 MCH_CFG_20 B48 PRSNT2#2 HSIN_7 A48
B49 GND29 GND37 A49
PEG_TXP7 C6D13 0.1uF PEG_C_TXP7 B50 A50 C6B11 C6B7 C6B4 C6B6 C6B8 C6N8
PEG_TXN7 PEG_C_TXN7 HSOP_8 RSVD8 22UF 22UF 22UF 22UF 0.1uF 0.1uF
B51 HSON_8 GND54 A51
C6D14 0.1uF B52 A52 PEG_RXP7 10% 10%
GND38 HSIP_8 PEG_RXN7
B53 GND39 HSIN_8 A53
PEG_TXP6 C6D16 0.1uF PEG_C_TXP6 B54 A54
PEG_TXN6 PEG_C_TXN6 HSOP_9 GND55

p
B55 HSON_9 GND56 A55
C6D17 0.1uF B56 A56 PEG_RXP6
GND40 HSIP_9 PEG_RXN6
B57 GND41 HSIN_9 A57
PEG_TXP5 C6E1 0.1uF PEG_C_TXP5 B58 A58
PEG_TXN5 PEG_C_TXN5 HSOP_10 GND57 14,15,17,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3
B59 HSON_10 GND58 A59
C6E2 0.1uF PEG_RXP5 5,7,10,12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S

o
B60 GND42 HSIP_10 A60
B61 A61 PEG_RXN5
PEG_TXP4 C6E3 0.1uF PEG_C_TXP4 GND43 HSIN_10
B62 HSOP_11 GND59 A62
B B

t
PEG_TXN4 PEG_C_TXN4 B63 A63 For D3 HOT/ D3 ON: R6C2 R6C3
C6E4 0.1uF HSON_11 GND60 PEG_RXP4 0.002 0.002
B64 GND44 HSIP_11 A64
B65 A65 PEG_RXN4 Stuff R6N7, R6C3, and +V3.3S_PEG 1% 1%
PEG_TXP3 C6E5 0.1uF PEG_C_TXP3 GND45 HSIN_11 NO_STUFF
PEG_TXN3 PEG_C_TXN3
B66 HSOP_12 GND61 A66 R6C4, unstuff R6N6,
B67 HSON_12 GND62 A67
PEG_RXP3 R6C2 and R6C5.

p
C6E6 0.1uF B68 A68
GND46 HSIP_12 PEG_RXN3 + C6C5 C6C4 C6C3
B69 GND47 HSIN_12 A69
PEG_TXP2 C6E7 0.1uF PEG_C_TXP2 B70 A70 100uF 0.1uF 0.1uF
PEG_TXN2 PEG_C_TXN2 HSOP_13 GND63
B71 HSON_13 GND64 A71
C6E8 0.1uF B72 A72 PEG_RXP2
GND48 HSIP_13 PEG_RXN2

la
B73 GND49 HSIN_13 A73
PEG_TXP1 C6E10 0.1uF PEG_C_TXP1 B74 A74
PEG_TXN1 PEG_C_TXN1 HSOP_14 GND65
B75 HSON_14 GND66 A75
C6E11 0.1uF B76 A76 PEG_RXP1
GND50 HSIP_14 PEG_RXN1
B77 GND51 HSIN_14 A77

.
PEG_TXP0 C6E12 0.1uF PEG_C_TXP0 B78 A78 14,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
PEG_TXN0 PEG_C_TXN0 HSOP_15 GND67
B79 HSON_15 GND68 A79
C6E13 0.1uF B80 A80 PEG_RXP0
GND52 HSIP_15 PEG_RXN0
B81 PRSNT2#3 HSIN_15 A81
B82 A82 C6C2 C6C1
RSVD4 GND69 0.1uF
PCIE_X16 22uF

w
Layout Note: place
AC coupling caps
close to GMCH. All
AC coupling caps are

w
0603 size.
A A
Capell Valley Intel Confidential
Title

w
PCIE GRAPHICS

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 13 of 60
5 4 3 2 1
5 4 3 2 1

+V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
CR6H1 17 +V3.3A_RTC

m
1 3
C6H7

BAT54 1uF
RTC Circuitry

o
CR6H2 R6H11 20K
BAT_D 1 3

C6H5 J6H1

c
BAT54 1uF
R6H9
D 1K R6H10 D

.
1M C8V1 10pF

1
BAT Y8G1 R8V5
32.768KHZ 10M

s
1

Cap values depend on Xtal

4
U7G1A
LPC_AD0 LPC_AD[3:0] 24,32,35,41,42
BT5H1 CMOS Settings J6H1 RTC_X1 AB1 AA6
Battery_Holder C8V2 10pF RTC_X2 RTXC1 LAD0 LPC_AD1 +V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58
AB2 AB5

it c
Clear CMOS Shunt RTCX2 LAD1

LPC
LPC_AD2

RTC
LAD2 AC4
Keep CMOS Open RTC_RST# AA3 Y6 LPC_AD3
RTCRST# LAD3
SM_INTRUDER# R6V11 R5V9
3

Y5 INTRUDER# LDRQ0# AC3 ICH_DRQ#0 42


13,15,17,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3 ICH_INTVRMEN W4 AA5 56 56
U8F3 INTVRMEN LDRQ1#/GPIO23 ICH_DRQ#1 42
8 1 EEP_CS W1 AB3
TP_EEP_DC VCC CS EE_CS LFRAME# LPC_FRAME# 24,32,35,41,42
C8U1 7 2 EEP_SK Y1 NO_STUFF NO_STUFF 3,4,6,9,10,17,30,37,45,48,53,56,58
TP_EEP_ORG DC SK EEP_DOUT EE_SHCLK +V1.05S
6 ORG DI 3 Y2 EE_DOUT A20GATE AE22 H_A20GATE 32,35
0.1uF EEP_DIN

a
5 GND DO 4 W3 EE_DIN A20M# AH28 H_A20M# 3
V3 AG27 TP_H_CPUSLP#
33 LAN_JCLK LAN_CLK CPUSLP#
AT88SC153 R5G5 0 R6V17
H_DPRSTP# 3,35

LAN
CPU
NO_STUFF U3 AF24 H_DPRSTP#_R 56
33 LAN_RSTSYNC LAN_RSTSYNC TP1/DPRSTP# H_DPSLP#_R
AH25 R6V13 0
TP2/DPSLP# H_DPSLP# 3,35
33 LAN_RXD0 U5 LAN_RXD0
33 LAN_RXD1 V4 LAN_RXD1 FERR# AG26 H_FERR# 3

m
33 LAN_RXD2 T5 LAN_RXD2
GPIO49/CPUPWRGD AG24 H_PWRGD 3,35
33 LAN_TXD0 U7 LAN_TXD0
33 LAN_TXD1 V6 LAN_TXD1
C 33 LAN_TXD2 V7 LAN_TXD2 IGNNE# AG22 H_IGNNE# 3 C

e
INIT3_3V# AG21 FWH_INIT# 24
27 ACZ_BITCLK U1 ACZ_BIT_CLK INIT# AF22 H_INIT# 3

AC-97/AZALIA
+V3.3S R6 AF25
27 ACZ_SYNC ACZ_SYNC INTR H_INTR 3
5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S R5 AG23 +V1.05S 3,4,6,9,10,17,30,37,45,48,53,56,58
27 ACZ_RST# ACZ_RST# RCIN# H_RCIN# 16,32,35
5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

h
27 ACZ_SDATAIN0 T2 ACZ_SDIN0 NMI AH24 H_NMI 3,35
R7H11 T3 AF23 H_SMI#_R R6V16 R6V14
27 ACZ_SDATAIN1 ACZ_SDIN1 SMI# H_SMI# 3,35,58 56
10K T1 0
27 ACZ_SDATAIN2 ACZ_SDIN2
STPCLK# AH22 H_STPCLK# 3
ACZ_SDATAOUT

c
27 ACZ_SDATAOUT T4 ACZ_SDOUT
AF26 H_THERMTRIP_R R6V12 24.9 1%
ICH_SATA_LED# THERMTRIP# PM_THRMTRIP# 3,7
AF18 SATALED#
IDE_PDD[15:0] 39 Layout note: R6V12 needs to placed
R7J5 C7W2 3900pF SATA_RXN0_C AF3 AB15 IDE_PDD0
43 SATA_RXN0 SATA0RXN DD0 within 2" of ICH7, R6V14 must be placed

-s
330 C7W1 3900pF SATA_RXP0_C AE3 AE14 IDE_PDD1
43 SATA_RXP0 SATA0RXP DD1
C7W3 3900pF SATA_TXN0_C AG2 AG13 IDE_PDD2 within 2" of R6V12 w/o stub.
43 SATA_TXN0 C7W4 SATA_TXP0_C SATA0TXN DD2 IDE_PDD3
AH2 SATA0TXP DD3 AF13
LED_R C7J12 43 SATA_TXP0 3900pF IDE_PDD4
DD4 AD14
C7H5 3900pF SATA_RXN2_C AF7 AC13 IDE_PDD5
44 SATA_RXN2 SATA2RXN DD5
2

0.1uF R7J3 C7H6 3900pF SATA_RXP2_C AE7 AD12 IDE_PDD6


10K 44 SATA_RXP2 SATA_TXN2_C SATA2RXP DD6 IDE_PDD7
CR7J1 C7H4 3900pF AG6 AC12
44 SATA_TXN2 SATA_TXP2_C SATA2TXN DD7 IDE_PDD8
C7H3 3900pF AH6 AE12
GREEN 44 SATA_TXP2 SATA2TXP DD8
5

IDE_PDD9

p
U7J1 AF12
DD9

SATA
1 AF1 AB13 IDE_PDD10
31 CLK_PCIE_SATA# SATA_CLKN DD10 IDE_PDD11
74AHC1G08 Distance between the ICH-7 M
1

54 ATA_LED# 4 31 CLK_PCIE_SATA AE1 SATA_CLKP DD11 AC14


2 AF14 IDE_PDD12
IDE_PDACTIVE# 39 and cap on the "P" signal should SATA_RBIAS_PN DD12 IDE_PDD13
AH10 SATARBIASN DD13 AH13
be identical distance between IDE_PDD14

o
AG10 SATARBIASP DD14 AH14
IDE_PDD15
3

the ICH-7 M and cap on the "N" DD15 AC15


B signal for same pair. IDE_PDA[2:0] 39 B

t
AF15 AH17 IDE_PDA0
39 IDE_PDIOR#
AH15
DIOR# IDE DA0
AE17 IDE_PDA1
39 IDE_PDIOW# DIOW# DA1 IDE_PDA2
39 IDE_PDDACK# AF16 DDACK# DA2 AF17
39 INT_IRQ14 AH16 IDEIRQ
R7H1 AG16 AE16
39 IDE_PDIORDY IORDY DCS1# IDE_PDCS1# 39

p
Short pins AH10 and 24.9 AE15 AD16
39 IDE_PDDREQ DDREQ DCS3# IDE_PDCS3# 39
17 +V3.3A_RTC 1%
AG10 at the package. ICH7M REV 1.02 EDS
Place R7H1 within 500
R7V1 mils of ICH7 ball

la
332K
1%
ICH7 internal VR enable strap
ICH_INTVRMEN
INTVRMEN R7V1 R7V2

.
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R7V2 Enable (default) 1 STUFF UNSTUFF
0 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
NO_STUFF Disable 0 UNSTUFF STUFF
R7C23 10K SMB_CLK_S2 R9D1 10K SMB_CLK_A1
R7D2 10K SMB_DATA_S2

w
R6D5 10K SMB_CLK_S3 R9D2 10K SMB_DATA_A1
R6D7 10K SMB_DATA_S3
R9A5 10K SMB_CLK_S4
R9A6 10K SMB_DATA_S4
+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A

+V3.3S 5,7,10,12,13,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

w
R8G8 +V3.3A 13,16,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 C7C6
1K U7C4
A NO_STUFF R7P23 10K CL1 0.1uF A
R7P28 10K CL2
1 EXPSCL1
2 EXPSCL2
VCC 20 Capell Valley Intel Confidential
R7R2 10K DA1 18 EXPSDA1 SCL1 5 SMB_CLK_A1 25,26,28
ACZ_SDATAOUT R7P24 10K DA2 Title

w
19 EXPSDA2 SDA1 6 SMB_DATA_A1 25,26,28

RSVD9 15 16,33,58 SMB_CLK 3 SCL0 SCL2 8 SMB_CLK_S2 21,22,23


ICH7-M (1 of 4)
16,33,58 SMB_DATA 4 SDA0 SDA2 9 SMB_DATA_S2 21,22,23
R7U13 R7R6 10K I2C_EN1 7 12
1K R7D11 10K I2C_EN2 11 EN1 SCL3
13
SMB_CLK_S3 30,31
SMB_DATA_S3 30,31
Size Document Number Rev
NO_STUFF R7D1 10K I2C_EN3 14 EN2 SDA3
R7R5 10K I2C_EN4 17 EN3
15
A D15378 1.501
EN4 SCL4 SMB_CLK_S4 13,35
10 VSS SDA4 16 SMB_DATA_S4 13,35
EXP. 5-CH-I2C HUB Date: Wednesday, July 20, 2005 Sheet 14 of 60
5 4 3 2 1
5 4 3 2 1

+V3.3S 5,7,10,12,13,14,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

m
C7T4
Layout note: PCIE AC coupling caps
0.1uF U8E2 need to be within 250 mils of the

5
o
1 PLT_RST# driver.
32,33,35 BUF_PLT_RST# 4 74AHC1G08
2 U7G1D
F26 V26

c
33 PCIE_RXN1_LAN PERn1 DMI0RXN DMI_RXN0 7

Direct Media Interface


R8B3 Buffer to reduce F25 V25
33 PCIE_RXP1_LAN PERp1 DMI0RXP DMI_RXP0 7
D 100K C6V1 0.1uF PCIE_TXN1_C D

3
loading on E28 PETn1 DMI0TXN U28 DMI_TXN0 7
33 PCIE_TXN1_LAN

.
PLT_RST# C6U2 0.1uF PCIE_TXP1_C E27 U27
33 PCIE_TXP1_LAN PETp1 DMI0TXP DMI_TXP0 7

28 PCIE_RXN2_SLOT1 H26 PERn2 DMI1RXN Y26


DMI_RXN1 7
28 PCIE_RXP2_SLOT1 H25 PERp2 DMI1RXP Y25 DMI_RXP1 7
C6F7 0.1uF PCIE_TXN2_C G28 W28
DMI1TXN DMI_TXN1 7

s
28 PCIE_TXN2_SLOT1 C6F6 0.1uF PCIE_TXP2_C PETn2
G27 PETp2 DMI1TXP W27 DMI_TXP1 7
28 PCIE_TXP2_SLOT1

PCI-Express
R6V5 0 PCIE_RXN3_R K26 AB26
28 PCIE_RXN3_SLOT2 PCIE_RXP3_R PERn3 DMI2RXN DMI_RXN2 7
R6V4 0 K25 AB25
28 PCIE_RXP3_SLOT2 PERp3 DMI2RXP DMI_RXP2 7
C6V3 0.1uF PCIE_TXN3_C J28 AA28

it c
28 PCIE_TXN3_SLOT2 PETn3 DMI2TXN DMI_TXN2 7
C6V2 0.1uF PCIE_TXP3_C J27 AA27
28 PCIE_TXP3_SLOT2 PETp3 DMI2TXP DMI_TXP2 7
R6V8 0 PCIE_RXN4_R M26 AD25
28 PCIE_RXN4_SLOT0 PCIE_RXP4_R PERn4 DMI3RXN DMI_RXN3 7 +V1.5S_PCIE_ICH 17
R6V6 0 M25 AD24
28 PCIE_RXP4_SLOT0 PCIE_TXN4_C PERp4 DMI3RXP DMI_RXP3 7
+V3.3 13,14,17,25,27,32,33,34,35,36,38,45,46,55,56 C6G5 0.1uF L28 AC28
28 PCIE_TXN4_SLOT0 PCIE_TXP4_C PETn4 DMI3TXN DMI_TXN3 7
C6G3 0.1uF L27 AC27
28 PCIE_TXP4_SLOT0 PETp4 DMI3TXP DMI_TXP3 7
NOTE: R7F3-5 are not needed
PCIE_RXN4_SLOT0 R6G5 0 NO_STUFF PCIE_RXN5_R P26 AE28
when sharing SPI flash with PCIE_RXP4_SLOT0 R6G4 0 NO_STUFF PCIE_RXP5_R PERn5 DMI_CLKN CLK_PCIE_ICH# 30 R7U9
P25 PERp5 DMI_CLKP AE27 CLK_PCIE_ICH 30
ICH7M and Tekoa PCIE_TXN4_SLOT0 C6G1 0.1uF NO_STUFF PCIE_TXN5_C 24.9 Place within 500

a
N28 PETn5
R7F5 R7F4 R7F3 PCIE_TXP4_SLOT0 C6F5 0.1uF NO_STUFF PCIE_TXP5_C N27 C25 1% mils of ICH
10K 10K 10K PETp5 DMI_ZCOMP DMI_IRCOMP_R
DMI_IRCOMP D25
NO_STUFF NO_STUFF NO_STUFF PCIE_RXN3_SLOT2 R6G3 0 NO_STUFF PCIE_RXN6_R T25
PCIE_RXP3_SLOT2 R6G2 0 NO_STUFF PCIE_RXP6_R PERn6
T24 PERp6 USBP0N F1 USB_PN0 40
PCIE_TXN3_SLOT2 C6G7 0.1uF NO_STUFF PCIE_TXN6_C R28 F2
PCIE_TXP3_SLOT2 PCIE_TXP6_C PETn6 USBP0P USB_PP0 40
C6G6 0.1uF NO_STUFF R27 G4
PETp6 USBP1N USB_PN1 40
USBP1P G3 USB_PP1 40

m
33 SPI_SCLK R2 SPI_CLK USBP2N H1 USB_PN2 29
33 SPI_CE# P6 SPI_CS# USBP2P H2 USB_PP2 29

SPI
33 SPI_ARB P1 SPI_ARB USBP3N J4 USB_PN3 40
USBP3P J3 USB_PP3 40
C 33 SPI_SI P5 SPI_MOSI USBP4N K1 USB_PN4 29 C

USB
e
33 SPI_SO P2 SPI_MISO USBP4P K2 USB_PP4 29
USBP5N L4 USB_PN5 40
R7F15 0 D3 L5
40 USB_OC#0 OC0# USBP5P USB_PP5 40
R7F14 0 C4 M1
40 USB_OC#1 OC1# USBP6N USB_PN6 29
R7F13 0 D5 M2
29 USB_OC#2 OC2# USBP6P USB_PP6 29
R7F12 0 D4 N4

h
40 USB_OC#3 OC3# USBP7N USB_PN7 40
R7F8 0 E5 N3
29 USB_OC#4 OC4# USBP7P USB_PP7 40
R7F9 0 C3
40 USB_OC#5 OC5#/GPIO29
R7F11 0 A2 D2
29 USB_OC#6 OC6#/GPIO30 USBRBIAS#
R7F10 0 B3 D1 USB_RBIAS_PN
40 USB_OC#7 OC7#/GPIO31 USBRBIAS

c
ICH7M REV 1.02 EDS
USB_OC#0_R
R8U5
USB_OC#1_R Place within 500 22.6
USB_OC#2_R
mils of ICH 1%
USB_OC#3_R

-s
USB_OC#4_R
USB_OC#5_R
USB_OC#6_R
USB_OC#7_R

p
PCI_GNT#3 25

o
U7G1B
25,26 PCI_AD[31:0]
PCI_AD0 E18 D7 R8U4 R7U18 - A16 swap override
B AD0 REQ0# PCI_REQ#0 16,26 B

t
PCI_AD1 C18 E7 1K
PCI_AD2 A16
AD1 PCI GNT0#
C16
PCI_GNT#0 26 NO_STUFF by default
AD2 REQ1# PCI_REQ#1 16,26 STUFF for A16 swap override
PCI_AD3 F18 D16 NO_STUFF
AD3 GNT1# PCI_GNT#1 26
PCI_AD4 E16 C17
AD4 REQ2# PCI_REQ#2 16,25
PCI_AD5 A18 D17
AD5 GNT2# PCI_GNT#2 25

p
PCI_AD6 E17 E13
AD6 REQ3# PCI_REQ#3 16,25
PCI_AD7 A17 F13
PCI_AD8 AD7 GNT3#
A15 AD8 REQ4#/GPIO22 A13 FWH_WP# 24,35
PCI_AD9 C14 A14
AD9 GNT4#/GPIO48 FWH_TBL# 24,35
PCI_AD10 E14 C8 R8U3 0
AD10 GPIO1/REQ5# PCI_GNT#5_R PCI_REQ#5 16,26 PCI_GNT#5 26
PCI_AD11

la
D14 AD11 GPIO17/GNT5# D8 PCI_GNT#5_R
PCI_AD12 B12 AD12 GNT5_SPI 29
PCI_AD13 C13 B15
AD13 C/BE0# PCI_C/BE#0 25,26
PCI_AD14 G15 C12 R7F7 R8U2
AD14 C/BE1# PCI_C/BE#1 25,26
PCI_AD15 G13 D12 1K 1K
AD15 C/BE2# PCI_C/BE#2 25,26

.
PCI_AD16 E12 C15
AD16 C/BE3# PCI_C/BE#3 25,26
PCI_AD17 C11 NO_STUFF ICH7 Boot BIOS select
PCI_AD18 AD17
D11 AD18 IRDY# A7 PCI_IRDY# 16,25,26
PCI_AD19 A11 E10
AD19 PAR PCI_PAR 25,26
PCI_AD20 A10 B18 GNT5# GNT4#
AD20 PCIRST# PCI_RST# 25,26,32 STRAP
PCI_AD21 F11 A12 R8U2 R7F7
AD21 DEVSEL# PCI_DEVSEL# 16,25,26
PCI_AD22 F10 C9 PCI_PERR# 16,25,26

w
PCI_AD23 AD22 PERR#
E9 E11 PCI_LOCK# 16,25,26 LPC (default) 11
PCI_AD24 D9
AD23 PLOCK#
B10
UNSTUFF UNSTUFF
AD24 SERR# PCI_SERR# 16,25,26
PCI_AD25 B9 F15
PCI_AD26 AD25 STOP# PCI_STOP# 16,25,26 PCI 10 UNSTUFF STUFF
A8 AD26 TRDY# F14 PCI_TRDY# 16,25,26
PCI_AD27 A6 F16
PCI_AD28 AD27 FRAME# PCI_FRAME# 16,25,26 SPI 01 STUFF UNSTUFF
C7 AD28
PCI_AD29 B6 C26

w
AD29 PLTRST# PLT_RST# 7,13,24,28,32,41,42,57
PCI_AD30 E6 A9
AD30 PCICLK CLK_PCIF_ICH 31
PCI_AD31 D6 B19
AD31 PME# PCI_PME# 25,26,35
A Intel Confidential A
16,25 INT_PIRQA# A3
Interrupt I/F G8 INT_PIRQE# 16,26
Capell Valley
PIRQA# GPIO2/PIRQE#
B4 F7
16,25,26 INT_PIRQB# PIRQB# GPIO3/PIRQF# INT_PIRQF# 16,25,26 Title

w
16,25 INT_PIRQC# C5 PIRQC# GPIO4/PIRQG# F8 INT_PIRQG# 16,25,26
16,25 INT_PIRQD# B5 PIRQD# GPIO5/PIRQH# G7 INT_PIRQH# 16,26 ICH7-M (2 of 4)
TP_ICH_RSVD1 AE5
MISC AE9 TP_ICH_RSVD6
RSVD[1] RSVD[6]
TP_ICH_RSVD2
TP_ICH_RSVD3
AD5 RSVD[2] RSVD[7] AG8 TP_ICH_RSVD7
TP_ICH_RSVD8
Size Document Number Rev
AG4 RSVD[3] RSVD[8] AH8
TP_ICH_RSVD4
TP_ICH_RSVD5
AH4 RSVD[4] RSVD[9] F21 RSVD9 14 A D15378 1.501
AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# 7
ICH7M REV 1.02 EDS
Date: Wednesday, July 20, 2005 Sheet 15 of 60
5 4 3 2 1
5 4 3 2 1

ICH7 Pullups RP9C1B 2 7 8.2K

m
5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
RP9D1A 1 8 8.2K
15,25,26 PCI_FRAME#
RP9D1B 2 7 8.2K
R7F16 - No Reboot Strap 15,25,26 PCI_IRDY#
RP9D1C 3 6 8.2K

o
SATA0_R1 15,25,26 PCI_TRDY#
NO_STUFF by default +V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 RP9D2A 1 8 8.2K
SATA0_R2 15,25,26 PCI_STOP#
STUFF for No Reboot RP9D2D 4 5 8.2K
15,25,26 PCI_SERR#
RP9D1D 4 5 8.2K
14,33,58 SMB_CLK 15,25,26 PCI_DEVSEL#
U7G1C RP9D2C 3 6 8.2K
14,33,58 SMB_DATA SATA0_R0 15,25,26 PCI_PERR#
R7W2 100 RP9D2B 2 8.2K

c
C22 SMBCLK GPIO21/SATA0GP AF19 15,25,26 PCI_LOCK# 7

SMB
D B22 AH18 R7W5 100 RP9B1A 1 8 8.2K D
SMBDATA GPIO19/SATA1GP 15,26 PCI_REQ#0

SATA
GPIO
R7F16 SMB_LINK_ALERT# A26 AH19 R7W3 100 RP9B3B 2 7 8.2K
LINKALERT# GPIO36/SATA2GP SATA_DET#2 32,44 15,26 PCI_REQ#1

.
1K SMLINK0 B25 AE19 SATA0_R3 R7W6 100 RP9C1D 4 5 8.2K
SMLINK1 SMLINK0 GPIO37/SATA3GP 15,25 PCI_REQ#2
NO_STUFF A25 RP9C1C 3 6 8.2K
SMLINK1 15,25 PCI_REQ#3
AC1 RP9C1A 1 8 8.2K
CLK14 CLK_REF_ICH 31 15,26 PCI_REQ#5

Clocks
A28 B2 RP9B3A 1 8 8.2K
35,42 PM_RI# RI# CLK48 CLK_USB48 30 15,25 INT_PIRQA#
RP9B1D 4 5 8.2K

s
15,25,26 INT_PIRQB#
A19 C20 RP9B2A 1 8 8.2K
27 ACZ_SPKR SPKR SUSCLK SUS_CLK 35,41 15,25 INT_PIRQC#
A27 RP9B1C 3 6 8.2K
32,35,42,57 PM_SUS_STAT# SUS_STAT# SLP_S3#_R 15,25 INT_PIRQD#
A22 B24 R8G7 100 RP9B2B 2 7 8.2K
54 PM_SYSRST# SYS_RST# SLP_S3# SLP_S4#_R PM_SLP_S3#_UNBUF 47 15,26 INT_PIRQE#
R6W3 R6W4 D23 R8G2 100 RP9B2C 3 6 8.2K
SLP_S4# PM_SLP_S4# 26,32,35,46,55,56 15,25,26 INT_PIRQF#
10K 10K RP9B2D 4 8.2K

it c
7 PM_BMBUSY# AB18 GPIO0/BM_BUSY# SLP_S5# F22 PM_SLP_S5# 55 15,25,26 INT_PIRQG# 5
RP9B1B 2 7 8.2K
PM_ICH_PWROK 15,26 INT_PIRQH#
NO_STUFF NO_STUFF B23 AA4 RP9B3D 4 5 8.2K
33 SMB_ALERT# GPIO11/SMBALERT# PWROK 25 PCI_REQ64#

Power MGT
RP9B3C 3 6 8.2K
R7W8 0 PM_STPPCI_ICH# PM_DPRSLPVR_R R7H9 100 25 PCI_ACK64#
30,35 PM_STPPCI# AC20 GPIO18/STPPCI# GPIO16/DPRSLPVR AC22 PM_DPRSLPVR 7,35,51

GPIO
R7W7 0 PM_STPCPU_ICH# AF21 R9W12 8.2K
30,35 PM_STPCPU# GPIO20/STPCPU# 25,26,32,35,42 PM_CLKRUN#

SYS
C21 PM_BATLOW#_R R8F9 0
TP0/BATLOW# PM_BATLOW# 32,35
29 PCIE_SLOT0_CARD_ID#1 A21 GPIO26
C23 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
PWRBTN# PM_PWRBTN# 32,35
BIOS_REC_R B21 GPIO27

a
E23 R7T6 10K
FWH_MFG_MODE_R GPIO28 35,42 PM_RI#
LAN_RST# C19 PM_LAN_ENABLE 32,34,35
25,26,32,35,42 PM_CLKRUN# AG18 GPIO32/CLKRUN#
R7H13 0 Y4 PM_RSMRST#_R R8G14 100 SMB_LINK_ALERT# R6U2 10K
27 DOCK_AZ_EN# RSMRST# PM_RSMRST# 32,35
AC19 SMLINK0 R6U3 10K
DOCK_AZ_EN#_R GPIO33/AZ_DOCK_EN#
U2 E20 SMLINK1 R6U1 10K
27 DOCK_AZ_RST# GPIO34/AZ_DOCK_RST# GPIO9 IDE_PATADET 35,39
GPIO10 A20 PCIE_SLOT0_CARD_ID#0 29
F20 F19 PATA_PWR_EN#_R
13,28,33 PCIE_WAKE# WAKE# GPIO12

m
AH21 E19 SMC_WAKE_SCI#_R 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S
25,32,35,42 INT_SERIRQ SERIRQ GPIO13
5,32,35 PM_THRM# AF20 THRM# GPIO14 R4 PCIE_SLOT1_CARD_ID#1 29
GPIO15 E22 SV_SET_UP
C AD22 R3 R7P22 10K C
31 VR_PWRGD_CK410 VRMPWRGD GPIO24 CRB_SV_DET_R 31 CLK_PCIE_SATA_OE#
R7H12 0 D20
43 SATA_PWR_EN#0 GPIO25

e
AC21 AD21 R9W4 8.2K
SATA_PWR_EN#0_R SMC_RUNTIME_SCI#_R AC18 GPIO6 GPIO35 CLK_PCIE_SATA_OE# 31 5,32,35 PM_THRM#
GPIO7 GPIO GPIO38 AD20 PCIE_SLOT1_CARD_ID#0 29
SMC_EXTSMI#_R E21 AE20 R7V3 10K
GPIO8 GPIO39 SATA_PWR_EN#2 44 14,32,35 H_RCIN#
ICH7M REV 1.02 EDS R7T8 10K
25,32,35,42 INT_SERIRQ

h
R8G11 10K
32,35,48 ALL_SYS_PWRGD
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 R8G12 10K
32,35 PM_RSMRST#

c
R8H3
10K R8G5 0 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A
35,39 PATA_PWR_EN#

s
PATA_PWR_EN#_R
R7N1 2.2K
14,33,58 SMB_CLK
Default is 1-X BIOS_REC R8H2 0 BIOS_REC_R
for BIOS recovery 1-2 R7N2 2.2K
14,33,58 SMB_DATA

-
J8H1
R9E1 1K
13,28,33 PCIE_WAKE#

p
13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A

R8B4 10K
33 SMB_ALERT#
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
J2J10

o
1
2 CRB_SV_DET R8V4 10K CRB_SV_DET_R
B 3 B

t
SMC_RUNTIME_SCI#_R
SMC_RUNTIME_SCI#_R
CON3_HDR R7W4 0
SMC_RUNTIME_SCI# 32,35

13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A SMC_EXTSMI#_R


SMC_EXTSMI#_R

p
R8V6 0
SMC_EXTSMI# 32,35,42,57

+V3.3A 13,14,17,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 R8F11 SMC_WAKE_SCI#_R


SMC_WAKE_SCI#_R
8.2K R8V2 0
SMC_WAKE_SCI# 32,35

la
PM_BATLOW#_R
R9Y1
10K

.
J9J8
2
1 FWH_MFG_MODE R9Y3 0 FWH_MFG_MODE_R

NO_STUFF

w
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

w
+V3.3S 5,7,10,12,13,14,15,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

A A
R3P1 Capell Valley Intel Confidential
2K
1%

w
U8C1 Title
5

PM_ICH_PWROK
1 ALL_SYS_PWRGD 32,35,48 ICH7-M (3 of 4)
4 74AHC1G08
2 DELAY_VR_PWRGOOD 7
R8C8 Size Document Number Rev
10K
1.501
3

A D15378

Date: Wednesday, July 20, 2005 Sheet 16 of 60


5 4 3 2 1
5 4 3 2 1

+V5S 5,10,18,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 Layout Note:


+V3.3S 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 U7G1F Place at MCH edge +V1.05S 3,4,6,9,10,14,30,37,45,48,53,56,58
VCC5REF G10 L11

m
V5REF[1] Vcc1_05[1]
Vcc1_05[2] L12
+V5A 29,40,46,47,48,49,54,55,57 AD17 L14
+V3.3A 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 V5REF[2] Vcc1_05[3] C7V9 C7V10
1 Vcc1_05[4] L16
1 V5REF_SUS F6 L17 0.1uF 1uF C6V4
R7F6 CR7F1 V5REF_Sus Vcc1_05[5] 10% 10V 20% 270uF
Vcc1_05[6] L18 20%

o
100 BAT54 R8U6 CR8U1 AA22 M11 SMC0402
10 BAT54 Vcc1_5_B[1] Vcc1_05[7]
AA23 Vcc1_5_B[2] Vcc1_05[8] M18

CORE
AB22 Vcc1_5_B[3] Vcc1_05[9] P11
3
AB23 Vcc1_5_B[4] Vcc1_05[10] P18
3
AC23 T11

c
C7V15 Vcc1_5_B[5] Vcc1_05[11] Layout Note:
AC24 Vcc1_5_B[6] Vcc1_05[12] T18
D 0.1uF C7V2 AC25 Vcc1_5_B[7] Vcc1_05[13] U11 Place on D

.
10% 10V 0.1uF AC26 U18 secondary
SMC0402 10% 10V Vcc1_5_B[8] Vcc1_05[14]
AD26 Vcc1_5_B[9] Vcc1_05[15] V11 side under
SMC0402 AD27 V12
Vcc1_5_B[10] Vcc1_05[16] MCH
AD28 Vcc1_5_B[11] Vcc1_05[17] V14
Layout note: C7V15 needs be placed D26 V16
Vcc1_05[18]

s
Layout note: C7V2 needs be placed Vcc1_5_B[12]
within 100mils of pin AD17 of ICH7 D27 Vcc1_5_B[13] Vcc1_05[19] V17
within 100mils of pin F6 of ICH7 on the D28 V18 13,14,15,25,27,32,33,34,35,36,38,45,46,55,56 +V3.3
on the bottom side or 140 mils on
bottom side or 140 mils on the top E24
Vcc1_5_B[14] VCC PAUX Vcc1_05[20]
the top Vcc1_5_B[15]
E25 Vcc1_5_B[16] VccSus3_3/VccLAN3_3[1] V5
E26 V1 +V3.3S/1.5S_AZ_IO 27

it c
Vcc1_5_B[17] VccSus3_3/VccLAN3_3[2] C7V5
F23 Vcc1_5_B[18] VccSus3_3/VccLAN3_3[3] W2 Place within 100
4,10,27,48,56,58 +V1.5S F24 W7 mils of ICH on 0.1uF
15 +V1.5S_PCIE_ICH Vcc1_5_B[19] VccSus3_3/VccLAN3_3[4] +V3.3A/1.5A_AZ_IO 27 C7V6 10% 10V
G22 Vcc1_5_B[20] the bottom side
G23 U6 0.1uF SMC0402
FB6G1 Vcc1_5_B[21] Vcc3_3/VccHDA 10% 10V or 140 mils on
H22 Vcc1_5_B[22]
H23 R7 SMC0402 the top near pin
100ohm@100MHz C6F4 C6G10 C6G8 Vcc1_5_B[23] VccSus3_3/VccSusHDA
J22 Vcc1_5_B[24]
C6G9 0.1uF 0.1uF 0.1uF J23 AE23 3,4,6,9,10,14,30,37,45,48,53,56,58 +V1.05S
220uF 10% 10V 10% 10V 10% 10V Vcc1_5_B[25] V_CPU_IO[1]
Layout note: Place above K22 Vcc1_5_B[26] V_CPU_IO[2] AE26
4V SMC0402 SMC0402 SMC0402

a
K23 AH26

VCCA3GP
Caps within 100 mils of 20% Vcc1_5_B[27] V_CPU_IO[3] 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
L22 Vcc1_5_B[28]
ICH on the bottom side L23 AA7 C7V18 C7V16 C7V21
Vcc1_5_B[29] Vcc3_3[3] +V3.3S 0.1uF 0.1uF 4.7uF
or 140 mils on the top M22 Vcc1_5_B[30] Vcc3_3[4] AB12
near D28, T28, AD28 M23 AB20 10% 10V 10% 10V 10% 10V
Vcc1_5_B[31] Vcc3_3[5] SMC0402 SMC0402 SMC1206
N22 Vcc1_5_B[32] Vcc3_3[6] AC16
+V1.5S 4,10,27,48,56,58 N23 AD13 Place within 100 mils of
Vcc1_5_B[33] Vcc3_3[7]

IDE
5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S P22 AD18 ICH7 on the bottom side C7V12
Vcc1_5_B[34] Vcc3_3[8]

m
L6H1 1uH P23 AG12 or 140 mils on the top 0.1uF 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R6H3 1 GPLL_R GPLL_R_L Vcc1_5_B[35] Vcc3_3[9] 10% 10V +V3.3S
1 2 R22 Vcc1_5_B[36] Vcc3_3[10] AG15 near pin
R23 AG19 SMC0402
Place within 100 C6H1 C7H2 C6U1 Vcc1_5_B[37] Vcc3_3[11]
R24 Vcc1_5_B[38]
C mils of ICH on the 0.01UF 10uF 0.1uF R25 Vcc1_5_B[39] Vcc3_3[12] A5 C
10% 50V 6.3V 10% 10V

e
bottom side or 140 R26 Vcc1_5_B[40] Vcc3_3[13] B13
SMC0603 20% SMC0402 T22 B16 C7U2 C7U4 C7V13
mils on the top Vcc1_5_B[41] Vcc3_3[14] 0.1uF 0.1uF 0.1uF
T23 Vcc1_5_B[42] Vcc3_3[15] B7
T26 C10 10% 10V 10% 10V 10% 10V
Vcc1_5_B[43] Vcc3_3[16]

PCI
T27 D15 SMC0402 SMC0402 SMC0402
Vcc1_5_B[44] Vcc3_3[17]
T28 F9

h
4,10,27,48,56,58 +V1.5S Vcc1_5_B[45] Vcc3_3[18] Layout Note: Distribute in PCI section 14 +V3.3A_RTC
U22 Vcc1_5_B[46] Vcc3_3[19] G11
U23 Vcc1_5_B[47] Vcc3_3[20] G12
V22 Vcc1_5_B[48] Vcc3_3[21] G16
V23 Vcc1_5_B[49]

c
W22 W5 C7V7 C7V8
Vcc1_5_B[50] VccRTC 0.1uF 0.1uF
W23 Vcc1_5_B[51]
C7V20 Y22 P7 +V3.3A 10% 10V 10% 10V
0.1uF Vcc1_5_B[52] VccSus3_3[1] SMC0402 SMC0402
Y23 Vcc1_5_B[53]
Place within 100 mils 10% 10V A24 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
VccSus3_3[2]

-s
of ICH on the bottom SMC0402 B27 C24
Vcc3_3[1] VccSus3_3[3] C7U6 C8G2
side or 140 mils on VccSus3_3[4] D19
AG28 D22 0.1uF 0.1uF
the top near pin AG5 VccDMIPLL VccSus3_3[5]
G19 10% 10V 10% 10V
VccSus3_3[6]
AB7 SMC0402 SMC0402
4,10,27,48,56,58 +V1.5S Vcc1_5_A[1]
AC6 Vcc1_5_A[2] VccSus3_3[7] K3
AC7 Vcc1_5_A[3] VccSus3_3[8] K4
AD6 K5 +V3.3A 13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57
Vcc1_5_A[4] VccSus3_3[9]

ARX

p
C7V14 AE6 K6
Vcc1_5_A[5] VccSus3_3[10]
Place within 100 mils of 0.1uF AF5 L1
Vcc1_5_A[6] VccSus3_3[11]
ICH on the bottom side 10% 10V AF6 L2
Vcc1_5_A[7] VccSus3_3[12]

USB
SMC0402 AG5 L3 C7V4 C7V1
or 140 mils on the top Vcc1_5_A[8] VccSus3_3[13]
AH5 L6 0.1uF 0.1uF
Vcc1_5_A[9] VccSus3_3[14]
10% 10V 10% 10V

o
VccSus3_3[15] L7
+V3.3S 5,7,10,12,13,14,15,16,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
AD2 VccSATAPLL M6 SMC0402 SMC0402
VccSus3_3[16]
VccSus3_3[17] M7
B B

t
AH11 N7 4,10,27,48,56,58 +V1.5S
Vcc3_3[2] VccSus3_3[18]
Place within 100 mils of C7V19 +V1.5S 4,10,27,48,56,58 AB10 AB17
Vcc1_5_A[10] Vcc1_5_A[19]
ICH on the bottom side or 0.1uF AB9 AC17
Vcc1_5_A[11] Vcc1_5_A[20]
140 mils on the top 10% 10V AC10 Vcc1_5_A[12]

p
SMC0402 AD10 T7
Vcc1_5_A[13] Vcc1_5_A[21]
13,14,16,24,25,26,27,28,29,32,35,38,40,42,45,46,47,48,49,50,54,55,57 +V3.3A AE10 F17
Vcc1_5_A[14] Vcc1_5_A[22]
ATX

AF10 Vcc1_5_A[15] Vcc1_5_A[23] G17


C7H1 AF9 +V1.5S 4,10,27,48,56,58
1UF Vcc1_5_A[16]
AG9 Vcc1_5_A[17] Vcc1_5_A[24] AB8
Place within 100 mils of ICH on 20% C7U7

la
AH9 Vcc1_5_A[18] Vcc1_5_A[25] AC8
the bottom side or 140 mils on 0.1uF
the top near AG9 10% 10V +V1.5S 4,10,27,48,56,58 E3 K7 TP_ICHVCCSUS1
VccSus3_3[19] VccSus1_05[1]
SMC0402
C1 C28 TP_ICHVCCSUS2 4,10,27,48,56,58 +V1.5S
VccUSBPLL VccSus1_05[2]

.
G20 TP_ICHVCCSUS3
TP_VCCSUSLAN1 VccSus1_05[3]
C7U5 AA2
0.1uF TP_VCCSUSLAN2 VccSus1_05/VccLAN1_05[1]
Y7 VccSus1_05/VccLAN1_05[2]Vcc1_5_A[26] A1
10% 10V H6
Vcc1_5_A[27]
USB CORE

SMC0402 H7 +V1.5S 4,10,27,48,56,58


Vcc1_5_A[28]
J6 4,10,27,48,56,58 +V1.5S
Vcc1_5_A[29]
J7

w
Vcc1_5_A[30]
C7V3
ICH7M REV 1.02 EDS 0.1uF
Place within 100 mils of 10% 10V C7V11
ICH on the bottom side SMC0402 0.1uF
10% 10V
or 140 mils on the top
SMC0402

w
AG11
AG14
AG17
AG20
AG25
AC11

AD11
AD15
AD19
AD23

AH12
AH23
AH27
AA24
AA25
AA26

AB11
AB14
AB16
AB19
AB21
AB24
AB27
AB28

AE11
AE13
AE18
AE21
AE24
AE25

AF11
AF27
AF28

ICH7M REV 1.02 EDS


W24
W25
W26

AG1
AG3
AG7
AC2
AC5
AC9

AD1
AD3
AD4
AD7
AD8

AH1
AH3
AH7
AA1

AB4
AB6

AE2
AE4
AE8
R11
R12
R13
R14
R15
R16
R17
R18

U12
U13
U14
U15
U16
U17
U24
U25
U26

AF2
AF4
AF8
P28

V13
V15
V24
V27
V28

Y24
Y27
Y28
T12
T13
T14
T15
T16
T17

W6
R1

U4

V2

Y3
T6

A A
U7G1E Capell Valley Intel Confidential
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]

Title

w
ICH7-M (4 of 4)
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]

Size Document Number Rev


M12
M13
M14
M15
M16
M17
M24
M27
M28
G14
G18
G21
G24
G25
G26
C27
D10
D13
D18
D21
D24

H24
H27
H28

N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26

A D15378 1.501
A23

B11
B14
B17
B20
B26
B28

E15

K24
K27
K28

P12
P13
P14
P15
P16
P17
P24
P27
F12
F27
F28

L13
L15
L24
L25
L26
J24
J25
J26

M3
M4
M5
G1
G2
G5
G6
G9
C2
C6

H3
H4
H5

N1
N2
N5
N6
A4

B1
B8

E1
E2
E4
E8

P3
P4
F3
F4
F5

J1
J2
J5

Date: Wednesday, July 20, 2005 Sheet 17 of 60


5 4 3 2 1
5 4 3 2 1

m
10,20,49,56,58 +V2.5S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S

C6D15 C7T1
0.1uF 0.1uF

7
Vp

Vp
CR7D1 ESD DIODE ARRAY CR7T1 ESD DIODE ARRAY

c
D D
CRT_Q_VSYNC

.
CRT_RED 1 8 1 8
I/O1 I/O6 7,20 TV_DACA_OUT I/O1 I/O6 CRT_Q_HSYNC
CRT_GREEN 2 6 2 6
I/O2 I/O5 7,20 TV_DACB_OUT I/O2 I/O5
CRT_BLUE 4 5 4 5
I/O3 I/O4 7,20 TV_DACC_OUT I/O3 I/O4

s
Vn

Vn
it c
3

3
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

a
+V3.3S
+V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

R7R12 C6D12
10K 5 0.1uF 5,10,17,19,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S
13,19,27,55,56 +VBATS

m
5% U7D7
INVERTER +V5S_F_DAC
DOCK_VGA_EN# 2 4 CRT_EN# F2A1
+
C R2M7 C
R7R13 1K

e
1.1A

2
10K 3
5% DDC_GATE
1 Q2B1
NO_STUFF Note: FB2A3
10,20,49,56,58 +V2.5S BSS138 50OHM
For video bandwidths > 200MHz:
R2M8

h
C3B1, C3A4, C2B1, C2A5, C2B2, C2B3 = 3.3pF
C7R11 100K
C3A1, C2A4, C2A6 = No_Stuff
DDC_SRC

3
U7D6
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
0.1uF +V3.3S FB3A1, FB2A5, FB2B2 = Short

+V5S_L_DAC
1 OE1# VCC 8

c
2 R2A5 R2B1
7 CRT_RED 1A OE2# 7 CRT_Q_RED 2.2k 2.2k
3 1B 2B 6
TP_DOCK_VGA_RED 4 R8E1
GND 2A 5 2.2K Q8E1
74CB3Q330 BSS138

-s
2 3 CRT_DDC_DATA_ISO
7 CRT_DDC_DATA
10,20,49,56,58 +V2.5S

5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
C7R7 +V3.3S
CRT_DDC_CLK_ISO
U7D8 0.1uF

1
1 OE1# VCC 8

p
2 7 CRT_Q_RED FB3B1 CRT_L_RED FB3A1
7 CRT_GREEN 1A OE2#
3 6 CRT_Q_GREEN 47ohm@100MHz 47ohm@100MHz
TP_DOCK_VGA_GRN 1B 2B C3B1 C3A4 C3A1
4 GND 2A 5
R3B1 10pF 22pF 10pF
74CB3Q330 150 5%
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 1% J2A2B

o
GND1 19
CRT_L2_RED RED 14 24 NC2
B B

t
10,20,49,56,58 +V2.5S GND2 18
R8E2 CRT_Q_GREEN FB3B2 CRT_L_GREEN FB2A5 CRT_L2_GREEN GRN 13 23 DATA
C7R9 2.2K Q8E3 47ohm@100MHz 47ohm@100MHz GND3 17
R3B2 C2B1 C2A5 C2A4 CRT_L2_BLUE BLU 12 22 HSYNC
BSS138 150
U7D9 0.1uF 10pF 22pF 10pF VCC 16
1%

p
1 8 2 3 5% NC1 11 21 VSYNC
OE1# VCC 7 CRT_DDC_CLK GND4
7 CRT_BLUE 2 1A OE2# 7 15
3 6 CRT_Q_BLUE GND5 10 20 CLK
TP_DOCK_VGA_BLUE 1B 2B +V3.3S
4 GND 2A 5
5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 CRT_Q_BLUE FB2B3 CRT_L_BLUE FB2B2 2IN1
74CB3Q330 1 47ohm@100MHz 47ohm@100MHz

la
R2B2 C2B2 C2B3 C2A6
150 10pF 22pF 10pF
1% 5%
+V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

.
C7R12

U7D11 0.1uF CRT_Q_VSYNC R7E1 39 CRT_R_VSYNC


1 OE1# VCC 8
7 CRT_VSYNC 2 1A OE2# 7
3 6 TP_DOCK_Q_VSYNC CRT_Q_HSYNC R7E2 39 CRT_R_HSYNC

w
CRT_Q_VSYNC 2Y 1Y
4 GND 2A 5
C7E1 C7D1
SN74LVC2G125 33pF 33pF
5% 5%
NO_STUFF NO_STUFF

w
Buffers provide
voltage translation +V3.3S 5,7,10,12,13,14,15,16,17,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
A from 2.5 to 3.3V A
C7T2 Capell Valley Intel Confidential
U7E1 0.1uF Title

w
1 8
7 CRT_HSYNC 2
OE1#
1A
VCC
OE2# 7 CRT
3 6 TP_DOCK_Q_HSYNC
CRT_Q_HSYNC 2Y 1Y
4 GND 2A 5

SN74LVC2G125 Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 18 of 60
5 4 3 2 1
5 4 3 2 1

m
+V5S 5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56

o
C6G2
+V3.3S
+VBAT 52,54,55,56 0.1uF 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

c
C6G4 C6F2
D 0.1uF D
10%

.
0.1uF

it cs
LVDS Panel Backlight
BIOS Note: Disable both
BKLTSEL lines before
enabling one.
+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

a
5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S

C7T11
R7T10 +V3.3S
U7E5 0.1uF 10K R6F2 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
1 8 10K C7E5 +VBAT 52,54,55,56
35,42 L_BKLTSEL0# OE1# VCC
7 L_BKLTCTL 2 1A OE2# 7 L_BKLTSEL1# 35,42

m
3 6 U6F1 0.1uF
1B 2B
4 GND 2A 5 L_CLKCTLB 7,37 35,42 L_BKLTSEL1# 1 OE# VCC 5
GMCH_PWM Support +V5S 5,10,17,18,20,25,26,39,41,43,44,45,47,51,52,54,55,56
74CBT3306 2 J5F1
GM_Data_D Support 7,37 L_CLKCTLA A
C 1 VDD_BLI C
GM_CLK_D Support

e
3 GND Y 4 2 VSS_BLI
3 VSS_DBC
74CBTLV1G125 4 VDD_DBC
DBL_CLK 5 DBL_CLK
L_BRIGHTNESS 6 DBL_DATA
7 ENA_BL

h
7 L_BKLTEN
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S R6V3 100K 8 NC
9 VDD_ALS
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 10 VSS_ALS
32,36 EMA_ALS_CLK 11 ALS_CLK

c
Q5G2 32,36 EMA_ALS_DATA 12 ALS_DATA
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 13 ALS_INTR
32,45 KBC_PROG_TX# L_VBATS_LPP
13,18,27,55,56 +VBATS SI4425DY 14 VDD_LPP
3 8 R6V2 15 VSS_VDL
2 7 10K
5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
R6V1 +V3.3S L_VDD_VDL1 16 VDD_VDL1

-s
1 6 10K L_VDD_VDL2 17 VDD_VDL2
5 18 VDD_VCL
19 RSVD
C5V5 20 VCL_CLK
7 L_DDC_CLK
R5V12 1000pF C5G2 C6F3
4

7 L_DDC_DATA 21 VCL_DATA
1M 22UF 0.1uF 22 A0M
10% 7 LA_DATAN0
7 LA_DATAP0 23 A0P
3 L_VDDEN_LPP#

R5V11 100K L_VDDEN_LPP_D# 24 VSS_SHIELD1

p
7 LA_DATAN1 25 A1M
7 LA_DATAP1 26 A1P
27 VSS_SHIELD2
7 LA_DATAN2 28 A2M
7 LA_DATAP2 29 A2P

o
30 VSS_SHIELD3
7 LA_CLKN 31 VDL_CLKAM
7 LA_CLKP 32 VDL_CLKAP
B B

t
L_VDDEN Q6G1 33 VSS
BSS138 J6E1 34 B0M
7 LB_DATAN0
1 L_VBATS_LPP 7 LB_DATAP0 35 B0P
7 L_VDDEN L_VDD_VDL2 1
2 36 VSS_SHIELD4
3 7 LB_DATAN1 37 B1M

p
R6V10
2

4 7 LB_DATAP1 38 B1P
L_VDD_VDL1 39 VSS_SHIELD5
100K L_VDD_VDL 5
6 7 LB_DATAN2 40 B2M
7 LB_DATAP2 41 B2P
6Pin_HDR 42 VSS_SHIELD6

la
7 LB_CLKN 43 VDL_CLKBM
7 LB_CLKP 44 VDL_CLKBP

+V3.3S 5,7,10,12,13,14,15,16,17,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 LVDS,CONN44


LPP Jumper J6E1 Key
SI2307DS

.
Jumper Default Option Description
Q6E1
2 3
J6E1 5-6 J5F1 Pin-16 gets +V3.3S
C6E14 C7E6 4-5 J5F1 Pin-16 gets +VBATS

w
R6E2 C6E9
1M 1000pF 22uF 0.1uF J6E1 2-3 J5F1 Pin-17 gets +V3.3S
1-2 J5F1 Pin-17 gets +VBATS
1

R6E3 100K L_VDDEN_D#


3 L_VDDEN#

w
A A
Q6E2 Capell Valley Intel Confidential
BSS138
L_VDDEN Title

w
1

LVDS
2

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 19 of 60
5 4 3 2 1
5 4 3 2 1
5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58
+V3.3S +V3.3S
5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

m
C6M9
R6M10 0.1uF
10K 5
5% U6A4
INVERTER

o
DOCK_TV_EN# 2 4 TV_EN#

Layout Note:
R6M12 Place 150 Ohm termination
10K 3

c
resistors, ferrite beads and
5% 10,18,49,56,58 +V2.5S
capicators close to
D NO_STUFF
connector
D

.
C6M11
U6A5
1 8 0.1uF
OE1# VCC
7,18 TV_DACA_OUT 2 1A OE2# 7
3 6 DACA FB2A2 DACA_L

s
TP_DOCK_TV_DACA_OUT 1B 2B 150ohm@100MHz
4 GND 2A 5
C1A3 C1A1
74CB3Q330 R1M1 5.6pF 5.6pF
150 4.5% 4.5%
1%

it c
10,18,49,56,58 +V2.5S

C6M7
U6B1
1 8 0.1uF
OE1# VCC Note:
7,18 TV_DACB_OUT 2 1A OE2# 7
3 6 DACB FB2A1 DACB_L ESD Diode Array for the TV
TP_DOCK_TV_DACB_OUT 1B 2B 150ohm@100MHz
4 GND 2A 5 DAC A, DAC B, DAC C signals
C2A3 C2A2
located on CRT page.
74CB3Q330 R2M6 5.6pF 5.6pF

a
150 4.5% 4.5%
1%
10,18,49,56,58 +V2.5S Port Value Voltage
IO2 IO1 IO0 Format Aspect Ratio Line1 Line2 Line3
C6N1 0 0 0b 525i (480) 4:3 0V 0V 0V
U6A2 0 0 1b 525i (480) 16:9 0V 0V 5V
1 8 0.1uF 0 0 Xb 525i (480) 4:3 Letterbox 0V 0V 2.2V
OE1# VCC

m
2 7 0 1 0b 525p (480) 4:3 0V 5V 0V
7,18 TV_DACC_OUT 1A OE2# DACC 0 1 1b 525p (480) 16:9 0V 5V 5V
3 6 FB1A1 DACC_L
TP_DOCK_TV_DACC_OUT 1B 2B 150ohm@100MHz 0 1 Xb 525p (480) 4:3 Letterbox 0V 5V 2.2V
4 GND 2A 5
C1A4 C1A2 X 1 0b 750p (720) 4:3 2.2V 5V 0V
C 74CB3Q330 R1M2 5.6pF 5.6pF X 1 1b 750p (720) 16:9 2.2V 5V 5V C
150 4.5% 4.5% J2A1 1 0 0b 1125i (1080) 4:3 5V 0V 0V

e
1% 1 8 1 0 1b 1125i (1080) 16:9 5V 0V 5V
2 9 1 1 0b 1125p (1080) 4:3 5V 5V 0V
3 10 1 1 1b 1125p (1080) 16:9 5V 5V 5V
4 11
5 12

h
6 13
7 14

CON14_DCONN-CP4120

c
Note:
Pins 12 & 14 are shorted
inside D-Connector plug.

- s
5,10,17,18,19,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S

p
5,10,17,18,19,25,26,39,41,43,44,45,47,51,52,54,55,56 +V5S

+V3.3S 5,7,10,12,13,14,15,16,17,18,19,21,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

C2A7

o
R2A11 R2A12 R2A13 R2A14 R2A15
2.2K 2.2K 1.0uF 10K
B B

t
5.90K 5.90K
U2A2 1% 1%
10 1 DLINE3_IO R2A16 10K DLINE3
I2C_RST#

VDD IO_0 DLINE2_IO R2A17 10K DLINE2


7 TV_DCONSEL1 9 SDA IO_1 2
8 3 DLINE1_IO R2A18 10K DLINE1
7 TV_DCONSEL0 SCL IO_2

p
7 INT# IO_3 4
6 RESET# VSS 5

R2A19 R2A20
I2C - PCA9537 4.7K 4.7K

. la
A

ww Capell Valley
Title
Intel Confidential
A

w
TV

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 20 of 60
5 4 3 2 1
5 4 3 2 1

o m
c
D D

.
M_A_DQ[63:0] 8

s
J5P1A CON200_DDR2-SODIMM-STAN
8,23 M_A_A[13:0] M_A_A0 M_A_DQ0
102 A0 DQ0 5
M_A_A1 101 7 M_A_DQ1
M_A_A2 A1 DQ1 M_A_DQ2
100 A2 DQ2 17
M_A_A3 99 M_A_DQ3
DQ3 19

it c
M_A_A4 A3 M_A_DQ4
98 A4 DQ4 4
M_A_A5 97 M_A_DQ5
M_A_A6 A5 DQ5 6 M_A_DQ6
94 A6 DQ6 14
M_A_A7 92 M_A_DQ7
M_A_A8 A7 DQ7 16 M_A_DQ8
93 A8 DQ8 23
M_A_A9 91 25 M_A_DQ9 7,9,22,34,46,47,56,58 +V1.8 J5P1B CON200_DDR2-SODIMM-STAN
M_A_A10 A9 DQ9 M_A_DQ10
105 A10/AP DQ10 35
M_A_A11 90 37 M_A_DQ11 112 18
M_A_A12 A11 DQ11 M_A_DQ12 VDD1 VSS16
89 A12 DQ12 20 111 VDD2 VSS17 24
M_A_A13 M_A_DQ13

a
116 A13 DQ13 22 117 VDD3 VSS18 41
86 M_A_DQ14
A14 DQ14 36 M_A_DQ15
96 VDD4 VSS19 53
84 A15 DQ15 38 95 VDD5 VSS20 42
85 M_A_DQ16
8,23 M_A_BS2 A16_BA2 DQ16 43 M_A_DQ17
118 VDD6 VSS21 54
DQ17 45 M_A_DQ18
81 VDD7 VSS22 59
8,23 M_A_BS0 107 BA0 DQ18 55 82 VDD8 VSS23 65
106 57 M_A_DQ19
5,7,10,12,13,14,15,16,17,18,19,20,22,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 87 60
8,23 M_A_BS1 BA1 DQ19 M_A_DQ20 VDD9 VSS24
7,23 M_CS#0 110 S0# DQ20 44 103 VDD10 VSS25 66
M_A_DQ21

m
7,23 M_CS#1 115 S1# DQ21 46 88 VDD11 VSS26 127
30 M_A_DQ22
7 M_CLK_DDR0 CK0 DQ22 56 M_A_DQ23 C4C12 C4C10
104 VDD12 VSS27 139
7 M_CLK_DDR#0 32 CK0# DQ23 58 VSS28 128
164 M_A_DQ24 2.2uF
7 M_CLK_DDR1 CK1 DQ24 61 199 VDDSPD VSS29 145
C 7 M_CLK_DDR#1 166 CK1# DQ25 63
M_A_DQ25 0.1uF
VSS30 165 C
M_A_DQ26

e
7,23 M_CKE0 79 CKE0 DQ26 73 83 NC1 VSS31 171
80 75 M_A_DQ27 120 172
7,23 M_CKE1 CKE1 DQ27 M_A_DQ28 NC2 VSS32
8,23 M_A_CAS# 113 CAS# DQ28 62 50 NC3 VSS33 177
108 64 M_A_DQ29 69 187
8,23 M_A_RAS# RAS# DQ29 M_A_DQ30 7,23 PM_EXTTS#0 NC4 VSS34
8,23 M_A_WE# 109 WE# DQ30 74 163 NCTEST VSS35 178
SA0_DIM0 198 M_A_DQ31
DQ31 76 190

h
SA1_DIM0 SA0 M_A_DQ32 VSS36
200 SA1 DQ32 123 47,58 M_VREF_DIMM0 1 VREF VSS37 9
197 M_A_DQ33
14,22,23 SMB_CLK_S2 SCL DQ33 125 M_A_DQ34 C6P2 C6P1 VSS38 21
14,22,23 SMB_DATA_S2 195 SDA DQ34 135 201 GND0 VSS39 33
M_A_DQ35 2.2uF
DQ35 137 M_A_DQ36
202 GND1 VSS40 155

c
R4C17 R4C25 7,23 M_ODT0 114 124 0.1uF 34
ODT0 DQ36 M_A_DQ37 VSS41
7,23 M_ODT1 119 ODT1 DQ37 126 VSS42 132
134 M_A_DQ38 47 144
8 M_A_DM[7:0] M_A_DM0 DQ38 M_A_DQ39 VSS1 VSS43
10K 10K 10
M_A_DM1 DM0 DQ39 136 M_A_DQ40
133 VSS2 VSS44 156
26 DM1 DQ40 141 183 VSS3 VSS45 168

s
M_A_DM2 52 M_A_DQ41 7,9,22,34,46,47,56,58 +V1.8
M_A_DM3 DM2 DQ41 143 M_A_DQ42
77 VSS4 VSS46 2
67 DM3 DQ42 151 12 VSS5 VSS47 3
M_A_DM4 130 M_A_DQ43
DM4 DQ43 153 48 VSS6 VSS48 15

-
M_A_DM5 147 M_A_DQ44
M_A_DM6 DM5 DQ44 140 M_A_DQ45 C4C11 C5C9 C5B17 C5R1
184 VSS7 VSS49 27
170 DM6 DQ45 142 78 VSS8 VSS50 39
M_A_DM7 185 M_A_DQ46
DM7 DQ46 152 M_A_DQ47 0.1uF 0.1uF 0.1uF 0.1uF
71 VSS9 VSS51 149
8 M_A_DQS[7:0] DQ47 154 72 VSS10 VSS52 161
M_A_DQS0 13 M_A_DQ48
M_A_DQS1 DQS0 DQ48 157 M_A_DQ49
121 VSS11 VSS53 28

p
31 DQS1 DQ49 159 122 VSS12 VSS54 40
M_A_DQS2 51 M_A_DQ50
M_A_DQS3 DQS2 DQ50 173 M_A_DQ51
196 VSS13 VSS55 138
70 DQS3 DQ51 175 Layout Note: Place these Caps near So-Dimm0. 193 VSS14 VSS56 150
M_A_DQS4 131 M_A_DQ52
M_A_DQS5 DQS4 DQ52 158 M_A_DQ53
8 VSS15 VSS57 162
148 DQS5 DQ53 160
M_A_DQS6 M_A_DQ54

o
169 DQS6 DQ54 174
M_A_DQS7 188 M_A_DQ55
8 M_A_DQS#[7:0] M_A_DQS#0 DQS7 DQ55 176 M_A_DQ56
11 DQS#0 DQ56 179
B B

t
M_A_DQS#1 29 M_A_DQ57
M_A_DQS#2 DQS#1 DQ57 181 M_A_DQ58
49 DQS#2 DQ58 189
M_A_DQS#3 68 M_A_DQ59
M_A_DQS#4 DQS#3 DQ59 191 M_A_DQ60
129 DQS#4 DQ60 180
M_A_DQS#5 146 M_A_DQ61
M_A_DQS#6 DQS#5 DQ61 182 M_A_DQ62

p
167 DQS#6 DQ62 192
M_A_DQS#7 186 194 M_A_DQ63
DQS#7 DQ63

Layout Note: Place these Caps near So-Dimm0.

la
7,9,22,34,46,47,56,58 +V1.8

.
C4C15 C5C12 C5C5 C5C10 C5C4
2.2uF 2.2uF 2.2uF 2.2uF 2.2uF

ww Capell Valley
Title
Intel Confidential
A

w
DDR SODIMM 0

Size Document Number Rev


A D15378 1.501
Date: Wednesday, July 20, 2005 Sheet 21 of 60
5 4 3 2 1
5 4 3 2 1

o m
c
D D

s.
J5N1A
M_B_DQ[63:0] 8
CON200_DDR2-SODIMM-REV
8,23 M_B_A[13:0] M_B_A0 M_B_DQ0
102 A0 DQ0 5
M_B_A1 101 7 M_B_DQ1
M_B_A2 A1 DQ1 M_B_DQ2
100 DQ2 17

it c
M_B_A3 A2 M_B_DQ3
99 A3 DQ3 19
M_B_A4 98 M_B_DQ4
M_B_A5 A4 DQ4 4 M_B_DQ5
97 A5 DQ5 6
M_B_A6 94 M_B_DQ6 7,9,21,34,46,47,56,58 +V1.8 J5N1B CON200_DDR2-SODIMM-REV
M_B_A7 A6 DQ6 14 M_B_DQ7
92 A7 DQ7 16
M_B_A8 93 23 M_B_DQ8 112 18
M_B_A9 A8 DQ8 M_B_DQ9 VDD1 VSS16
91 A9 DQ9 25 111 VDD2 VSS17 24
M_B_A10 105 M_B_DQ10
M_B_A11 A10/AP DQ10 35 M_B_DQ11
117 VDD3 VSS18 41
90 A11 DQ11 37 96 VDD4 VSS19 53
M_B_A12 M_B_DQ12

a
89 A12 DQ12 20 95 VDD5 VSS20 42
M_B_A13 116 M_B_DQ13
A13 DQ13 22 M_B_DQ14
118 VDD6 VSS21 54
86 A14 DQ14 36 81 VDD7 VSS22 59
84 M_B_DQ15
A15 DQ15 38 M_B_DQ16
82 VDD8 VSS23 65
8,23 M_B_BS2 85 A16_BA2 DQ16 43 87 VDD9 VSS24 60
45 M_B_DQ17 103 66
DQ17 M_B_DQ18 VDD10 VSS25
8,23 M_B_BS0 107 BA0 DQ18 55 88 VDD11 VSS26 127
106 57 M_B_DQ19
5,7,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58 +V3.3S 104 139
8,23 M_B_BS1 BA1 DQ19 M_B_DQ20 VDD12 VSS27

m
7,23 M_CS#2 110 S0# DQ20 44 VSS28 128
115 M_B_DQ21
7,23 M_CS#3 S1# DQ21 46 199 VDDSPD VSS29 145
5,7,10,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,35,37,39,42,43,44,45,47,48,49,51,54,55,56,57,58

30 M_B_DQ22
7 M_CLK_DDR3 CK0 DQ22 56 M_B_DQ23 C4B11 C4B13 VSS30 165
7 M_CLK_DDR#3 32 CK0# DQ23 58 83 NC1 VSS31 171
C 7 M_CLK_DDR2 164 CK1 DQ24 61
M_B_DQ24 2.2uF 120 NC2 VSS32 172 C
M_B_DQ25 0.1uF

e
7 M_CLK_DDR#2 166 CK1# DQ25 63 50 NC3 VSS33 177
79 73 M_B_DQ26 69 187
7,23 M_CKE2 CKE0 DQ26 M_B_DQ27 NC4 VSS34
7,23 M_CKE3 80 CKE1 DQ27 75 163 NCTEST VSS35 178
+V3.3S 113 M_B_DQ28
8,23 M_B_CAS# CAS# DQ28 62 M_B_DQ29 7,23 PM_EXTTS#1 VSS36 190
8,23 M_B_RAS# 108 RAS# DQ29 64 47,58 M_VREF_DIMM1 1 VREF VSS37 9
109 M_B_DQ30
DQ30 74 21

h