Kinetis Mexeedev

Freescale Kinetis Seminar
ARM Cortex-M4 Microcontrollers

Design Potential. Realized
Gonzalo Delgado & Paolo Alcantara

TM
Freescale, the Freescale logo, CodeWarrior, ColdFire and Powerquicc are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Flexis, Processor Expert and QorIQ are
trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and
Power.org logos and related marks are trademarks and service marks licensed by Power.org. ARM is the registered trademark of ARM Limited. ARM Cortex-M4 and ARM Cortex-M3 are
trademarks of ARM Limited. © 2010 Freescale Semiconductor, Inc.
Top Level Agenda
Top Level Agenda
Freescale Kinetis 1-Day Seminar
► Freescale Kinetis Overview

► System Architecture
► Peripherals Overview
► “Hands-On” Exercise
► Third Party Ecosystem
► Q&A, Close
Freescale Confidential and Proprietary

TM
2
Freescale Kinetis Overview
TM
Kinetis: Overview
 The most scalable portfolio of low-power

ARM Cortex-M4 MCUs available today
 Innovative 90nm Thin-Film Storage

Flash with FlexMemory embedded
EEPROM capability
 Exceptional mixed-signal integration
 One of the most comprehensive ARM®

enablement portfolios, including solutions
from Freescale as well as the ARM
connected community

TM
MCU Portfolio: Solutions-Focused and Core Agnostic
Built on…
Power 90nm
Market-leading performance, reliability and software
100-400+ MIPS
Architecture® enablement for automotive and industrial applications.
Technology
32-bit Kinetis NEW!

Scalable, ultra-low-power product families with
based on ARM® 90nm 50-200 MIPS bundled software enablement for industrial and
Cortex™-M4 core consumer applications.
ColdFire Application-oriented ultra-low power solutions with

NEW!
ColdFire+ 90nm 50-200 MIPS optimized enablement, integration and cost for appliance,
metering and consumer applications.
Digital Signal Controllers Application-oriented solutions for automotive, motor

16-bit control and power conversion applications.
S12 and S12X
Scalable cost & power-optimized product families for

8-bit RS08 and S08
industrial, automotive and consumer applications.
Giving customers an ideal solution regardless of architecture preference.

TM
Kinetis MCUs
Scalable Mixed-Signal Consumer and Industrial Microcontroller Families
Market-leading software
enablement – IDE, RTOS Innovative low-power
and initialization tools from 90nm thin film storage
Freescale and leading ARM flash process with
ecosystem providers to speed FlexMemory EEPROM
time to market capability
More than 40 New 90nm
ColdFire+ MCUs
More than 200 New 90nm

Kinetis MCUs
Hundreds of new 32-
bit mixed-signal MCUs Ultra-low power
with huge performance, consumption with flexible
memory and feature power management to
scalability balance performance
and battery life
More than 240 new 90nm 32-bit

MCUs in scalable product families
First available broad-market MCU samples based on ARM Cortex-M4!
TM
Freescale’s Industrial and Multi-Market 32-bit MCU Portfolio
General Energy & Factory
Appliance Consumer Medical
Purpose Metering Automation
5V Capability Low Power Large, Measurement Precision Signal

Compatible Engine Analog Processing
High- USB Portfolio
performance Connectivity Power Line Ultra-Low High-Speed
Timers Full Connectivity Communication Power Peripherals
Encryption Offering
Human Wireless Connectivity – Integrated
Machine Touch Low Power Capability Continua Analog and
Interface Sensing Mixed-Signal
Precision Analog
Kinetis MCUs
ColdFire+ MCUs
Offers customers great solutions for a variety of applications.

TM
Key Differentiators
Memory Technology, Low power, and Integration
TM
90nm TFS Flash: Differentiators
Freescale’s 90nm Thin Film Storage (TFS) flash memory

technology with FlexMemory will deliver outstanding
performance, value, reliability and low power for next
generation industrial and consumer microcontrollers.
 Industry leading bit-level reliability through

revolutionary silicon nano crystal technology
 Fast, low-voltage transistors that provide low-
power read capability and help satisfy the
increasing demands of power-sensitive
applications with full flash operation specified
down to 1.71 volts
 Flash access times of >30nsec; and excellent
area efficiency, enabling a rich level of memory
and peripheral integration across flash
densities, while maintaining optimal MCU cost
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc.,
TM
Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.
90nm TFS Flash: Differentiators
Traditional embedded
Attribute FlexMemory
EEPROM
Read-while-write with
Yes Yes
program memory
Granularity Byte write/erase Byte write/erase
~100usec
~1-5msec (word or byte program,
Write Time
(byte write only) brown-outs w/o loss/corruption of
data)
Erase + Write Time ~5-10 msec ~750usec + ~750usec = ~1.5msec
Guaranteed Can exceed 10Mcycles

50-300K cycles (fixed)
Endurance [configurable]
Write Voltage ≥ 2.0V ≥ 1.71V

Configurable
Flexibility Fixed by part number
[Quantity vs. Endurance]
TFS Value = reliability, lower power, EEPROM, scalability
TM
Kinetis Power Modes
Typical
Recovery IDD:
Time:
Starting @
<200uA/MHz
4us
4us
4us
4us 1.2uA - 7uA
35us 1uA - 5uA
35us 750nA - 2uA

100us 500nA – 1.5uA
+ EE restore
Values subject to change

TM
Kinetis Power Modes
Mode Definition
Run MCU can be run at full speed.
Wait Allows peripherals to function, while CPU goes to sleep reducing power consumption.
CPU and peripheral clock maximum frequency is restricted. CPU/Platform clock
VLP Run
is restricted to 2MHz. Flash access is restricted to 1MHz. LVD is off.
VLP Wait Similar to VLP Run, with CPU in sleep to further reduce power.
Stop MCU is in static state. Lowest power mode that retains all registers while maintaining LVD protection.
MCU is in static state with LVD operation off. Lowest power mode with
VLP Stop
ADC, LPT, RTC, LCD, HSCMP, DAC, and pin interrupts functional.
MCU is in low leakage state retention power mode. LLWU controls wakeup sources
LL Stop
including LPT, RTC, LCD, HSCMP, DAC and select pin interrupts.
Powering down most internal logic. All system RAM contents are retained and I/O states held.
VLL Stop 3
LLWU controls wakeup sources (up to 16 GPIOs, LPT, RTC, LCD, HSCMP, and DAC)
VLL Stop 2 Similar to VLL Stop 3, partial system RAM retention. FlexRAM contents can optionally be retained.
VLL Stop 1 Similar to VLL Stop 3, with only 32 byte register file retention.
TM
ARM Cortex-M4(F) Processor
Cortex-M4(F) new features
 Single cycle MAC (Up to 32 x 32 + 64 -> 64)
 DSP extensions by default
 Single Precision Floating Point Unit (optional)
Freescale IP and Innovation

 On-chip instructions / data cache (optional)
 Cross-Bar Switch (concurrent multi-master/slave access)
 On-chip DMA for CPU off-load
 Low-leakage Wake-up (in addition to AWIC) Unit
Freescale IP for Digital Signal Processing

Dotted boxes denote optional blocks
 Motor Control:
Advanced algorithms, longer lifespan, power efficiency
 Automation
High calculation and algorithm bandwidth at a low cost
 Power management
Designed for low/battery powered systems
 Audio and Video
5x performance improvement over software, making batteries last longer
TM
Kinetis Family
200 scalable and compatible Devices
TM
14
Kinetis Family Overview
Common Common Common

K70 System IP Analog IP Digital IP
Development
512KB-1MB,
196-256pin 32-bit ARM Bundled IDE
CRC
Cortex-M4 Core 16-bit ADCs w/ Processor
K60 w/ DSP Instructions Expert
I2 C
256KB-1MB, Next Generation Bundled OS
100-256pin
Flash Memory USB, TCP/IP,
Programmable SAI (I2S)
K50 High Reliability, Gain Amplifiers Security
128-512KB, Fast Access
UARTs/SPIs Modular Tower
64-144pin FlexMemory w/ H/ware
EEPROM capability Development
K40 12-bit DACs
Programmable
Delay Block System
64-512KB, SRAM
64-144pin External Bus Application
Memory Interface Software
K30 Protection Unit High-speed Stacks,
Motor Control
64-512KB, Comparators Peripheral
eDMA Timers, PIT, LPT
64-144pin
Drivers & App.
K20 Low Voltage, eSDHC Libraries
32KB-1MB, Low Power Multiple Low-power (Motor Control,
Operating Modes, Touch Sensing HMI, USB)
32-144pin RTC
Clock Gating
K10 (1.71V-3.6V , optional *128k Flash and higher Broad 3rd party
32KB-1MB, with 5V tolerant I/O) **120MHz & 150MHz only ecosystem
32-144pin ***256 pin only
-40°C to 105°C
TM
CPU Frequency Options
Maximum CPU
Frequency Across Kinetis
Families
TM
Embedded Memory Options
Kinetis
Families
WITHOUT
FlexMemory
Kinetis
Families
WITH
FlexMemory
TM
DIGITAL I/O = UART, SPI, I2C, CAN, TIMER, etc.
ANALOG I/O = OSC, ADC, CMP, etc.
Pin Compatibility Across Families
LCD
DIG / ANA I/O + LCD power
DIG / ANA I/O + sLCD pins
DIG / ANA I/O

DIGITAL I/O
DIGITAL I/O
DIG / ANA I/O + LCD

DIG / ANA I/O
K10 K30
DIGITAL I/O
DIGITAL I/O
K20
DIG / ANA I/O + LCD

48-pin 64-pin orK40 80-pin
48-pin 64-pin
96 segments 192or 80-pin
segments
(8 x 12) (8 x 24)
General Purpose 96 segments 192 segments
(8 x 12) (8 x 24)
DIGITALUSB
I/O
DIGITAL I/O USB DIGITAL
USB I/O
+ sLCD
DIGITAL I/O USB
K10  K20 & K30  K40 = Add USB
The only difference will be 4 extra USB pins and 4 less digital I/O pins
K10  K30 & K20  K40 = Add Segment LCD

Digital & Analog I/O signals maintain placement order
Segment LCD signals are muxed with existing Digital & Analog I/O signals
Most Digital I/O signals muxed with Segment LCD signals become available on added pins by larger package
K20  K60 = Add Ethernet

All Ethernet signals are muxed with existing Digital & Analog I/O signals
TM
Kinetis Peripherals
HMI, Connectivity, Communications, Interfaces, Integrity & Security
TM
Feature Summary: HMI (Human Machine Interface)
MCU
123
456
789
0#
*
Low Power Touch Sensing Low power wake-up via touch, H/ware module
(All Kinetis families) avoids polling method of s/ware implementations
Blink mode operation reduces power, Failure

Low Power Segment LCD detection in s/ware of segment, connector or LCD-
(K30, K40 families) to-connector faults
8-bit QVGA (MCU), 24-bit SVGA with ext. memory
Graphics LCD
Bus Master – memory to LCD data transfer with no
(K70 family) CPU intervention
Audio Interface (DSP + IIS) M4 core - fast/efficient processing, IIS - easy

(All Kinetis families) integration of audio processing h/ware
TM
Feature Summary: Connectivity & Communications
IEEE 1588 Compliant Hardware time stamping provides precision clock

10/100 Ethernet MAC synchronization for real-time industrial control, AMD Magic
(K50, K60, K70 families) Wake-Up Pack [wake-up source for AWIC]
USB host/device/OTG DCD (Device Charge Detect) optimizes charging current/time

(FS/LS) Controller extending battery life, Low voltage regulator supplies 120mA at
(K20, K40, K60, K70 families) 3.3V for powering ext. components from 5V input
USB host/device/OTG USB LS/FS Device/Host/OTG 2.0 complaint with internal PHY
(HS) Controller and USB HS Device/Host/OTG 2.0 compliant with up to
(K20, K60, K70 families) 480Mbps with external ULPI PHY
CAN, UART (ISO7816), Multiple comms. interfaces for simple and efficient data
DSPI, IIC, IIS exchange supported by eDAM, industrial network bridging and
(All Kinetis families) audio interfacing
Carrier Modulator Transmitter

Infra Red waveform generation for remote control applications
(All Kinetis Families)
www.freescale.com/MQX [= FREE RTOS, RTCS, .... ]

TM
Feature Summary: Mixed Signal (Analogue)
Fast, accurate signal conditioning, configurable resolution,

16-bit ADC
sample time, avaraging, self calibration, level/compare mode,
(All Kinetis families) speed and power (8/10/12/16-bit)
12-bit DAC Analog signal generation (DMA and buffer support) for audio
(All Kinetis families) applications
Comparator Fast, accurate motor over-current protection with internal 6-bit

(All Kinetis families) DAC, band gap and external or internal voltage reference
Programmable Gain Amplifier

x64 gain for small amplitude signal boost
(All Kinetis families)
Analog Voltage Reference Accurate on-chip Vref eliminates need for external Vref -
(All Kinetis families) reduced system cost
Input / output, combine, pulse measurement, PWM functions;

FlexTimer [PIT & LPT]
double buffered, fault detect & dead time, Quadrature encoder,
(All Kinetis Families) self test, DMA trigger, gloabel time base [8ch, 2ch, 2ch]
TM
Feature Summary: Security
Flash Security 4-level protection limits access to flash resources

(All Kinetis families) safeguarding user’s IP
Memory Protection Unit

Data protection and increased software reliability
(All Kinetis families)
DryIce & Tamper Detection Voltage, frequency, temperature & external sensing for
(K60, K70 families) physical attack detection, independent VBAT & EXTAL32
Cryptographic Acceleration
Faster than s/ware implementations with only minimal CPU
Unit intervention Wide variety of algorithms supported
(K50, K60, K70 families)
Validation of memory contents and communication data for
H/w Cyclic Redundancy Check
enhanced system integrity [initial seed and polynomial,
(All Kinetis families) transpose and final XOR]
TM
Feature Summary: External Interfaces
FlexBus Connection of ext. memories & peripherals e.g. graphics

(All Kinetis families) displays. Supports up to 6 chip selects [no additional BOM]
DRAM Controller
Connection of DDR, DDR2 and low-power DDR memories
(K60, K70 families)
Connection of up to 32-bit ECC current & future NAND types

NAND Flash Controller
ECC management handled in h/ware – minimizes s/ware
(K10, K20, K60, K70 families) overhead
Secure Digital Host Controller Connection of SD, SDIO, MMC or CE-ATA cards for in-
(All Kinetis families) application software upgrades, media files or Wi-Fi support
TM
Enablement & Ecosystem
Development Tools & Hardware, 3rd Parties
TM
Choose Your Partner: The Freescale MCU Ecosystem
Run-Time Software: RTOS, Stacks, File System
ARM® Cortex™ Microcontroller Software Interface Standard - hardware abstraction layer
HW BDM Debugger/Emulators IDE: Tools Compliers, Debuggers
GNU Tools
MQX Support / Audio/Video GUI Security / EVBs & System Ind. Protocol
Design Services Codecs Graphical Medical Design Stacks
eGUI
TM
Cortex-M4 Math and DSP Libraries
Free ARM Cortex-M4 Math & DSP libraries
 CodeWarrior, IAR, Keil, and CMSIS C callable and operating system independent functions
 Functions optimized for ARM Cortex-M4 using compiler intrinsics for DSP/SIMD instructions
 Separate functions for 8-bit, 16-bit, 32-bit integers and 32-bit floating-point values
 Supports many math and DSP functions:
Vector Math
 Absolute value
Filtering  Add (element by element)
 Biquad cascade direct form 1 (IIR)  Vector dot product
 Convolution  Multiply elements
 Partial convolution  Invert sign (negate)
 FIR (transversal) filter  Add constant offset
 Polyphase FIR decimator  Scale by constant
 Polyphase FIR interpolator  Shift left/right
 LMS adaptive filter  Subtract (element by element)
 Normalized LMS adaptive filter Fast Math
 Sparse FIR filter  Sine, Cosine, Square root
 Correlation Interpolation (linear and bilinear)
 64-bit high precision biquad filters Complex Math
 FIR lattice filters  Complex conjugate
 Direct form 2 transposed IIR filter  Complex magnitude
 IIR lattice filters  Complex magnitude squared
Transforms  Complex by complex multiplication
 Complex forward FFT  Complex by real multiplication
 Real FFT  Complex dot product
 Inverse real FFT Statistics
 Discrete cosine transform  Maximum / minimum value
 Inverse discrete cosine transform  Mean
Matrix addition, subtraction, transpose, scaling, inversion  Power
Controller  Root mean square (RMS)
 PID controller  Standard Deviation
 Field oriented control (clarke and park transforms)  Variance
TM
Kinetis Enablement
Freescale MQX + MCU + Tower System + CodeWarrior IDE
Free MQX RTOS
MQX Core
PSP & BSP
+  Modular, expandable and cost-effective

development platform for 8/16/32-bit  Eclipse environment
MCUs and MPUs  Processor Expert code
 Full-featured, scalable, proven RTOS  Rapid eval and prototyping with generation wizard
 Simplifies HW management, streamlines maximum HW reuse.  Build, debug and flash tools
SW development  Supported by a diverse range of MCU  Software analysis
 Reduces development costs while and peripheral plug-in boards and a  Kernel-aware debug
speeding time to market growing web community  Host platform support
Comprehensive solution for Open source hardware platform for Visual and automated framework to
embedded control and connectivity prototyping application development accelerate development time
One-stop-shop for silicon, IDE & RTOS

TM
The Freescale Tower System
A modular development platform
for 8/16/32-bit MCUs & MPUs
• Quickly combine Tower Modules to build a
prototype of your application
• Modules sold individually or in kits
• Open Source: Build your own Tower Module TWR-MEM TWR-LCD TWR-SENSOR-PAK
to integrate your IP
• Cost-optimized hardware
• Software support from Freescale and Third
Parties MCU/MPU Module:
• Tower controller board
• Growing community of Third Party hardware • Standalone or in Tower System
support Primary
Elevator
• On-line community: www.towergeeks.org
Part Number Contents SRP
TWR-K40X256 TWR-K40X256 module $69
TWR-K40X256 module
TWR-K40X256-KIT TWR-ELEV module $139
TWR-SER module Board
Connectors
TWR-K60N512 TWR-K60N512 module $69 Secondary
Peripheral Module: Elevator
TWR-K60N512 module • Up to 3 per system: Serial,
TWR-K60N512-KIT TWR-ELEV module $139 Memory, LCD,..
TWR-SER module • Mix & match with different
MCU modules
TM
Top Level Agenda
Top Level Agenda
► Welcome and Introductions

► Q&A, Close
TM
and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 30
Kinetis System Architecture
TM
System Agenda
► Cortex M4 Overview
► Kinetis System Architecture
► Flash Performance
► FlexMemory
► Low Power Modes
TM
TM
Cortex M4 is fully compatible with Cortex M3
and adds :
•DSP & SIMD instructions
•Optional s.p. Floating Point
TM
DSP Library Performance ( CMSIS 2.0 )
•Cortex-M4 SIMD + FPU
•Fix point: ~2x faster
•Floating point: ~10x faster
DSP Library Benchmark: Cortex-M3 vs. Cortex-M4
- 35%
- 70%
- 75%
- 69%
- 91%
158,878
13,619
8,819
2,244
8,596
2,462
8,310
2,462
41
27
FIR q15 PID q15 IIR q31 Matrix Mul Correlation

fixed point fixed point fixed point fixed point floating point
Cycles: smaller numbers are Cortex-M3 Cortex-M4 Memory Access
better Cycles
TM
TM
Bus Structure
Core
SRAM Cache AHB Masters
Bus Fabric
AHB Slaves
Flash
IPS Slaves
TM
All access to
SRAM is via
the MPU
MPU
TM
Architecture of devices available today
No SP FPU
100MHz
No Cache
100
MHz Up to 512kB
No NFC
No LCDC
No SDRAM
No DryICE
4K EERAM
4 Kbyte
EERAM
Up to
512k
bytes
TM
System Agenda
► FlexMemory
► Low Power Modes
TM
Kinetis: Flash Performance
TM
Clock Domains (100 MHz)
Platform
100 MHz
50 MHz
Flash
25 MHz IPS Peripherals
50 MHz
TM
Flash Memory Controller
►Flash System Architecture

• “Dual Bank, x64 Flash Memory”
• “Consecutive x32, word aligned reads with no wait states”
• FMC effectively reads 128bit records from flash each access
TM
System Agenda
► FlexMemory
► Low Power Modes
TM
Flex Memory
TM
What is FlexMemory?
• FlexMemory is a memory block that

can be configured as EEPROM and/or Firmware
flash memory
• Combination of TFS flash array
(FlexNVM) + SRAM block (FlexRAM) +
hardware state machine. Main Program
Memory
Memory
• Fully embedded in the MCU – Interface &
XBS
avoids software complexity and Control Logic
eliminates system resource
impact on CPU/flash/RAM of
EEPROM emulation schemes
FlexMemory
FlexRAM
• Can be accessed FlexNVM
simultaneously with the main
program memory Firmware
• Can be used for storing

additional application program
code, data tables or byte
write/erase system data
TM
Feature list [1]
P-Flash (Program Flash)
 256 Kbytes of P-Flash memory composed of one logical 256 Kbyte

Flash block divided into 128 sectors of 2 Kbytes
 P-Flash protection scheme prevents accidental program or erase of
stored data
 Automated, built-in, program and erase algorithms with verify
 Section programming for faster bulk programming times
 Read access to P-Flash memory possible while programming or erasing
data in the D-Flash memory or EERAM
TM
Feature list [2]
D-Flash (Data Flash)
 Up to 256 Kbytes of D-Flash memory with 2 Kbyte sectors

 D-Flash protection scheme prevents accidental program or erase of
stored data
 Automated, built-in program and erase algorithms with verify
 Section programming for faster bulk programming times
 Read access to D-Flash memory possible while programming or erasing
data in the P-Flash memory
TM
Feature list [3]
EERAM
Up to 4 Kbytes of EERAM configured for EEE or traditional RAM operations

 When configured for EEE (EEPROM Emulation):
 EERAM protection scheme prevents accidental program or erase of data
 Built-in hardware emulation scheme to automate EEE record maintenance
 Programmable EEE Data Set Size and D/E-Flash Partition Code allows EEE
memory endurance trade-offs
 Supports EERAM aligned writes of 1, 2, or 4 bytes at a time
 Read access to EERAM possible while programming or erasing data in the
P-Flash or D-Flash memory
 When configured as Traditional RAM
 Read and write access possible to the EERAM while programming or
erasing data in the P-Flash or D-Flash memory
TM
FTFL Commands
Supported Embedded Commands:
 Read 1s Block  Program Once

 Read 1s Section  Erase All Blocks
 Verify Backdoor Access Key
 Program Check
 Program Partition
 Read Resource
 Set EERAM Function
 Program Longword
 Erase Flash Block
 Erase Flash Sector
 Program Section
 Read 1s All Blocks
 Read Once
The address of FCCOBn registers are not in normal sequence
(3,2,1,0,7,6,5,4,B,A,9,8)
TM
Useful Information
► Program flash is guaranteed to minimum 10K cycles over full operating

specification
Parameter Min Typ Max

Tacc at Full Power 28 ns
Tacc at Low Power 800 ns[1]
Twakeup from VLLS mode 4 us
Twakeup from POR 20 us
Tpgm 50 us 75 us 500 us
Terase 2 ms 5 ms 200 ms
TM
System Agenda
► FlexMemory
► Low Power Modes
TM
Kinetis – Low Power Modes & Wakeup
Modes, NVIC, AWIC, LLWU
TM
Power Modes, Current & Wake-Up Times
Typical
Recovery
Time: IDD:
Starting @
<200uA/MHz
4us
4us
4us
4us 12uA
35us 6uA
35us 4uA
100us 2uA
+ EE restore
TM
Power Modes: Definition
Mode Definition
Run MCU can be run at full speed.
Wait Allows peripherals to function, while CPU goes to sleep reducing power consumption.
CPU and peripheral clock maximum frequency is restricted. CPU/Platform clock
VLP Run
is restricted to 2MHz. Flash access is restricted to 1MHz. LVD is off.
VLP Wait Similar to VLP Run, with CPU in sleep to further reduce power.
Stop MCU is in static state. Lowest power mode that retains all registers while maintaining LVD protection.
MCU is in static state with LVD operation off. Lowest power mode with
VLP Stop
ADC, LPT, RTC, LCD, CMP, DAC, and PIN interrupts functional.
MCU is in low leakage state retention power mode. LLWU controls wakeup sources
LL Stop
including LPT, RTC, LCD, CMP, DAC and select PIN interrupts.
Powering down most internal logic. All system RAM contents are retained and I/O states held.
VLL Stop 3
LLWU controls wakeup sources (up to 16 GPIOs, LPT, RTC, LCD, CMP, and DAC)
VLL Stop 2 Similar to VLL Stop 3, partial system RAM retention. FlexRAM contents can optionally be retained.
VLL Stop 1 Similar to VLL Stop 3, with only 32 byte register file retention.
NOTE: The WFI instruction invoke both wait and stop modes. The MCU exits the low-power mode via an interrupt
TM
Top Level Agenda
Top Level Agenda

► Q&A, Close
TM
Kinetis Peripherals Overview
TM
Peripherals Overview - Agenda
Section 1: Communications Peripherals
UART , DSPI , I2C, FlexCAN , USB , Ethernet , SSI
Section 2: Analog Peripherals
ADC & PGA , DAC , Vref , HSCMP
Section 3: Timers
PDB , FlexTimer, CMT, LPT, PIT, Watchdog & EWM,
RTC
Section 4: HMI
TSI , sLCD
Section 5: Security & Integrity
CRC, CAU, RNG, RTC
Section 6: Memory Interfaces
FlexBus, eSDHC, NAND- CTRL, DRAM-CTRL
Section 6: Programming & Debugging
TM
Pin Muxing: Alternate functions
•Some pins have fixed ( power or analog ) function :
Vdd,Vss,Vdda,Vssa, Vrefh,Vrefl, VREF_OUT, USB_DP/DM, DACx_OUT,
Extal32 , Xtal32, Vbat, Reset, Vout33, Vregin, some differential and single
ended ADC inputs
e.g.
DAC output
RTC crystal and
battery
.
•BUT most pins have several “Alternate” functions – up to 8 !
TM
PORT Module: Port Control Register
Every pin has a dedicated (32-bit) PCR register.
e.g. On K60 144bga ball“A3” corresponding to PORTD bit 5 (PTD5 ) has

PORTD_PCR5 register associated, where we can get/set for that pin only :
1. Interrupt flag (w1c )

2. Interrupt configuration : int/dma, edge/level, low/high, rising/falling/both
3. Mux control : can select Disabled (analog) or Alternate function Alt1 -> Alt7
4. Drive Strength low/high
5. Open drain yes/no
6. Slew Rate : fast/slow
7. Pull Resistor Enable : yes/no, pull-up or pull-down
8. Passive filter enable : optional passive lowpass filter (10-30MHz BW )
PCR settings are always in effect – regardless of what module is

connected to the pin
Note : a lock bit in each PCR register can make it read-only until next reset
TM
Section 1 – Communications Peripherals
TM
Part 1 of 7 - UART
It is not “Just a UART”:

• It is 6 UARTs on 144pin packages
• All 6 UARTs support LIN
• All 6 UARTs support IrDA
• Check routing in SIM; only UART0 &, UART1 <-> CMP
Modified IP : MCF51AG128 • UART0 supports ISO7816 (SIM, smartcards)
• At 100MHz:
• UART0 /1– 6.25 Mbits/s
• UART2-5 – 3.13 Mbits/s
• Reduced CPU Loading

• Rx, Tx from UART can assert DMA request
• UART0, UART1 have 8-entry Rx, Tx FIFOs
• All UARTs have optional RTS, CTS
• UART2-5 have double-buffered registers
• Address-Match feature
• Low Power enablement
• Muxed to several alternate ports

• e.g. UART0 available on 4 ports for 144pin package
TM
Part 2 of 7 – DSPI [1]
DSPI = “DMA” Serial Peripheral Bus:
Re-use IP : A 3-wire, full duplex synchronous bus

MCF532x/7x, MCF5445x,
• 3 SPIs on 144pin packages
others • Master and Slave Modes
• Very Fast
• Max Master speed is fBUS/2 , 25MHz
• Max Slave speed is fBUS/4 , 12.5 MHz
• FIFO Architecture
• 4-entry Transmit FIFO
• 4-entry Receive FIFO
• DMA Capable “Queued Mode”

• Command Buffer in system RAM
• “Tx FIFO not full” DMA trigger
• “Rx FIFO not empty” DMA trigger
• Up to 6 Peripheral Chip Selects

• Can be expanded with external mux

• e.g. DSPI0 available on 3 ports for 144pin package
TM
Part 3 of 7 - I2C
Standard I2C Features, of course:

• Multi-master operation
• 7-bit address or 10-bit address extension
Modified IP : MCF51AG128 • Software-selectable acknowledge bit
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode
switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and
detection
• Repeated START signal generation and
detection
• Acknowledge bit generation and detection

• e.g. I2C0 available on 3 ports for 144pin package
TM
Part 4 of 7 – FlexCAN
Compliant to CAN protocol Ver 2.0B

• Standard data and remote frames
Modified IP: MCF52xx
• Extended data and remote frames
“FlexCAN3”
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mb/sec
• Content-related addressing
Flexible Mailboxes Architecture
• 16 mailboxes
• Zero to eight bytes data length
• Each configurable as Rx or Tx
• Individual Rx Mask Registers per Mailbox
• Full featured Rx FIFO with storage capacity
for up to 6 frames and automatic internal
pointer handling
Idle Start-of-Frame Identifier Control Data CRC ACK End-of-Frame Interframe Space Idle
TM
Part 4 of 7 – FlexCAN [2]
New Features
• Extended ID Filtering
• Safe mechanism for ID filter re-configuration
• Match incoming IDs against:
• 128 extended IDs, or 256 standard IDs or
• 512 partial IDs, with up to 32 individual masking capability
• Flexible Mailboxes
• Rx Mailboxes can be configured with the same acceptance criteria
• Reception Queue
• Allows the CPU more time to service received messages
• Selectable priority of message reception between Mailbox and Rx FIFO
Idle Start-of-Frame Identifier Control Data CRC ACK End-of-Frame Interframe Space Idle
TM
Part 5 of 7 - USB
USB-oriented Modules:
Re-use IP: USB ecosystem is an integration of three modules:
MCF5225x, MCF51JM
• On chip voltage regulator
• Device charger detection module (DCD)
• Full-speed USB 2.0 dual-role module (Host / device)
3.3v
Voltage
regulator
VBUS
D+
D-
USB
GND
DCD
TM
Part 5 of 7 – USB [2]
On chip voltage regulator
USB voltage regulator is independent of the MCU NEW IP
Enabled even if the MCU is not powered. 5v USB voltage input
• 3.3v output @ 120mA • Drop-out is 300mV

• Output pin: Vreg33 • Modes:
• Can supply MCU • Run (120uA)
• Standby (1uA)
• Shutdown
TM
USB Engine
Main Features Re-use IP:
MCF5225x, MCF51JM
• Full-speed USB 2.0 Compliant
• Dual Role Operation – Host/Device
• 16-off, double-buffered, bidirectional endpoints
• Onchip USB full-speed PHY
• Low Power Operation
• Integrated with DCD Module
Only 2 pins to Remember! VBUS

• D+ USB0_DP D+
D- USB
• D- USB0_DM GND
• Both shared with DCD Block DCD
• Dedicated, so no pin muxing required.
TM
Device Charger Detection DCD NEW

NEW IP IP
Background:
• USB Battery Charger Spec Rev 1.1 Compliant

• I am a USB Device, Full Speed USB2.0
• I have a rechargeable battery
• I want to know if the host into which I am plugged can
provide sufficient charging current
• Negotiated during device attachment

• D+ and D- sink/source currents, detected by DCD module
• Charger Port Detection
• Charger Type Detection
• About 40ms after D-pin connect debounce.
TM
Part 6 of 7 - Ethernet
Ethernet Module “MAC-NET” ( 10/100 MAC )
Modified IP: MCF5441x ► Supports legacy FEC buffer descriptors

► compatible with FEC used on ColdFire
► Supports MII and RMII interfaces
► IEEE1588
► Implements a hardware acceleration block
► For IP, TCP, UDP and ICMP protocol services
► Supports AMD magic packet detection with interrupt
to wake up MCU from low power mode
TM
Part 7 of 7 - SSI
Synchronous Serial Interface:

A full duplex synchronous bus, typically for audio
Re-use IP:
MCF532x/7x, MCF5445x, • 1 SSI on 144pin packages
others • Supports a variety of formats:
• AC97
• I2S
• „Normal‟ Modes
• Synchronous, also Gate Clock mode
• Asynchronous
• Network (TDM) Mode
• FIFO Architecture
• Dual 15-entry, 32-bit Transmit FIFOs
• Dual 15-entry 32-bit Receive FIFOs
• DMA Capable
• “Tx FIFOn empty” DMA trigger
• “Rx FIFOn full” DMA trigger

• SSI available on 3 ports for 144pin package
TM
Section 2 – Analog Peripherals
TM
Part 1 of 4 – ADC16
 SAR architecture with up to 16-bit resolution
• Up to 4 pairs of differential and 24 single-ended external

analog inputs + various internal channels
• Single or continuous conversion (automatic return to idle after
single conversion)
• Configurable sample time and conversion speed/power
• Input clock selectable from up to four sources
• Operation in low power modes
• Asynchronous clock source for lower noise operation
• Selectable hardware conversion trigger with hardware
channel select
• Automatic compare with interrupt for less-than, greater-than
or equal-to, within range , or out-of-range, programmable
value
• Temperature sensor
• Hardware average function
• Selectable voltage reference: external or alternate
• Self-calibration mode
• Programmable Gain Amplifier (PGA) with up to x64 gain
Two independent ADC blocks
available in current silicon
TM
12 bit DAC – Overview & Features Part 2 of 4 – DAC12
• Low power, general purpose 12 bit dac
DAC & buffer
• Two blocks available on current devices
• 16 word FIFO with hw or sw triggering,
and configurable watermark.
• Selectable reference voltage
• Output available on-chip and off-chip
• Interrupt or DMA request generation
• Mantains static voltage output
in Stop modes.
• Operational range : Vdd = 1.71 to 3.6V
Vref.= 1.15V to 3.6V
• 16 word FIFO can be triggered form

programmable PDB update pulses and
can update the output word pointer in 3
modes :
• Circular Buffer mode
• Swing (Up-Down) mode 16 word FIFO
• One Time Scan mode
TM
Part 3 of 4 – VREF
Adds to PMC bandgap reference , but with higher performance
and more features
►Features
• 1.20 V nominal output ( Factory
Trimmed )
• Tight regulation mode for external
use
• < 33ppm/ºC temp variation
 In critical 0-50 C° temp range
•VREF module connects to :

1. dedicated VREF_OUT pin ( only in tight regulation mode )
2. DAC ( as voltage reference input )
3. ADC ( as reference and channel input )
4. HSCMP 0,1 .
Static in LLS, off in VLLSx, functional in all other modes

TM
Part 4 of 4 – HSCMP
► Comparator Features:
• operation over entire supply
range and rail-to-rail inputs
• optional output to MCU pin for all
comparators
• configurable rising and falling
edge interrupts
• option to generate DMA request
• wake-up source for all MCU low-
power modes
• operation in continuous,
sampled, or windowed modes
• programmable filter to change
output state only when
consecutive samples agree
• four software-controlled levels of
hysteresis
TM
Section 3 - Timers
LPT
CAU
TM
Part 1 of 7 - PDB
PDB functionality
The purpose of PDB (Programmable Delay Block ) is to

synchronize by means of hw the activity of certain
peripherals, by generating :
 programmable delays between input triggers and

output triggers
 periodical output triggers
► output triggers from PDB are available to : ADC16, DAC12,

HSCMPx
► input triggers can be sourced to PDB from : external pin,

CMP, PIT, FTM, RTC, LPT, software
TM
Part 2 of 7 - FlexTimer
Timing & Control / PWM - Overview

 Up to 3 FlexTimer with 2ch, 2ch and 8ch [ main user registers are buffered ]
 Support for motor control , power management, and digital lighting solutions
 FTM is based/backwards compatible with HC9S08 TPM but with several key enhancements
[ signed up counter, deadtime insertion, fault inputs, enhanced triggering function, initialization and polarity ]
 16bit (un)signed counter [ divide-by 1,2,3,8,16,32,64, or 128 ]
• Free-running or with initial and final value
• Up or up-down counting
 Clock Options:
• Bus Clock [default]
• FFCLK [Fixed Frequency Clock] NOTE
[ 1/2 of system clock frequency ] The FTM1 and FTM2 configuration differs from the FTM0 configuration by reduced
number of channels and by adding support for quadrature decoder mode.
• EXTCLK [External Clock Path]
[ 2 Pins, 1/4 of system clock ]
• Global Time Base
[ Synchronization of FTM modules (two ore more) ]
 Multiple sources of interrupts [ OR'd together ]
TM
Part 3 of 7 - CMT
Feature Overview Carrier Modulation Transmitter
 Provides means to generate the protocol timing
and carrier signals for encoding schemes
 Incorporates hardware to off-load the critical
and/or lengthy timing requirements
 Support Interrupt and DMA request
[ i.e. interrupt on end of cycle ]
 Modulator disabled allow infrared output use
 Modes of operation:
• Time with independent control of high/low times
[ Modulator can gate the carrier onto the modulator output ]
• Baseband
[ Modulator can control the logic level of the modulator output ]
• Frequency shift key (FSK)
[ Modulator can count carrier periods and instruct the carrier generator to alternate
between two carrier frequencies whenever a modulation period (mark + space counts) ]
• Direct software control of CMT_IRO pin [ infrared output ]
• Extended space operation in time, baseband, and FSK modes
[ Extended Space Operation can be used to emulate a zero mark event ]
TM
Part 4 of 7 - LPT
Feature Overview Low-Power Timer

 16bit free-running counter
• Reset on compare
• Pulse counter with compare
• Input pins and rising or falling edge
• CMP output used in pulse counter mode
 Interrupt and HW trigger on Timer Compare
 Modes [ across all power modes ]:
 Pulse Counter, with glitch filter is bypassed / enabled
[ glitch filter clock sources are 1kHz LPO, EXTAL, EXTAL32, IRC ]
 Time Counter, with presacle bypassed / enabled
[ increment 22.....216 ]
 Continue operating through most system reset events
• The LPT is reset only on global POR or LVD
• AWIC and LLWU Wake-up Source
TM
Part 5 of 7 - PIT
Feature Overview
Periodic Interrupt Timer
 4 x 32bit timers [ system clock source ]
• Stopping and Starting
• Modifying Running Timer Period
• Dynamically Setting a New Load Value [without restarting] DMA transfer Ch0 ... Ch3
 Independent timeout periodes for each timer
• Generate triggers at periodic intervals
[ timer reaches '0' ]
Provide an automatic mechanism to

• Generate DMA trigger pulses transmit bytes, frames or packets at
fixed intervals without the need for
processor intervention.
• Generate maskable Interrupts
Seperate Vectors PIT Ch0...Ch3
• Counter values (current state) could be read
 Functional in RUN and VLPR mode
TM
Part 6 of 7 - COP & EWM
Computer Operating Properly & External Watchdog Monitor
Feature Overview - Watchdog (COP)
 Independent-clocked Watchdog
[ monitors the operation of the system by expecting periodic refreshing ]
 Programmable Timeout Period and Window Refresh Option
 Unlock sequence for allowing updating of configuration registers
[ within 256 clock cycles being unlocked, need update after unlocking, otherwise it resets the system ]
 Ability to TESET Watchdog [ Timer and RESET ]
• Quick Test: Small timeout value programmed
• Byte Test: Individual bytes of timer tested
• Read-Test: Read-only access to read/check WDOG counter value
 Fully Functional in RUN, STOP, VLPR, VLPW, VLPS
Feature Overview - EWM

 8bit ripple counter
 Redundant Watchdog, monitors external circuits
 EWM does not reset the MCU
 EWM_IN Pin: Allows an external circuit to control the EWM_OUT
 EWM_OUT Pin: When asserted is used to reset or place the external circuit into safe mode
TM
Part 7 of 7 - RTC
Real Time Clock
Feature Overview
 32bit monotonic counter
 32bit Alarm [ invalidated on DryIce tamper detect &
alarm/interrupt at a predefined time ]
 16bit prescaler with compensation
[ can correct errors between 0.12 … 3906 ppm ]
 Independent Battery Power Supply
[ VBAT, supply RTC & VBAT-Register ]
 Independent 32.768kHz OSC [EXTAL32]
 Automatic Gain Control
[ optimize power consumption ]
 Alarm Pin [ optional, not on all devices ]
 Register write protection
 Fully functional in all modes
EXTAL32 can be used as main

oscillator source (cost reduction)
[ AWIC and LLWU Wake-up Source ]
TM
Section 4 – HMI Peripherals
sLCD
TM
Part 1 of 2 - TSI
► 16 input capacitive touch sensing pins

• Wide measuring capacitance range ( 1- 500pF )
• Each with individual result registers – 16 bit resolution
• Automatic detection of Electrode Capacitance Change with programmable upper and
lower threshold (for each electrode)
► Capacitive touch sensing detection across all power modes

• Automatic periodic scan or software triggered single scan of selected pins
• Configurable resolution / scan speed
► TSI low power mode

• Module can scan a single electrode in any VLLSx low power mode and wake-up MCU on
touch detection
• Low power mode current adder can be <1uA
TM
Part 1 of 2 – TSI [2]
TSI block diagram Measures a single capacitance
Generates the electrode

scan sequence
Takes the decision on
each measurement
TM
Part 2 of 2 - sLCD
 Available on all K30 and K40 devices and some future K50 devices
 Connects LCD glasses with static drive or up to 1/8 duty cycle –>
Fewer pins required to drive LCD segments (up to 320 )
 48 pins required for 320 segments in 8x40 mode

 Low power blinking mode
 Programmable blink modes and frequency in all low power modes

 Can alternate two patterns on LCD ( in 4x mode or less ) or blank entire LCD
periodically
 Internal charge pump provides all voltages required to power up LCD

glass at 3 or 5 volts
 Internal software selectable regulated power supply that keeps constant voltage
across LCD glass to avoid degradation
 kinetis sLCD offers 4 bits resolution trim to digitally adjust contrast control
TM
Part 2 of 2 – sLCD [2]
 Segment fault detection capability

 Hardware support for segment LCD display errors
 Front and back plane assignment

 FP and BP can be software selectable to be either FP or BP, making board layout an
 easier task and very flexible for changes
 BackPlane re-assignment
 Assist in vertical scrolling on dot-matrix displays
 LCD waveforms functional in all low-power modes

 Allow the LCD to work in any low power mode
 LCD registers are only initialized after Power on Reset.

 For low power modes reduce the time to initialize the code.
TM
Section 5: Security & Integrity
LPT
CAU
TM
Security & Integrity
RNGB, MMCAU & CRC

 Pseudo-Random Number Generator (RNGB)
 Memory-Mapped Cryptographic Acceleration Unit (CAU)
 Hardware Cycle Redundancy Check Generator support 16bit & 32bit (CRC)
DEFAULT
TM
AN3795 Document show CRC Module can be used to check in-application Part 1 of 3 - CRC
SOFTWARE for corruption and verify DATA integrity.
Cyclical Redundancy Check

Feature Overview
 The 16/32-bit code is calculated for 32-bit of data at a time
 Programmable initial seed value and polynomial
 Optional 'Final XOR' with 0xFFFFFFFF or 0xFFFF
 Support transpose register
[ required for certain CRC standards ]
• Input data
• CRC result
• Transpose types are
 No Transposition
 Bits in bytes are transposed, bytes are not transposed
 Both bits in bytes and bytes are transposed
 Only bytes are transposed, no bits in a byte are transposed
TM
True Random Number Generator (TRNG)
Pseudo-Random Number generator (PRNG) Part 2 of 3 - RNG and CAU
Random Number Generator
Feature Overview - RNGB
Crypto Acceleration Unit
 Performs seed generation and
random number generation
 Use TRNG and PRNG to achieve true
randomness & cryptographic strength
 Self Test Mode
[ verify HW is functioning (~29,000 cycles) ]
Feature Overview - MMCAU

 Coprocessor, connected to Private Peripheral Bus (PPB).
Supports hardware implementation of a set of specialized
operations to improve throughput of SW based security
encryption or decryption operations and message digest functions.
 Acceleration of the DES, 3DES, AES, MD5, SHA-1 and SHA-256 algorithms.
Freescale provides an optimized, callable C-function library that provides the
appropriate software building blocks to implement higher-level security functions.
 Simple, flexible programming model and the ability to sent up to three commands in one data write operation
TM
Section 6 - Memory
DRAM* Interfaces
*256 pin only
LPT
CAU
TM
AN3854 NO inverter required [FB_A[0] to BHE/BLE]
NO additional external address lacth required Part 1 of 3 - FlexBus
Interface to (a)synchronous devices
[Flash, Smart LCDs, FPGAs, SRAM,
Feature Overview
PROM, EPROM, EEPROM]
 Designed to connect up to 6 external devices
[ 6 independent, user-programmable chip-selects ]
Package 144 104 100 81 80 64
 8-, 16-, and 32-bit port sizes with configuration Signals
Muxed
for multiplexed or non-multiplexed address mode
Non-muxed
and data buses [ with optional burst support ] mode
LCD
 Auto-acknowledge feature mode
• Primary and optional secondary wait state counter FlexBus Modes of Operation [ LCD devices ]
• Useful for interfacing to burst Package 144 104 100 81 80 64 48 32
Signals
• Data access time [if subsequent data's are faster]
Muxed
mode
 Programmable Non-muxed
mode
• Address-setup time with respect to the
LCD
assertion of chip select mode
• Address-hold time with respect to the FlexBus Modes of Operation [ non LCD devices ]
negation of chip select and transfer direction

TM
Part 2 of 3 - eSDHC
Enhanced Secure Digital Host Controller
Feature Overview
 Card bus clock frequency up to 50 MHz
 1bit / 4bit SD and SDIO modes
Up to 200Mbps of data transfer (using 4 parallel data lines)
 1bit / 4bit / 8bit MMC modes
Up to 416Mbps of data transfer (using 8 parallel data lines, single data rate mode)
 1bit / 4bit / 8bit CE-ATA devices
 Single Block, Multi Block read and write
 Block sizes of 1 ~ 4096 bytes
SD MMC CE-ATA SD/SDIO

SD/SDIO
Identification Mode CE-ATA 1-bit
SD 1bit MMC 1bit full speed mode
(up to 400 kHz)
(up to 25 MHz)
SD/SDIO
MMC full speed mode
SD 4bit MMC 4bit CE-ATA 4-bit high speed mode
(up to 20 MHz)
(up to 50 MHz)
MMC high speed mode
MMC 8bit CE-ATA 8-bit
(up to 52 MHz)
TM
Part 3 of 3 - NAND-CTRL, DRAM-CTRL
External Memory Interfaces - Summary
Feature Overview - DRAM Controller
 External Data Bus Interface: 8-bits / 16-bits
 Up to 125 MHz Clock and 250 MHz Data
 Supports: DDR, DDR2, LPDDR
 Fully asynchronous operation with an independent PLL.
 Supports burst of 16 bytes and 32 bytes
Robust timing recovery makes board routing easier !!!
Feature Overview - NAND Flash Controller

 NAND Flash Interface: 8-bits / 16-bits (shares FlexBus pins)
MLC NAND Flash:
 Supports all NAND Flash products (SLC & MLC) regardless of density / organization Multi-Level per Cell able to store
[ with page size of 512+16B/2K+64B/4K+128B/4K+218B/8K ] multi bits [cheaper due to higher
density]
 By-passable ECC mode, NFC supports 4/6/8/12/16/24/32 bits error correction
Opposed to SLC NAND Flash:
Single-Level per Cell
TM
Section 6 - Programming and
Debugging
Cortex-M4
Debug Topology
TM
Debugging
Debug Interface
4pin or 5pin JTAG [ IEEE 1149.1 ]
Debug in Low Power Modes
 JTAG_CLK
 JTAG_DO In low power modes in which the debug modules are kept
 JTAG_DI static or powered off, the debugger cannot gather any debug
 JTAG_MS data for the duration of the low power mode.
 JTAG_TRST
(optional JTAG Reset) In the case that the debugger is held static, the debug port
2pin cJTAG [ IEEE 1149.7 ] returns to full functionality as soon as the low power mode
 JTAG_CLK exits and the system returns to a state with active debug.
 JTAG_MS In the case that the debugger logic is powered off, the
2pin Serial Wire Debug (ARM SWD) debugger is reset on recovery and must be reconfigured
 SWD_CLK (available on JTAG_CLK pin) once the low power mode is exited.
 SWD_DIO (available on JTAG_MS pin)
ARM Real-Time Trace Interface
TM
Debugging
Flash Programming Methodes
Resident flash programming routines for firmware updates in the field via communication interfaces
TM
Top Level Agenda
Top Level Agenda

► Q&A, Close
TM
Exercises
TM
Top Level Agenda
Top Level Agenda

► Q&A, Close
TM
Top Level Agenda
Top Level Agenda

► Q&A, Close
TM
Q&A
TM
TM
TM

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Freescale Kinetis Seminar

ARM Cortex-M4 Microcontrollers

Gonzalo Delgado & Paolo Alcantara

► Freescale Kinetis Overview

Freescale Confidential and Proprietary

 The most scalable portfolio of low-power

 Innovative 90nm Thin-Film Storage

 Exceptional mixed-signal integration

 One of the most comprehensive ARM®

Freescale Confidential and Proprietary

32-bit Kinetis NEW!

ColdFire Application-oriented ultra-low power solutions with

Digital Signal Controllers Application-oriented solutions for automotive, motor

Scalable cost & power-optimized product families for

Giving customers an ideal solution regardless of architecture preference.

Freescale Confidential and Proprietary

More than 200 New 90nm

More than 240 new 90nm 32-bit

5V Capability Low Power Large, Measurement Precision Signal

Offers customers great solutions for a variety of applications.

Freescale Confidential and Proprietary

Freescale’s 90nm Thin Film Storage (TFS) flash memory

 Industry leading bit-level reliability through

Guaranteed Can exceed 10Mcycles

Write Voltage ≥ 2.0V ≥ 1.71V

TFS Value = reliability, lower power, EEPROM, scalability

4us 1.2uA - 7uA

35us 1uA - 5uA

35us 750nA - 2uA

Values subject to change

Run MCU can be run at full speed.

Freescale IP and Innovation

Freescale IP for Digital Signal Processing

Common Common Common

DIG / ANA I/O

DIG / ANA I/O + LCD

DIG / ANA I/O + LCD

K10  K30 & K20  K40 = Add Segment LCD

K20  K60 = Add Ethernet

Blink mode operation reduces power, Failure

Audio Interface (DSP + IIS) M4 core - fast/efficient processing, IIS - easy

IEEE 1588 Compliant Hardware time stamping provides precision clock

USB host/device/OTG DCD (Device Charge Detect) optimizes charging current/time

Carrier Modulator Transmitter

www.freescale.com/MQX [= FREE RTOS, RTCS, .... ]

Fast, accurate signal conditioning, configurable resolution,

Comparator Fast, accurate motor over-current protection with internal 6-bit

Programmable Gain Amplifier

Input / output, combine, pulse measurement, PWM functions;

Flash Security 4-level protection limits access to flash resources

Memory Protection Unit

FlexBus Connection of ext. memories & peripherals e.g. graphics

Connection of up to 32-bit ECC current & future NAND types

ARM® Cortex™ Microcontroller Software Interface Standard - hardware abstraction layer

HW BDM Debugger/Emulators IDE: Tools Compliers, Debuggers

+  Modular, expandable and cost-effective

One-stop-shop for silicon, IDE & RTOS

Part Number Contents SRP

TWR-K40X256 TWR-K40X256 module $69

► Welcome and Introductions

•DSP & SIMD instructions

•Optional s.p. Floating Point

FIR q15 PID q15 IIR q31 Matrix Mul Correlation

SRAM Cache AHB Masters