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Lecture 19
ADC Converters
• Sampling (continued)
– Sampling switch charge injection
• Complementary switch
• Use of dummy device
• Bottom-plate switching
– Track & hold circuits
– T/H circuit incorporating gain & offset cancellation
• ESD protection impact on converter performance
• ADC architectures
- Nyquist rate ADCs
- Oversampled ADCs
φ1B
VL
t
φ1
φ1B
• In slow clock case if area of n & p devices are equal Æ effect of overlap capacitor
for n & p devices to first order cancel (matching n & p width and ΔL)
1⎛Q Q ⎞
Δ Vo ≈ ⎜ c h − p − c h − n ⎟
2 ⎜⎝ Cs Cs ⎟⎠ VL
t
Vo = Vi (1 + ε ) + Vos
φ1
1 W C L + WpCo x Lp
ε ≈ − × n ox n
2 Cs
VL
t
φ1a M2
t
S2A φ1
φ1D
φ1D
φ1D φ2 S3 φ2
C
vIN
S1A S2 vOUT
S2A φ1D
φ1D
φ2
φ1D φ2 S3
C Charging C
vIN
S1A S2 vOUT
φ1 S1
vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 7
φ2
φ1D φ2 S3
C Holding
vIN
S1A S2 vOUT
φ1 S1
vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 8
Flip-Around T/H - Timing
φ2
φ1
S2A φ1D
φ1D
φ2
φ1D φ2 S3
C Sampling
vIN
S1A S2 vOUT
Charge Injection
• At the instant of sampling, some of the
charge stored in sampling switch S1 is
dumped onto C
• With "Bottom Plate Sampling", charge
injection comes only from S1 and is to
first-order independent of vIN
– Only a dc offset is added This dc offset can
be removed with a differential architecture
φ1D φ2 S3 φ2
C
vIN
S1A S2 vOUT
φ1 S1
vCM
EECS 247 Lecture 19: Data Converters © 2005 H.K. Page 11
Flip-Around T/H
• S1 is an n-channel MOSFET
• Since it always switches the same voltage, it’s on-
resistance, RS1, is signal-independent (to first order)
• Choosing RS1 >> RS1A minimizes the non-linear
component of R = RS1A+ RS1
– S1A is a wide (much lower resistance than S1) & constant
VGS switch
– In practice size of S1A is limited by the (nonlinear) S/D
capacitance that also adds distortion
– If S1A’s resistance is negligible Æ delay depends only on S1
resistance
– S1 resistance is independent of VIN Æ delay is independent
of VIN
S11
S12
φ1’
φ1
• Gain=1 φ2
• Feedback factor=1
• ΔVin-cm=Vout_com-Vsig_com
Æ Amplifier needs to have large input common-mode compliance
Ref: K. Vleugels et al, “A 2.5-V Sigma–Delta Modulator for Broadband Communications Applications “
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, pp. 1887
Input Common-Mode
Cancellation
• Gain=4C/C=4
• Feedback factor =1/(1+G)=0.2
• Input voltage common-mode level removed
• Amplifier offset not removed
Ref: S. H. Lewis, et al., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter” IEEE
JSSC, VOL. SC-22,NO. 6, DECEMBER 1987
Vout=gm1roVin1 + gm2roVin2
Ref: H. Ohara, et al., "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition
peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.
+
(V INAZ+ -VINAZ- )= -gm1/gm2 Voffset
-
Voffset
ESD Protection
ADC Architectures
[http://www.idt.com/docs/AN_123.pdf]
[http://www.ce-mag.com/archive/03/ARG/dunnihoo.html]
Ref: I. E. Opris, "Bootstrapped pad protection structure," IEEE J.Solid-State Circuits, pp. 300,
Feb. 1998
C(Vin)= 2......4pF
for Vin=2....0V
-60 -80
-80 -100
-100 -120
6 7 8 9 10 6 7 8 9 10
10 10 10 10 10 10 10 10 10 10
Input Frequency Input Frequency
ADC Architectures
• Slope Converters
• Successive approximation
• Flash
• Folding
• Time-interleaved / parallel converter
• Residue type ADCs
– Two-step
– Pipeline
– Algorithmic
– …
• Oversampled ADCs
VRamp
• Low complexity
Time
• Hard to generate precise ramp
• Better: Dual Slope, Multi-Slope
http://www.maxim-ic.com/appnotes.cfm/appnote_number/1041
Clock Y N
1Æ[MSB-1] VIN>VDAC? 0Æ[MSB-1]
..
..
Y N
1Æ[LSB] VIN>VDAC? 0Æ[LSB]
VDAC/VREF
VIN 1
1/2 3/4 5/8 11/16 21/32 41/64
VREF DAC
3/4
5/8
1/2 VIN
Control
Logic
Clock
Time / Clock Ticks
ADCÆ101000
VREF VIN
• B-bit flash ADC: fs
– DAC generates all
possible 2B -1 levels
– 2B-1 comparators
compare VIN to DAC
outputs D 2B-1ÆB
– Comparator output: A Encoder
Digital
Output
• If VDAC< VINÆ 0 C
• If VDAC > VINÆ1
– Comparator outputs form
thermometer code
– Encoder converts
thermometer to binary
code
0 B-bits
1 1
0
1
Encoder
1
1
Time
comparison
R
– Half cycleÆ 2B-1 to B
.. Digital
Encoder
encoding .. Output
.
• High complexity: R
2B-1 comparators
R
B-bits
R/2
• High capacitance @ input Thermometer
node code
Folding Converter
MSB
VIN
ADC
Digital
Output
LSB
ADC
Folding Circuit
• Extremely fast:
Digital Output
ADC
Digital output
up to (B1 + B2 + ... + Bk) Bits
Algorithmic ADC
Digital Output
Shift Register
& Correction Logic
start of conversion
Residue
VIN coarse
ADC DAC 2B T/H
(1 ... 6 Bit)
Digital
VIN Digital
H(z) Decimation
Output
Filter
DAC
16
1)
ximivaeti
B+
2 (0.4
14
ss
Resolution [Bit]
Su ce
Appcro
ple Bit
d~
12
am 1-
ers der
B
10 2
l~
Ov Or
ri a
Se
2 nd
0 0 1 2 3 4 5
10 10 10 10 10 10
Clock Cycles per Conversion
[www.v-corp.com]