D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

VLSI Physical Design

• Logic level
• logic gates / logic equations
• nets / bits

• Physical level
• transistors / wires

• polygons

 Peeter Ellervee vlsi - physical level - 1

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Basic gates - NAND vs. NOR

TTL (Si) ECL (Si)

 Peeter Ellervee vlsi - physical level - 2

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Basic gates - NAND vs. NOR

CMOS (Si) DCFL (GaAs)

Direct-coupled FET

• Material properties
• mobility (Si) -- µn = 1250 cm2 / V sec & µp = 480 cm2 / V sec & R ~ µ-1

 Peeter Ellervee vlsi - physical level - 3

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Material properties

Properties Unit Si GaAs 4H-SiC Diamond

Electron mobility [ cm2/ V·s ] 1500 8500 1000 2200

Hole mobility [ cm2/ V·s ] 600 400 50 1600

Bandgap [ eV ] 1.1 1·43 2 2.7

Dielectric constant 11.8 12.5 9.7 5.5
Thermal conductivity [ W / cm ·°K ] 1.5 0.46 4.9 20
Saturation electron drift velocity [ x107 cm/s ] 1 1 2 2.7

Melting point [C] 1420 1238 2830 4000

Breakdown field [ x105 V/cm ] 3 6 30 100

 Peeter Ellervee vlsi - physical level - 4

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

CMOS Bipolar GaAs

Power dissipation (PDC) Low High Medium

Input impedance High Low High

Noise margin High Medium Low
Speed Medium High Very high
Packing density High Low High
Delay sensitivity to load High (o) Low (o) High (i/o)
Output drive Low High Low
Bidirectional Yes No Possible
Switching device Ideal Not ideal Reasonable
ft frequency Medium High Very high
(at low current)

Mask levels 12 to 16 12 to 20 6 to 10

 Peeter Ellervee vlsi - physical level - 5

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

CMOS - why NAND?

• Mobility -- gate
µn = 1250 cm2 / V sec & µp = 480 cm2 / V sec drain
w

• R ~ µ-1 & R ~ L w-1 (L-constant) source

L

Ronup R ~ µ-1 w-1

CL
wp ~ 3·wn (Rp=Rn)

Rp||Rp ~ Rn+Rn

Rondown CL
~CL· Ronup ~CL· Rondown Rp ~ 4·Rn (wp=wn)

 Peeter Ellervee vlsi - physical level - 6

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Very high speed

CMOS DCFL
VDD
LPw

LO
input ξ output

LGw CL RL
PDC = 0 i1 = IDD or i2 = IDD
PAC = CV2f PDC = PAC = VDDIDD LPCB

CMOS

DCFL
A B
Vth
Vaa’
A’ B’ Vbb’
frequency

 Peeter Ellervee vlsi - physical level - 7

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Process steps
• Mask 1 - deep p-well diffusions nMOS transistors
• Mask 2 - thinox regions
• Mask 3 - polysilicon for “gate wires”
• Mask 4 - p-diffusion pMOS transistors, p +-mask & mask 2
• Mask 5 - n-diffusion nMOS transistors, inverted p +-mask & mask 2
• Mask 6 - contact cuts
• Mask 7 - metal layer
• Mask 8 - overglass layer overall passivation, access to bonding pads

7
6
5
4
3
2
1

V DD V in Vout V SS

p
n

 Peeter Ellervee vlsi - physical level - 8

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Process steps - variations

• Lithography masks - positive & negative
• Transistor wells - p-well, n-well, twin-tub & silicon-on-insulator

VDD V in V o ut V SS

n -w e ll

n
p

VDD V in V ou t V SS

tw in -tu b

e p ita x ia l
n p la y e r

• “Educational Java Applets in Solid State Materials” - jas2.eng.buffalo.edu

 Peeter Ellervee vlsi - physical level - 9

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Layout rules

• Feature size - λ ( 2 µm, 0.8 µm, 0.13 µm, etc.)

• Layers - L1, ... , Lv

• Wire width - wi
• w1>2, wi>wi-1 wiλ siλ

• Wire separation - si
• s1=3, si≥si-1

• Contact rule - layers Li & Lj (i<j)

ejλ
• Layout grid
• siλ=svλ=λs, eiλ=evλ=λe --> λs+λe ajλ

 Peeter Ellervee vlsi - physical level - 10

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Layout environments

• Cell generation
• Programmable logic arrays (PLA)
• Transistor chaining
• Weinberger arrays & gate matrices

• Layout environments
• Standard cells
• Gate arrays Transistor chaining
• Sea-of-gates
• Field-Programmable Gate Arrays (FPGA)

 Peeter Ellervee vlsi - physical level - 11

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Layout methodologies

• Partitioning

• Floorplanning
• initial placement

• Placement
• fixed modules

• Global routing

• Detailed routing

• Layout optimization

• Layout verification

 Peeter Ellervee vlsi - physical level - 12

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Partitioning

• Weighted compatibility graph partitioning A C

• hypergraphs

• Constructive approaches B D
• hierarchical clustering

• Iterative improvements
3
• Kernighan-Lin heuristic
2

cut-lines
• Weights
1
• module size
• number of connections A B C D
• number of I/O-s

 Peeter Ellervee vlsi - physical level - 13

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Floorplanning
• Sliceable floorplan
• two slices
• templates

• Rectangular dual graph approach

• planar graph
• (Mi,Mj)∈E - modules are adjacent Mi, Mj

• Hierarchical approaches
• bottom-up approach
• top-down approach

• Soft-computational approaches
• simulated annealing
• genetic algorithms

 Peeter Ellervee vlsi - physical level - 14

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Placement
4
• Improvement of the initial floorplan
1 2
3

• Refined cost functions

3
• known ports 1 2
4

• Constructive heuristics 3
2
4

• Iterative heuristics 1

• Soft-computing 1
4
2
3

 Peeter Ellervee vlsi - physical level - 15

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Routing

4 3 2 3 4 5
• Maze running 9
9
8 9
9
9 8 9
3
2
2
1
1 2 3 4
1 2 3
5
4 5
9 8 7 8 9 8 7 8 9 3 2 1 2 3 4 5
• memory usage! 9 8 7 6 6 7 8 4 3 2 3 4
9 6 5 4 3 4 5 6 7 5 4 4 5 4 3 4 5
• bidirectional search 8 9 5 4 3 2 3 7 8 5 5 4 3 2 3
7 3 2 1 2 6 7 3 2 1 2
• minimum cost paths 6 5 4 3
7 6 5 4
2
3
1 1
2 1 2 3
5
4
6
5
5 4 3 2 1
5 4 3 2
1 5
1 2 3 4 5
8 7 6 5 4 3 2 3 4 5 6 5 4 3 2 3 4 5
• multilayer routing
• multiterminal routing

• Line searching
• track graph

 Peeter Ellervee vlsi - physical level - 16

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Routing

• Global routing
• dividing routing task into smaller sub-tasks
• routing channels

• Detailed routing
• routing inside channels

• Layout optimization
• channel compaction

 Peeter Ellervee vlsi - physical level - 17

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Delay modelling
w
• Delays in wires can not be neglected anymore!
l
h
• Cw = fr εox w l / tox Rw = ρ l / w h tox

• Standard unit of capacitance Cg -

R R
gate-to-channel capacitance having W=L=λ
C C
• 1.2 µm technology
Cg - 2.3 fF & τ - 46 ps distributed RC L-model

R/2 R/2 R

C C/2 C/2
• Elmore delay - TELM = ½RwCw + RwCL
T-model Π-model

 Peeter Ellervee vlsi - physical level - 18

 D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Delay modelling
w1_3 w1_4 n2
n2
w1_8
n1 n1 w1_7
w1 w1_2
n3
n3
w1_1
w1_5 w1_6

• Analog (Spice) models

• transmission line based models ~ distributed RC
• approximate models - L-model, Elmore delay

• Digital (VHDL) models

• wire segment == assignment with delay
• back-annotation -- layout -> VHDL model

w1_1 <= not n1 after gate_delay ps;

w1_2 <= w1_1 after delay_w1_1 ps;
. . .
w1_8 <= w1_7 after delay_w1_8 ps;
n3 <= not w1_8 after gate_delay ps;

 Peeter Ellervee vlsi - physical level - 19

D e p a r t m e n t o f C o m p u t e r E n g i n e e r i n g

Packaging
Packaging hierarchy
Crystal
1st level packaging
Multi-crystal-module / Chip
2nd level packaging
PCB
3rd level packaging
Mother-board
4th level packaging
Rack

Technology Decreased Increased

advances transistor size gain

Smaller delay More gates Larger crystal

Technology
requirements Higher Higher Lower Higher Higher

System Signal Clock Power

issues bandwidth frequency Noise dissipation I/O count

Packaging
constraints Lower Lower Higher Lower Lower

 Peeter Ellervee vlsi - physical level - 20