PIC12F508/509

Memory Programming Specification

This document includes the 1.2 Program/Verify Mode
programming specifications for the The Program/Verify mode for the PIC12F508/509
following devices: allows programming of user program memory, user ID
• PIC12F508 locations, backup OSCCAL location and the Configura-
tion Word.
• PIC12F509

Pin Diagrams
1.0 PROGRAMMING THE
PIC12F508/509 PDIP, SOIC, MSOP
The PIC12F508/509 is programmed using a serial
method. The Serial mode will allow the PIC12F508/509

PIC12F508/509
VDD 1 8 VSS
to be programmed while in the user’s system. This
allows for increased design flexibility. This GP5/OSC1/CLKIN 2 7 GP0/ICSPDAT
programming specification applies to PIC12F508/509 GP4/OSC2 3 6 GP1/ICSPCLK
devices in all packages. GP3/MCLR/VPP 4 5 GP2/T0CKI

1.1 Hardware Requirements

The PIC12F508/509 requires one power supply for
VDD (5.0V) and one for VPP (12V).

TABLE 1-1: PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F508/509

During Programming
Pin Name
Function Pin Type Pin Description
GP1 ICSPCLK I Clock input – Schmitt Trigger input
GP0 ICSPDAT I/O Data input/output – Schmitt Trigger input
MCLR/VPP Program/Verify mode P(1) Program Mode Select
VDD VDD P Power Supply
VSS VSS P Ground
Legend: I = Input, O = Output, P = Power
Note 1: In the PIC12F508/509, the programming high voltage is internally generated. To activate the Program/
Verify mode, high voltage of IIHH current capability (see Table 6-1) needs to be applied to the MCLR input.

 2004 Microchip Technology Inc. Preliminary DS41227D-page 1

PIC12F508/509
2.0 MEMORY MAPPING FIGURE 2-1: PIC12F508 PROGRAM
MEMORY MAP
2.1 User Program Memory Map 000h

User Memory
Space
The user memory space extends from (0x000-0x1FF) On-chip User 0FFh
Program Memory 100h
on the PIC12F508 and (0x000-0x3FF) on the
PIC12F509. In Program/Verify mode, the program
memory space extends from (0x000-0x3FF) for the 1FEh
PIC12F508 and (0x000-0x7FF) for the PIC12F509. Reset Vector 1FFh

Config Memory
The first half, (0x000-0x1FF) and (0x000-0x3FF) 200h
User ID Locations
respectively, is user program memory. The second half, 203h

Space
(0x200-0x3FF) and (0x400-0x7FF) respectively, is Backup OSCCAL value 204h
configuration memory. The PC will increment from 205h
(0x000-0x1FF) and (0x000-0x3FF) respectively, then Reserved
to 0x200 and 0x400, respectively (not to 0x000). 23Fh
In the configuration memory space, 0x200-0x23F for 240h
Unimplemented
the PIC12F508 and 0x400-0x43F for the PIC12F509 3FEh
are physically implemented. However, only locations Configuration Word 3FFh
0x200-0x203 and 0x400-0x403 are available. Other
locations are reserved.
FIGURE 2-2: PIC12F509 PROGRAM
2.2 User ID Locations MEMORY MAP
000h
A user may store identification information (ID) in four On-chip User
User Memory
user ID locations. The user ID locations are mapped in Space Program
1FFh
[0x200:0x203] and [0x400:0x403], respectively. It is On-chip User 200h
recommended that the user use only the four Least Program
Significant bits (LSb) of each user ID location and Memory (Page 1) 3FEh
program the upper 8 bits as ‘1’s. The user ID locations Reset Vector 3FFh
read out normally, even after code protection is 400h
User ID Locations
enabled. It is recommended that user ID location is
Config Memory

403h
written as ‘1111 1111 bbbb’ where ‘bbbb’ is user Backup OSCCAL value 404h
Space

ID information.
2.3 Configuration Word
The Configuration Word is physically located at 0x3FF
and 0x7FF, respectively. It is only available upon
Program mode entry. Once an Increment Address
command is issued, the Configuration Word is no
longer accessible, regardless of the address of the
program counter.
Note: By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC12F508/509. This logical address
location may not reflect the actual physical
address for the part itself. It is the respon-
sibility of the programming software to
retrieve the Configuration Word from the
logical address within the hex file and
granulate the address to the proper physi-
cal location when programming.
405h
Reserved
43Fh
440h
Unimplemented
7FEh
Configuration Word 7FFh
2.4 Oscillator Calibration Bits
The oscillator calibration bits are stored at the Reset
vector as the operand of a MOVLW instruction. Program-
ming interfaces must allow users to program the
calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.
2.5 Backup OSCCAL Value
The backup OSCCAL value, 0x204/0x404, is a factory
location where the OSCCAL value is stored during test-
ing of the INTOSC. This location is not erased during a
standard bulk erase, but is erased if the PC is moved
into configuration memory prior to invoking a bulk
erase. If this value is erased, it is the user’s responsibil-
ity to rewrite it back to this location for future use.

DS41227D-page 2 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
3.0 COMMANDS AND 3.1.2 SERIAL PROGRAM/VERIFY
ALGORITHMS OPERATION
The ICSPCLK pin is used for clock input and the
3.1 Program/Verify Mode ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
The Program/Verify mode is entered by holding pins six times. Each command bit is latched on the falling
ICSPCLK and ICSPDAT low while raising VDD pin from edge of the clock with the LSb of the command being
VIL to VDD. Then raise VPP from VIL to VIHH. Once in input first. The data must adhere to the setup (TSET1)
this mode, the user program memory and configuration and hold (THLD1) times with respect to the falling edge
memory can be accessed and programmed in serial of the clock (see Table 6-1).
fashion. Clock and data are Schmitt Trigger input in this
Commands that do not have data associated with them
mode.
are required to wait a minimum of TDLY2 measured
The sequence that enters the device into the Program- from the falling edge of the last command clock to the
ming/Verify mode places all other logic into the Reset rising edge of the next command clock (see Table 6-1).
state (the MCLR pin was initially at VIL). This means Commands that do have data associated with them
that all I/O are in the Reset state (high-impedance (Read and Load) are also required to wait TDLY2
inputs). between the command and the data segment
measured from the falling edge of the last command
3.1.1 PROGRAMMING clock to the rising edge of the first data clock. The data
The programming sequence loads a word, programs, segment, consisting of 16 clock cycles, can begin after
verifies and finally increments the PC. this delay.
Program/Verify mode entry will set the address to Note: After every End Programming command,
0x3FF for the PIC12F508 and 0x7FF for the a delay of TDIS is required.
PIC12F509. The Increment Address command will
The first and last clock pulses during the data segment
increment the PC. The available commands are shown
correspond to the Start and Stop bits respectively. Input
in Table 3-1.
data is a “don't care” during the Start and Stop cycles.
The 14 clock pulses between the Start and Stop cycles,
FIGURE 3-1: ENTERING HIGH clock the 14 bits of input/output data. Data is
VOLTAGE PROGRAM/ transferred LSb first.
VERIFY MODE
During Read commands, in which the data is output
TPPDP THLD0 from the PIC12F508/509, the ICSPDAT pin transitions
from the high-impedance input state to the low-imped-
ance output state at the rising edge of the second data
clock (first clock edge after the Start cycle). The
VPP ICSPDAT pin returns to the high-impedance state at
the rising edge of the 16th data clock (first edge of the
VDD Stop cycle). See Figure 3-3.
The commands that are available are described in
ICSPDAT
Table 3-1.

ICSPCLK

TABLE 3-1: COMMAND MAPPING FOR PIC12F508/509

Command Mapping (MSb … LSb) Data
Load Data for Program Memory x x 0 0 1 0 0, data (14), 0
Read Data from Program Memory x x 0 1 0 0 0, data (14), 0
Increment Address x x 0 1 1 0
Begin Programming x x 1 0 0 0 Externally Timed
End Programming x x 1 1 1 0
Bulk Erase Program Memory x x 1 0 0 1 Internally Timed

 2004 Microchip Technology Inc. Preliminary DS41227D-page 3

PIC12F508/509
3.1.2.1 Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-1.

FIGURE 3-2: LOAD DATA COMMAND (PROGRAM/VERIFY)

1 2 3 4 5 6 1 2 3 4 5 15 16
TDLY2
ICSPCLK

ICSPDAT 0 1 0 0 x x strt_bit LSb MSb stp_bit

TSET1 TDLY1 TSET1
THLD1 -+THLD1

3.1.2.2 Read Data From Program Memory

After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP = 0),
portions of the program memory will be read as zeros.
See Section 5.0 “Code Protection” for details.

FIGURE 3-3: READ DATA FROM PROGRAM MEMORY COMMAND

TDLY2

1 2 3 4 5 6 1 2 3 4 5 15 16
ICSPCLK
TDLY3
1 0 0 1 0 x x MSb stp_bit
ICSPDAT strt_bit
LSb
TSET1 TDLY1

THLD1

input output input

DS41227D-page 4 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
3.1.2.3 Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-4.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0x3FF
for the PIC12F508 or 0x7FF for the PIC12F509 to
0x000.

FIGURE 3-4: INCREMENT ADDRESS COMMAND

TDLY2
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

0 1 1 0 x x
ICSPDAT
TSET1
THLD1

3.1.2.4 Begin Programming (Externally

Timed)
A Load command must be given before every Begin
Programming command. Programming will begin after
this command is received and decoded. Programming
requires (TPROG) time and is terminated using an End
Programming command. This command programs the
current location, no erase is performed.

FIGURE 3-5: BEGIN PROGRAMMING (EXTERNALLY TIMED)

TPROG
End Programming Command
1 2 3 4 5 6 1 2
ICSPCLK

0 0 0 1 x x 0 1
ICSPDAT
TSET1 THLD1

 2004 Microchip Technology Inc. Preliminary DS41227D-page 5

PIC12F508/509
3.1.2.5 End Programming
The End Programming command terminates the
program process. A delay of TDIS (see Table 6-1) is
required before the next command to allow the internal
programming voltage to discharge (see Figure 3-6).

FIGURE 3-6: END PROGRAMMING (EXTERNALLY TIMED)

TDIS
Next Command
1 2 3 4 5 6 1 2
ICSPCLK

0 1 1 1 x x
ICSPDAT
TSET1 THLD1

3.1.2.6 Bulk Erase Program Memory To perform a full device bulk erase of the program
memory, configuration fuses, user IDs and backup
After this command is performed, the entire program
OSCCAL, the following sequence must be performed
memory and Configuration Word is erased.
(see Figure 3-13).
Note 1: A fully erased part will read ‘1’s in every 1. Read and save 0x1FF/0x3FF oscillator calibra-
program memory location. tion bits and 0x204/0x404 backup OSCCAL bits
2: The oscillator calibration bits are erased if into computer/programmer temporary memory.
a bulk erase is invoked. They must be 2. Enter Program/Verify mode.
read and saved prior to erasing the 3. Increment PC to 0x200/0x400 (first user ID
device and restored during the program- location).
ming operation. Oscillator calibration bits
4. Perform a Bulk Erase command.
are stored at the Reset vector as the
operand of a MOVLW instruction. 5. Wait TERA to complete bulk erase.
6. Restore OSCCAL bits.
To perform a bulk erase of the program memory and
configuration fuses, the following sequence must be 7. Restore backup OSCCAL bits.
performed (see Figure 3-12).
1. Read and save 0x1FF/0x3FF oscillator
calibration bits and 0x204/0x404 backup
OSCCAL bits into computer/programmer
temporary memory.
2. Enter Program/Verify mode. PC is set to Config-
uration Word address.
3. Perform a Bulk Erase Program Memory
command.
4. Wait TERA to complete bulk erase.
5. Restore OSCCAL bits.

DS41227D-page 6 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
TABLE 3-2: BULK ERASE RESULTS
Program Memory Space Configuration Memory Space
PC = Configuration Backup
Program Memory Reset Vector User ID
Word OSCCAL
Configuration Word or
E E E U U
Program Memory Space
First User ID Location E E E E E
Legend: E = Erased, U = Unaffected

FIGURE 3-7: BULK ERASE PROGRAM MEMORY COMMAND

TERA
Next Command
1 2 3 4 5 6 1 2

ICSPCLK

1 0 0 1 x x
ICSPDAT
TSET1

THLD1

 2004 Microchip Technology Inc. Preliminary DS41227D-page 7

PIC12F508/509
FIGURE 3-8: READING AND TEMPORARY SAVING OF THE OSCCAL CALIBRATION BITS

Start

Enter Programming
Mode

No PC =
Increment
Address 0x1FF/3FF?

Yes

Read Calibration
Bits and Save in
Computer/Programmer
Temp. Memory

Increment No PC =
Address 0x204/404?

Yes

Read Backup OSCCAL

Calibration Bits
and Save in
Computer/Programmer
Temp. Memory

Exit Programming Mode

Done

DS41227D-page 8 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
FIGURE 3-9: RESTORING/PROGRAMMING THE OSCCAL CALIBRATION BITS

Start

Enter Programming
Mode

Increment No PC =
Address 0x1FF/3FF?

Yes

Read Calibration
Bits from
Computer/Programmer
Temp. Memory

Write Calibration Bits

back as the operand
of a MOVLW instruction
to 0x1FF/3FF

Increment No PC =
Address 0x204/404?

Yes

Read Backup OSCCAL

Calibration Bits from
Computer/Programmer
Temp. Memory

Write Backup OSCCAL

Bits back to 0x204/404

Exit Programming Mode

Done

 2004 Microchip Technology Inc. Preliminary DS41227D-page 9

PIC12F508/509
FIGURE 3-10: PROGRAM FLOW CHART – PIC12F508/509 PROGRAM MEMORY

Start

Read and save

OSCCAL bits
(Figure 3-8)

Enter Programming
Mode
PC = 0x3FF/7FF
(Config Word)

Increment
Address

Bulk Erase PROGRAM CYCLE

Device
Load Data
for
Program Memory
One Word
Program Cycle
Begin
Programming
Command
Read Data (Externally timed)
from
Program Memory

Wait TPROG
Report
No
Data Correct? Programming
Failure
End
Yes
Programming

Increment
Address No
All Programming
Command
Locations
Done? Wait TDIS

Yes

Exit Programming
Mode

Restore 0SCCAL bits

(Figure 3-9)

Program
Configuration
Memory
(Figure 3-11)

Done

DS41227D-page 10 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
FIGURE 3-11: PROGRAM FLOW CHART – PIC12F508/509 CONFIGURATION MEMORY

Start

Enter Programming
Mode
PC = 0x3FF/7FF
(Config Word)

Load Data Command

Programs Configuration Word

One-Word
Programming
Cycle
(see Figure 3-10)

Read Data Command

Data No Report
Correct? Programming
Failure
Yes

Increment Address
Command

No Address =
0x200/400?

Yes
Load Data
Command Programs User IDs

One-Word
Programming Read Data Command
Cycle
(see Figure 3-10)

Data No Report
Correct? Programming
Failure

Yes

Increment Address
Command

No Address =
0x204/404?

Yes

Exit Programming Mode

Done

 2004 Microchip Technology Inc. Preliminary DS41227D-page 11

PIC12F508/509
FIGURE 3-12: PROGRAM FLOW CHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD

Start
Bulk Erase Device

Read and save

OSCCAL bits Wait TERA
(Figure 3-8)

Restore OSCCAL bits

Enter (Figure 3-9)
Program/Verify mode
PC = 0x3FF/7FF
(Config Word)
Exit Programming
Mode

Done

DS41227D-page 12 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
FIGURE 3-13: PROGRAM FLOW CHART – ERASE PROGRAM MEMORY, CONFIGURATION
WORD AND USER ID

Read and save

Start
OSCCAL bits
(Figure 3-8)

Enter
Program/Verify mode
PC = 0x3FF/7FF
(Config Word)

Increment No PC = 0x200/400?
PC (First User ID)

Yes

Bulk Erase Device

Wait TERA Restore OSCCAL bits

(Figure 3-9)

Exit Programming Mode

Done

 2004 Microchip Technology Inc. Preliminary DS41227D-page 13

PIC12F508/509
4.0 CONFIGURATION WORD
The PIC12F508/509 has several configuration bits.
These bits can be programmed (reads ‘0’) or left
unchanged (reads ‘1’), to select various device
configurations.

REGISTER 4-1: CONFIGURATION WORD – PIC12F508/509

— — — — — — — MCLRE CP WDTE FOSC1 FOSC0

bit 11 bit 0

bit 11-5 Unimplemented: Read as ‘1’

bit 4 MCLRE: Master Clear Enable bit
1 = GP3/MCLR pin functions as MCLR
0 = GP3/MCLR pin functions as GP3, MCLR internally tied to VDD
bit 3 CP: Code Protection bit
1 = Code protection off
0 = Code protection on
bit 2 WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0 FOSC1:FOSC0: Oscillator Selection bits
00 = LP oscillator
01 = XT oscillator
10 = INTOSC
11 = EXTRC

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

DS41227D-page 14 Preliminary  2004 Microchip Technology Inc.


5.0 CODE PROTECTION
For the PIC12F508/509, once code protection is
enabled, all program memory locations 0x040-0x1FE
(F508) and 0x040-0x3FE (F509) inclusive, read all ‘0’s.
Program memory locations 0x000-0x03F, 0x1FF
(F508) and 0x3FF (F509) are always unprotected. The
user ID locations, backup OSCCAL location and the
Configuration Word read out in an unprotected fashion.
It is possible to program the user ID locations, backup
OSCCAL location and the Configuration Word after
code-protect is enabled.
5.1 Disabling Code Protection
It is recommended that the following procedure be
performed before any other programming is attempted.
It is also possible to turn code protection off (CP = 1)
using this procedure. However, all data within the
program memory will be erased when this
procedure is executed, and thus, the security of the
code is not compromised.
PIC12F508/509
5.3 Checksum Computation
5.3.1 CHECKSUM
Checksum is calculated by reading the contents of the
PIC12F508/509 memory locations and adding up the
opcodes up to the maximum user addressable location
(e.g., 0x1FF for the PIC12F508). Any carry bits
exceeding 16 bits are neglected. Finally, the Configura-
tion Word (appropriately masked) is added to the
checksum. Checksum computation for the PIC12F508/
509 is shown in Table 5-1.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The Configuration Word, appropriately masked
• Masked user ID locations (when applicable)
The Least Significant 16 bits of this sum is the
checksum.
The following table describes how to calculate the
checksum for each device.

To disable code-protect: Note: The checksum calculation differs depend-

ing on the code-protect setting. The
a) Enter Program mode
Configuration Word and user ID locations
b) Execute Bulk Erase Program Memory can always be read regardless of the
command (001001) code-protect settings.
c) Wait TERA

5.2 Embedding Configuration Word

and User ID Information in the
Hex File
Note: To allow portability of code, the program-
mer is required to read the Configuration
Word and user ID locations from the hex
file when loading the hex file. If Configura-
tion Word information was not present in
the hex file, then a simple warning
message may be issued. Similarly, while
saving a hex file, Configuration Word and
user ID information must be included. An
option to not include this information may
be provided.
Microchip Technology Incorporated feels
strongly that this feature is important for
the benefit of the end customer.

 2004 Microchip Technology Inc. Preliminary DS41227D-page 15

PIC12F508/509
TABLE 5-1: CHECKSUM COMPUTATIONS – PIC12F508(1)
0x723 at 0
Blank
Device Code-Protect Checksum* and Max
Value
Address
PIC12F508 OFF SUM[0x000:0x1FE] + CFGW & 0x01F 0xEE20 0x0C68
ON SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID 0xEDF7 0xD363
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.

TABLE 5-2: CHECKSUM COMPUTATIONS – PIC12F509(1)

0x723 at 0
Blank
Device Code-Protect Checksum* and Max
Value
Address
PIC12F509 OFF SUM[0x000:0x3FE] + CFGW & 0x01F 0xEC20 0xDA68
ON SUM[0x00:0x3F] + CFGW & 0x01F + SUM_ID 0xEBF7 0xD163
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a to b inclusive]
SUM_ID = User ID locations masked by 0xF then made into a 16-bit value with ID0 as the Most Significant
nibble.
For example, ID0 = 0x1, ID1 = 0x2, ID2 = 0x3, ID3 = 0x4, then SUM_ID = 0x1234.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
Note 1: Checksum shown assumes that SUM_ID contains the unprotected checksum.

DS41227D-page 16 Preliminary  2004 Microchip Technology Inc.

 PIC12F508/509
6.0 PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS

TABLE 6-1: AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY

MODE
Standard Operating Conditions (unless otherwise stated)
AC/DC CHARACTERISTICS Operating Temperature 10°C ≤ TA ≤ 40°C
Operating Voltage 4.5V ≤ VDD ≤ 5.5V
Conditions/
Sym Characteristics Min Typ Max Units
Comments
General
VDDPROG VDD level for read/write operations, program TBD — 5.5 V
memory
VDDERA VDD level for bulk erase/write operations, 4.5 — 5.5 V
program memory
IDDPROG IDD level for read/write operations, program TBD TBD mA
memory
IDDERA IDD level for bulk erase/write operations, TBD TBD mA
program memory
VIHH High voltage on MCLR for Program/Verify 12.5 — 13.5 V
mode entry
IIHH MCLR pin current during Program/Verify 0.5 TBD mA
mode
TVHHR MCLR rise time (VSS to VIHH) for Program/ — — 1.0 µs
Verify mode entry
TPPDP Hold time after VPP↑ 5 — — µs
VIH1 (ICSPCLK, ICSPDAT) input high level 0.8 VDD — — V
VIL1 (ICSPCLK, ICSPDAT) input low level — — 0.2 VDD V
TSET0 ICSPCLK, ICSPDAT setup time before 100 — — ns
MCLR↑ (Program/Verify mode selection
pattern setup time)
THLD0 ICSPCLK, ICSPDAT hold time after MCLR↑ 5 — — µs
(Program/Verify mode selection pattern setup
time)
Serial Program/Verify
TSET1 Data in setup time before clock↓ 100 — — ns
THLD1 Data in hold time after clock↓ 100 — — ns
TDLY1 Data input not driven to next clock input (delay 1.0 — — µs
required between command/data or
command/command)
TDLY2 Delay between clock↓ to clock↑ of next 1.0 — — µs
command or data
TDLY3 Clock↑ to data out valid (during Read Data) — 80 ns
(1)
TERA Erase cycle time — 6 10 ms
TPROG Programming cycle time (externally timed) — 1 2(1) ms
TDIS Time delay for internal programming voltage 100 — — µs
discharge
TRESET Time between exiting Program mode with VDD — 10 — ms
and VPP at GND and then re-entering Program
mode by applying VDD.
Legend: TBD = To Be Determined.
Note 1: Minimum time to ensure that function completes successfully over voltage, temperature and device variations.

 2004 Microchip Technology Inc. Preliminary DS41227D-page 17

PIC12F508/509
NOTES:

DS41227D-page 18 Preliminary  2004 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. Use of Microchip’s products as critical components in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2004 Microchip Technology Inc. DS41227D-page 19

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09/27/04

DS41227D-page 20  2004 Microchip Technology Inc.