REVIEW

Silicon Device Scaling to the

Sub-10-nm Regime
Meikei Ieong,1* Bruce Doris,2 Jakub Kedzierski,1 Ken Rim,1 Min Yang1

channel transistors. This source, substrate,

In the next decade, advances in complementary metal-oxide semiconductor fabrication and drain doping effectively produces two
will lead to devices with gate lengths (the region in the device that switches the current back-to-back junction diodes from the source
flow on and off) below 10 nanometers (nm), as compared with current gate lengths in terminal to the drain terminal. When a suf-
chips that are now about 50 nm. However, conventional scaling will no longer be ficiently large positive voltage is applied to
sufficient to continue device performance by creating smaller transistors. Alternatives the gate of an N-channel transistor (which
that are being pursued include new device geometries such as ultrathin channel struc- creates an electric field, hence the field ef-
tures to control capacitive losses and multiple gates to better control leakage pathways. fect), the silicon surface is ‘‘inverted’’—the
Improvement in device speed by enhancing the mobility of charge carriers may be ob- conduction band is populated and forms a
tained with strain engineering and the use of different crystal orientations. Here, we narrow conducting layer between the source
discuss challenges and possible solutions for continued silicon device performance trends and the drain. If there is a voltage difference
down to the sub-10-nm gate regimes. between the source and the drain, an electric
current can flow between them. When the

T
he steady reduction in the minimum 10 nm (1). We discuss below the challenges gate voltage is removed or set at zero volt-
feature size in integrated circuits has in device scaling and possible solutions in age, the surface region under the gate is
helped the microelectronic industry to maintaining the performance trend. depleted with electric carriers and there is no
produce products with spectacular increase in current flow between the source and the
computational capability and integration den- MOSFETs: The Building Blocks drain. We can therefore see that the current
sity at lower cost. Smaller transistors operate The MOSFET, or metal oxide semiconductor flowing through the structure can be regulat-
faster than larger ones, and for a given chip field-effect transistor, is a fundamental ed by applying voltage to the gate electrode.
technology, the cost
of a chip decreases
with area rather than B C
A Scaled Device
with the number of
transistors. Voltage, V/α
The exponential ed
tox/α pe

ctive
s
Gate delay

scaling trend surely SCALING e

as

Pa
will eventually hit Voltage: V/α re
GATE Vt In
c

uce
fundamental limits, Oxide: tox/α

Red
but the many predic- n+ source n+ drain
Gate Length: L/α
tions of a near-term Diffusion: xd/α e P standby
end of device scaling Substrate: α*NA Reduc
have proven too pes- L/α
xd/α Vt Vdd Vdd
simistic. With the
introduction of the p substrate, doping α*NA
production of 90-nm
node technology in
2004, the semicon- Fig. 1. (A) Schematic of MOSFET indicating various relevant device scaling parameters. (B) Complementary metal-oxide
ductor industry is en- semiconductor (CMOS) inverter gate delay as a function of power-supply voltage (Vdd). Gate delay rapidly increases as Vdd
tering the Bnano[ era approaches the threshold voltage (Vt). (C) Design space for supply and threshold voltages for optimum performance and
power dissipation. Technology scaling diminishes this design space.
(1). (The B90-nm
node[ refers to the
smallest half-pitch metal lines available in the switching device in very-large-scale integrat- A MOSFET can be used either as an elec-
technology. The actual gate lengths of the de- ed (VLSI) circuits. A MOSFET (Fig. 1A) trical switch or as an amplifier. The majority
vices are about 50 nm.) In the next decade, has at least three terminals, which are des- of MOSFETs on an integrated circuit today
device gate lengths will be scaled to below ignated as gate, source, and drain. The gate are used as electrical switches. How fast a
electrode is separated electrically from the MOSFET can be switched on and off is
1
IBM Semiconductor Research and Development source and the drain by a thin dielectric film, therefore a critical figure of merit to deter-
Center, T. J. Watson Research Center, Yorktown
2
Heights, NY 10598, USA. IBM Semiconductor Re-
usually silicon dioxide. The source and the mine the competitiveness of the technology.
search and Development Center, Microelectronic drain are doped with impurities that are op- The two major factors that control the speed
Division, Hopewell Junction, NY 12533, USA. posite in polarity to the substrate, which is of MOSFETs are the channel length from
*To whom correspondence should be addressed. doped with boron for N-channel transistors the source to the drain and the speed at which
E-mail: mkieong@us.ibm.com and with arsenic or phosphorous for P- channel charge carriers travel from the source

www.sciencemag.org SCIENCE VOL 306 17 DECEMBER 2004 2057

 REVIEW
to the drain. We will discuss these two fac-
tors in more detail below.
Shrinking the Transistor
Shrinking transistors not only packs more
devices into a given area but also shortens the
distance between source and drain, or the gate
length, which can improve the switching
speed. The two challenges in
decreasing MOSFET size are
fabrication and maintaining
performance. The backbone
of MOSFET fabrication is a
process called lithography,
which resembles the printing
of a photograph by shining
light through a negative onto
a photosensitive surface. Li-
thography allows complex
patterns to be created through
a series of printing and etch-
ing steps. The ability to print
ever-smaller fine lines is
mandatory for continued de-
vice scaling. Advanced photo-
lithography techniques have
enabled the industry to keep
pace with the demand im-
posed by increasingly smaller Fig. 2. Device schematics and cross sections for (A) SOI MOSFET, (B) UTSOI lem is exacerbated by the
structures. However, the MOSFET, and (C) FinFET double-gate MOSFET.
smallest feature size is re-
lated to the fundamental
limit of wavelength used in
conventional optical lithog-
raphy. Alternative technol-
ogies capable of writing
features far smaller than
those produced by conven-
tional optics have also been
demonstrated and include
the use of extreme ultravio-
let (EUV) radiation, x-rays,
and electron beams. Re-
cently, the self-assembly
process has attracted much
attention because of its po-
tential in producing nano-
scale patterns. The concern
is whether any of these al-
ternatives can be scaled up
to meet the throughput, con-
trol, and cost requirements Fig. 3. Device cross sections for (A) strained silicon on insulator (SGOI), (B) strained consumed when the device
for manufacturing. silicon directly on insulator (SSDOI), and (C) hybrid-orientation technology (HOT). is off (the stand-by power)
Given the ability to cre-
ate smaller device features,
to what extent can the gate length be re-
duced before the MOSFET ceases to func-
tion as a switch? The gate terminal can lose
the control of channel electric carriers when
the source and the drain are brought into
proximity without scaling other device pa-
rameters. Eventually, the gate terminal can-
not turn off the devices, and transistor action
can no longer be observed. This phenom-
enon is the so-called short-channel effect
2058 17 DECEMBER 2004
(SCE). According to the scaling theory of
Dennard (2), the vertical dimensions (gate-
oxide thickness, junction depth, and depletion
width) must be scaled down with the lateral
dimensions such as gate length. This theory
guarantees appropriate electrostatic character-
istics when a larger device is scaled down to
a smaller one (Fig. 1A). The industry has
been by and large following this scaling
guideline for shrinking MOSFETs to gain
higher density and speed without degrading
reliability and power.
The accelerated gate-length scaling in the
past decade has pushed many vertical device
parameters to their fundamental or techno-
logical limits. For example, gate oxide now
consists of only a few atomic layers; alterna-
tive gate materials with a higher dielectric
VOL 306 SCIENCE www.sciencemag.org
constant are needed. It is also difficult to pro-
duce an extremely shallow and abrupt junction
without increasing the external resistance.
(Junction resistance is inversely proportional
to junction depth.)
Ion implantation has been the dominant
process for the creation of shallow junctions. A
high-temperature annealing process is needed
to repair the damage to the
single crystal and to activate
the dopant atoms. During this
step, diffusion and redistribu-
tion of dopant atoms occur. A
high-temperature, short time
scale annealing process is
more desirable to produce
shallow and abrupt junctions.
A near-zero thermal-budget
junction technology, such as
millisecond flash-lamp and la-
ser annealing, will be required.
Finally, the increase in
channel doping needed for
SCE control will substantial-
ly increase the junction ca-
pacitance and leakage. All of
these changes degrade de-
vice performance. The prob-
‘‘nonscaling’’ factors that
arise when the traditional
MOSFET design is scaled.
Nonscaling Factors
As pointed out above, sev-
eral factors do not scale as
we shrink MOSFETs. The
subthreshold nonscaling issue
is the most fundamental one
(3). A MOSFET is turned on
when a sufficiently high volt-
age is applied to the gate.
The voltage above which the
MOSFET is turned on is
loosely defined as threshold
voltage. The leakage current
in the off state depends ex-
ponentially on the threshold
voltage. Ideally, one would
keep the threshold voltage
high to minimize the power
and to ensure an appropri-
ate noise margin. The sup-
ply voltage is usually reduced in device
scaling to keep the active power manageable
and to ensure reliability. However, higher
device performance will require as much
gate overdrive (the excess voltage applied
above the threshold) as possible, because
higher driving voltages lead to faster switch-
ing. Figure 1B shows the circuit delay as
a function of supply voltage, Vdd. Perform-
ance can only be maintained by keeping

threshold voltages low, but the threshold
voltage cannot be scaled down much without
causing a substantial increase in leakage cur-
rent in the off state. The proper choice of
Vdd and threshold voltage for best per-
formance and power tradeoff depends on the
application. The design window rapidly dimin-
ishes as technology is scaled down (Fig. 1C).
In addition, the aggressive reduction in gate
dielectric has also caused exponential in-
crease in gate leakage.
Together, these effects have caused
the so-called power crisis in the silicon
chip industry. Power management has
tension should be designed to minimize loss
of dopant dose and to avoid complete amor-
phization of the silicon layer by the ion im-
plantation process. A thin gate spacer coupled
with the raised-source-drain process has been
shown to be effective in minimizing external
resistance without compromising parasitic
capacitance. With this new process scheme,
improved drive currents were realized (9).
Setting and controlling the threshold volt-
age in devices with such thin SOI layers is also
REVIEW
SOI channels could be a fundamental issue.
The channel mobility is substantially reduced at
SOI thicknesses below 10 nm. This decrease
may be caused by a ‘‘surface roughness’’–like
scattering mechanism that results from the
perturbation of band potential by variations
in the SOI layer thickness (10).
The ultrathin SOI thickness requirement for
SCE control in single-gate FETs can be relaxed
by using a more complex ‘‘double-gate’’ FET
that offers improved electrostatic gate control
of the body. There are many review ar-
ticles on double-gate devices (11–13).
The symmetric nature in a double-gate

Gate
now become the number one issue in
any high-performance and low-power
application. Currently, there is a con-
Source
sensus that maintaining the device
performance trend with conventional
device scaling technique is extremely
Z FET reduces the depletion width by 50%
compared with that of a single-gate
structure. In addition, there is no drain-
Drain
to-body fringing field through the buried
STI
oxide (BOX) (Fig. 2A) in a double-gate
Desired Stress: structure. Numerical simulations indicate

Transverse
challenging, if possible at all. New Tran. Long. Z that scalability for double-gate FETs
Gate

device structures and materials will be Source Drain

pFET T C T improves by a factor of 2.5 to 3 (5). Be-
needed to sustain the current rate of nFET T T C
cause the double-gate device operates
progress in device technology. at much lower vertical electric fields,
T: Tensile stress the mobility requirement in double-gate
C: Compressive stress
Possible Solutions for Longitudinal devices can be lower than that of con-
Device Scaling Fig. 4. Possible directions of uniaxial stresses and their effects ventional planar MOSFETs (14).
Circuit performance can be improved on N-channel and P-channel MOSFETs. Double-gate FETs can be fabricated
by building conventional MOSFETs on in planar (14, 15), vertical (16), and
a silicon-on-insulator (SOI) substrate finlike (17–19) structures. Of all the
(Fig. 2A). The insulator layer can be Conduction band Unstr. Si Strained Si double-gate device structures, the FinFET
created by implanting oxygen ions and ∆2 valleys ∆4 m is the simplest to implement. The body
then annealing the layer to form an ∆6 l of a FinFET device consists of a vertical
oxide. The addition of an oxide layer Ec crystalline silicon wall (Fig. 2C). The
below the transistor junction SOI layer gate wraps around both sides of the fin
can effectively reduce the junction ∆ mt and creates a channel on each side of
capacitance and leakage current. It ∆4 valleys ml 2
the fin. In a FinFET, the two channels
also eliminates the so-called ‘‘reverse mt mt < ml are perpendicular to the wafer surface
body effect’’ (4) in stacked circuits. As and the current direction is parallel to
mt
a result, SOI technology offers a faster the wafer surface. High current has been
circuit and consumes less power. Valence band demonstrated when the FinFET struc-
Ultrathin SOI (UTSOI) MOSFET is ture is combined with a raised-source-
Bulk Si E Strained Si E
an attractive option for device scaling, drain process.
because it can effectively reduce the SCE out-of-
and eliminate most of the leakage plane Enhanced Mobility: Making
paths (5–7). For thicker SOI channels, HH k meV k Carriers Travel Faster
∆E 38
the drain field could easily penetrate to 10%Ge Mobility enhancement is an attractive
the source side through the channel or LH option, because it can potentially im-
buried oxide when the gate length is prove device performance beyond any
reduced. However, a thin SOI channel Spin-orbit of the benefits from device scaling.
can resolve this problem. Based on this The two main approaches being pursued
Fig. 5. Biaxial stress effects on the conduction and valence
concept, a functional transistor with a bands of strained silicon. are strain engineering (both process-
gate length of 6 nm was demonstrated induced and substrate-induced) and ori-
(Fig. 2B) by using an ultrathin channel entation effects (Fig. 3).
of 4 to 8 nm and aggressive ‘‘halo’’ (8) im- quite challenging. Conventional doping schemes Strain engineering. Strain effects induced
plantation (6). This extremely small silicon may not be effective as a result of doping during the fabrication process can increase the
MOSFET was functional, but its device drive fluctuation. One attractive process option is channel mobility. Both tensile and compres-
current suffered from channel mobility degra- to completely ‘‘silicide’’ the polycrystalline- sive stresses can be introduced in any one of
dation and high external resistance. silicon gate stack by converting the polysili- the three dimensions by process techniques
The integration of ultrathin SOI channels con to a metal silicide. The gate work function (20–27). The electron and hole mobility re-
into the conventional MOSFET process is can be adjusted over a substantial range by spond differently to uniaxial stresses (Fig. 4).
quite challenging. The gate and spacer mod- alloyed silicide and ion implantation to the The most effective way to introduce high
ules must be carefully designed to prevent gate before silicidation (7). Although the ex- tensile strain to the channel is to epitaxially
substantial silicon consumption. The ion im- ternal resistance can be reduced by process grow strained silicon on a relaxed silicon ger-
plantation process for the source/drain ex- improvement, the mobility degradation in thin manium (SiGe) layer. Because of the lattice

www.sciencemag.org SCIENCE VOL 306 17 DECEMBER 2004 2059

 REVIEW
mismatch between silicon and SiGe, the lat-
tice of the silicon layer is stretched (strained)
in the plane of the interface. This deformation
breaks the symmetry of the energy-band struc-
ture and results in band splitting (Fig. 5). The
reduced interband/intervalley scattering and
effective masses result in enhanced carrier
transport in the strained-silicon layer that is
used as the channel of the MOSFET. En-
hanced drive currents of 15 to 25% have been
demonstrated on sub-100-nm bulk strained-
silicon MOSFETs (20). The performance ben-
efit of combining strained silicon with an
SOI substrate has also been demonstrated in a
60-nm gate length, N-channel MOSFET with
ultrathin thermally mixed strained silicon/
SiGe on insulator substrate (28). The presence
of the SiGe layer in strained-silicon substrate
leads to several challenges related to materials
and integration, such as a high density of
defects in strained silicon on relaxed SiGe
induced by the strain relaxation in SiGe and a
substantial difference in doping diffusion
property in SiGe. (Boron diffusion is retarded,
whereas arsenic diffusion is enhanced as com-
pared with the diffusion in silicon.) Such
challenges require additional efforts in junc-
tion engineering to control SCEs and to set
the MOSFET threshold voltages to the desired
values. Substantial device self-heating is also
observed in strained silicon/SiGe devices
because of the lower thermal conductivity in
SiGe. Recently, Rim et al. (29) demonstrated
transistors using ultrathin strained silicon
directly on insulator (SSDOI) structures that
eliminate the SiGe layer before transistor fab-
rication, thereby providing higher mobility
while mitigating the SiGe-induced material
and process integration problems.
An SSDOI structure is fabricated by a
layer-transfer or ‘‘wafer-bonding’’ technique.
First, an ultrathin layer of strained silicon is
formed epitaxially on a relaxed SiGe layer,
and an oxide layer is formed on top. After
hydrogen is implanted into the SiGe layer, the
wafer is flipped and bonded to a handle
substrate. A high-temperature process splits
away most of the original wafer and leaves
the strained-silicon and SiGe layers on top of
the oxide layer. The SiGe is then selectively
removed and transistors are fabricated on the
remaining ultrathin strained-silicon. A fabri-
cated SSDOI device structure is shown in
Fig. 3A. Both electron and hole mobility
enhancement have been observed, which indi-
cates that strain is retained after the device-
processing steps have been completed (29).
Crystal orientation effects. The carrier
mobility of inversion layers depends on surface
orientations and current flow directions. For P-
channel MOSFETs, hole mobility is 2.5 times
as high on (110) surface orientation as on a
standard wafer with (100) surface orientation
(30). However, electron mobility is highest on
(100) substrates. To fully realize the advan-
2060 17 DECEMBER 2004
tage of the carrier mobility dependence on
surface orientation, a new technology has been
developed to fabricate complementary metal-
oxide semiconductor (CMOS) on hybrid sub-
strates with different crystal orientations, with
NFETs on silicon of (100) surface orientation
and PFETs on (110) surface orientation (31).
In this hybrid-orientation technology (HOT),
layer-transfer process, block-level trench etch,
and epitaxial regrowth were performed before
the conventional CMOS device process. A
cross section of CMOS on hybrid substrate is
shown in Fig. 3C, with NFET on (100) SOI
and PFET on (110) silicon epitaxial layer. The
hybrid substrate was formed by layer-transfer
technique through wafer bonding. First, hy-
drogen was implanted into an oxidized silicon
substrate. The wafer was then flip-bonded to a
handle wafer with different surface orienta-
tion. A two-phase heat treatment was then
carried out to split the hydrogen-implanted
wafer and strengthen the bonding. Finally, the
top SOI layer was polished and thinned down
to the desired thickness. A substantial PFET
performance enhancement was demonstrated
on 90-nm-node CMOS devices.
Threshold voltage roll-off behavior, junc-
tion leakage current, overlap, and junction
capacitances are all very similar between
(110) and (100) substrates, which indicates
similar dopant diffusion characteristics for
these orientations. The HOT technology is
clearly an attractive option to improve device
performance without introducing new mate-
rial. However, the impact on circuit perform-
ance of mixing SOI and bulk devices on the
same chip will require more detailed analysis.
Viability: The Crucial Issues
The 2003 version of the International Road-
map for Semiconductors (1) projected that, by
2016, sub-10-nm gate-length MOSFETs will
be in production with equivalent oxide thick-
nesses of 5 Å and junction depths below 10 nm.
Although functional MOSFETs with sub-10-
nm gate lengths have been demonstrated using
UTSOI substrate, manufacturability problems
of sub-10-nm gate devices remain to be re-
solved. First, gate stacks with higher dielectric
constants and metal gate electrodes are needed
to mitigate the gate leakage problem. Second,
alternative doping techniques are required to
produce shallow and abrupt junction profiles
without severely increasing the external re-
sistance. Third, alternative device structures
such as UTSOI and double-gate structures will
likely be needed for sub-10-nm gate devices.
Additional sources of performance gain are
also needed to compensate for any degradation
from the subthreshold nonscaling phenomenon.
Mobility-enhancement technique is attractive,
because it provides performance enhancement
in addition to any benefits derived from device
scaling alone. Straining the silicon crystal and
building N-type and P-type MOSFETs on differ-
VOL 306 SCIENCE www.sciencemag.org
ent crystal orientations are promising methods
for mobility enhancement. In fact, some form
of strained-silicon techniques are already being
used in silicon integrated-circuit manufactur-
ing. Some scaling and mobility-enhancement
options can be combined for even higher per-
formance gains. One example that integrates
both UTSOI and FinFET devices on the same
wafer and that enables hybrid orientation was
reported by Doris et al. (32).
The growing power density and the diminish-
ing process margin of sub-10-nm gate-length
MOSFETs cannot be dealt with by process tech-
nology alone. Overall system performance gain
will require optimization among the technol-
ogy, circuit, packaging, and architecture levels.
References and Notes
1. Semiconductor Industry Association, International
Technology Roadmap for Semiconductors (2003);
available at http://public.itrs.net.
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(1974).
3. Y. Taur, IEEE Spectrum 36, 25 (1999).
4. The performance of bulk MOSFETs is often degraded
in a stack configuration. This is known as the reverse
body effect. In SOI technology, the body is isolated
from other terminals; therefore, the reverse body
effect can be avoided.
5. M. Ieong, J. Kedzierski, Z. Ren, B. Doris, T. Kanarsky, H.-S.
P. Wong, Extended Abstract of the 2002 International
Conference on Solid State Devices and Materials (SSDM),
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8. A halo implant is an ion implantation technique that
places impurity dopants next to the junction tip to
prevent SCEs without substantially increasing the
total amount of impurity dopants in the channel.
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shorter gate lengths before notable SCE sets in.
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33. The authors are grateful to their IBM colleagues.
Fabrication support by the Advanced Semiconductor
Technology Center of IBM Microelectronic Division
and the Advanced Semiconductor Technology Labo-
ratory of IBM Research are very much appreciated.
10.1126/science.1100731