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DAC Supplemental

UCSD

Jerry Twomey

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•Details of the DAC process:


•Figure: Sub sections of many DAC systems
DAC input is a digital code
Digital Input, often synchronous to a clock,
binary code is common
DAC may convert to another code format.
Positive/Negative sign bit may be used.

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•DAC system (DAC and LPF) converts a numeric value that represents
a signal that is discrete-amplitude, and discrete-time, to a continuous
time and continuous amplitude signal.
•DAC without the LPF will produce discrete output amplitudes
Common to most DAC systems:
Digital input is converted to a digital control pattern that is compatible
with the architecture of the analog parts of the DAC
Converter taking the digital control pattern and using the DAC to
produce analog voltage equivalents
Deglitching, common in many (not all) devices with sample and hold,
reduces effects of switching transitions.
deglitcher may be removed if DAC conversion is very good or
application can tolerate transition glitches.

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Spectral shaping (now commonly done in DSP prior to DAC) to


remove spectral effects due to sampling systems.
analog low-pass filter (LPF) limits output signal bandwidth so
spectral content of clocking and discrete, quantized analog "steps"
are removed/reduced in the waveform.

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Integral nonlinearity (INL) can be defined in two slightly different
ways:

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•DAC output, Settling time and Glitch Impulses

•Settling time – amount of time for output to experience full- scale


transition and settle within a specified error band around final value.
•Settling time and delay are usually functions of output loading and
switching speed,
•Glitch impulse (a.k.a. "Glitch Energy"): maximum area under any
extraneous output glitch that appears after input code changes. Also
called "glitch energy" (even though it does not have an energy dimension)
Glitch impulse depends on the DAC architecture and quality of the design.
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•Latency (a.k.a. "Conversion Delay") is the total delay from the time
the input changes to the time the output changes.
•Latency may include multiples of the clock period if the ADC/DAC is
pipelined in some form.
•Latency in an ADC:

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Common DAC Structures


Available
Type: Resistor String DAC
Figure: One of N control input
resistor string DAC
Multiplexing control for a resistor
divider
Without output buffer amplifier, can
be sensitive to loading.

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As number of bits
increases, digital decoder
interconnect becomes
problematic. (i.e. 8 bits, 256
connections)
Figure: Binary control input
resistor string DAC
Binary control method leads
to large numbers of switches
in series.
Switching speeds can be
slowed by the RC effects of
the switches.

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Simpler control coding, binary input, and the compliment.


Typical Applications
Offset and trim control,
Low conversion rate system,
Useful in systems that do not have a clock running in the system.

Size:
Depends on bit count,
Have seen 6 bit versions in 100x200 micron area.
Conversion rate:
BW limited by buffer amplifier

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Considerations in Design:
All resistor string DAC's at high bit counts require large number of
elements.
Resistors can take up large areas of die space.
Devices can have multiple outputs that use the same R-string.
•Example: four multiplexing circuits, one R-string
• 4 DAC's in an area slightly larger than a single DAC

Op-amp will have some offset associated therewith.

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Type: Sub
Ranging Resistor
String
Variation on the
resistor string,
reduces number of
resistors, and
simplifies control
switching.

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Typical Applications
Similar to R-string applications.
Size:
DOPP, and on desired bit count:
8 bit device seen on .35 um process in area of 200 x 300 um
Conversion Rate:
Limited by settling times of all three amplifiers.
Considerations in Design:
Can be "glitchy" due to 3 amps "settling out" at the same time.
Output amp can have a sample and hold, to reduce transition switching
issues.
Conversion rate - limited by the amp bandwidth
Useful method of getting a low bandwidth, no clock needed, DAC into a
small area.
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Type: Current Steering DAC's


Figure: Concept - Summation of current sources into
a common load resistance.

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Binary summation of current sources is very problematic.
Transition glitches when changing state.
High demands on matching of current sources
10 bit DAC would require a (512 * Imin) and a (1* Imin) current
source that would need matching accuracy of (1/1024) to get
1/2 LSB of DNL accuracy. Not viable.
Works nicely as a mathematical model but not in the real world.

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Figure: Thermometer
code control DAC.
Reduces transition
glitch energy
Matching of current
sources can be relaxed
sizably.
Matching of 1/2 to get
1/2 LSB of DNL
accuracy.
Above 8 bits,
interconnection, number
of switches, control
signal decoding, switch
phasing can be
problematic.

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Compromise: Segmented architecture
MSB's are done with thermometer code
LSB's are done with a binary code control.
Reduces interconnect problems
Compromises on matching requirements
Compromises on transition glitch problems.
6-8 bit thermometer and 4-2 bit binary are common in 10 bit DAC
Typical Applications:
High bandwidth applications
High output current applications
Suitable to drive an external coaxial cable.
DDS (direct digital synthesis) waveform generation.
Video output drivers. Page 17
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Size:
10 bit devices done with cascode current sources and differential
outputs, that were 1500 x 2000 microns.
Conversion Rate:
When done properly, easily over 250MHz.
Considerations in Design:
Current sources are not turned on/off, two switches steer current.
Bias distribution must be carefully done. (Ibias distribution and
local diode references.)
timing alignment of all switches should be synchronized and in
tight alignment to reduce glitches.

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Over-sampling DACs
•Pulse Coded Modulation (PCM), Pulse Width Modulation (PWM)
Sigma-Delta
•PCM and PWM are two names, same thing.
•Architecture & Waveforms from a PWM DAC:

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Typical Applications:
Low bandwidth applications, Audio BW and similar.
Guaranteed Monotonic, so, common in motion control and other
feedback control systems.
Size:
Extremely small, LPF is largest part of the system.
Conversion Rate:
Need to examine the clocking rate, and the spectral content of the
digital output.
LPF BW typically a 10X or more below the clocking rate.
Considerations in Design:
Attempt to keep the spectral content of the output high.

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Oversampling: Sigma Delta
Takes and introduces Sum (sigma) and Difference (delta)
values.
Digital output prior to LPF is no longer 2 state with duty cycle
variance.
Output can have several distinct output levels, and then a
PWM signal summed with that.
Figure: Typical Sigma/Delta signal prior to LPF

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Typical Applications:
Very popular in audio applications.
Digital Cell phones use these widely due to low power
consumption.
Work well at high resolution (12-16 bits)
More Depth on Sigma/Delta see:
"Oversampling Delta-Sigma Data Converters” by Candy and
Temes, IEEE Press, 1991, ISBN 0-87942-258-8
“Delta Sigma Data Converters – Theory Design Simulation” by
Norsworthy, Schreir, Temes, IEEE Press 1997, ISBN 0-7803-
1045-4
Understanding Delta Sigma Data Converters - Schreir, Temes
– Wiley, 2005

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